diff --git a/docs/VLSI/ASAP7-Tutorial.rst b/docs/VLSI/ASAP7-Tutorial.rst index b147d6a5..67165912 100644 --- a/docs/VLSI/ASAP7-Tutorial.rst +++ b/docs/VLSI/ASAP7-Tutorial.rst @@ -30,7 +30,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo * Hammer IR for this tutorial. -* ``example-design.yml``, ``example-nangate45.yml``, ``example-tech.yml`` +* ``example-design.yml``, ``example-sky130.yml``, ``example-tech.yml`` * Hammer IR not used for this tutorial but provided as templates. diff --git a/docs/VLSI/Basic-Flow.rst b/docs/VLSI/Basic-Flow.rst index 8ac01523..610f6958 100644 --- a/docs/VLSI/Basic-Flow.rst +++ b/docs/VLSI/Basic-Flow.rst @@ -42,7 +42,7 @@ Setting up the Hammer Configuration Files The first configuration file that needs to be set up is the Hammer environment configuration file ``env.yml``. In this file you need to set the paths to the EDA tools and license servers you will be using. You do not have to fill all the fields in this configuration file, you only need to fill in the paths for the tools that you will be using. If you are working within a shared server farm environment with an LSF cluster setup (for example, the Berkeley Wireless Research Center), please note the additional possible environment configuration listed in the :ref:`VLSI/Basic-Flow:Advanced Environment Setup` segment of this documentation page. -Hammer relies on YAML-based configuration files. While these configuration can be consolidated within a single files (as is the case in the ASAP7 tutorial :ref:`tutorial` and the ``nangate45`` +Hammer relies on YAML-based configuration files. While these configuration can be consolidated within a single files (as is the case in the ASAP7 tutorial :ref:`tutorial` and the ``sky130`` OpenRoad example), the generally suggested way to work with an arbitrary process technology or tools plugins would be to use three configuration files, matching the three Hammer concerns - tools, tech, and design. The ``vlsi`` directory includes three such example configuration files matching the three concerns: ``example-tools.yml``, ``example-tech.yml``, and ``example-design.yml``. diff --git a/docs/VLSI/Hammer.rst b/docs/VLSI/Hammer.rst index df803b1d..b1d86b1e 100644 --- a/docs/VLSI/Hammer.rst +++ b/docs/VLSI/Hammer.rst @@ -25,6 +25,17 @@ Hooks Hooks are modifications to steps or actions that are programmatically defined in a Hammer configuration. + +VLSI Flow Control +----------------- +Sometimes we want more fine-grained control of the VLSI flow than at the action level. +The Hammer flow supports being able to start/stop before/after any of the steps in a particular action. +See the `Hammer documentation on Flow Control `__ for a full list and description of the options. +The ``Makefile`` in the ``vlsi`` directory passes this extra information via the ``HAMMER_EXTRA_ARGS`` variable. +This variable can also be used to specify additional YAML configurations that may have +changed or been omitted from the inital build. + + Configuration (Hammer IR) ========================= diff --git a/docs/VLSI/Sky130-Tutorial.rst b/docs/VLSI/Sky130-Commercial-Tutorial.rst similarity index 94% rename from docs/VLSI/Sky130-Tutorial.rst rename to docs/VLSI/Sky130-Commercial-Tutorial.rst index 2a9c19b1..cc53c46f 100644 --- a/docs/VLSI/Sky130-Tutorial.rst +++ b/docs/VLSI/Sky130-Commercial-Tutorial.rst @@ -1,8 +1,8 @@ -.. _sky130-tutorial: +.. _sky130-commercial-tutorial: Sky130 Tutorial =============== -The ``vlsi`` folder of this repository contains an example Hammer flow with the SHA-3 accelerator and a dummy hard macro. This example tutorial uses the built-in Sky130 technology plugin and requires access to the included Cadence and Mentor tool plugin submodules. Cadence is necessary for synthesis & place-and-route, while Mentor is needed for DRC & LVS. +The ``vlsi`` folder of this repository contains an example Hammer flow with the TinyRocketConfig from Chipyard. This example tutorial uses the built-in Sky130 technology plugin and requires access to the included Cadence and Mentor tool plugin submodules. Cadence is necessary for synthesis & place-and-route, while Mentor is needed for DRC & LVS. Project Structure ----------------- @@ -30,7 +30,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo * Hammer IR for this tutorial. -* ``example-design.yml``, ``example-nangate45.yml``, ``example-tech.yml`` +* ``example-design.yml``, ``example-asap7.yml``, ``example-tech.yml`` * Hammer IR not used for this tutorial but provided as templates. @@ -45,7 +45,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo Prerequisites ------------- -* Python 3.4+ +* Python 3.6+ * numpy package * Genus, Innovus, Voltus, VCS, and Calibre licenses * Sky130 PDK, install using `these directions `__ diff --git a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst new file mode 100644 index 00000000..54baadbb --- /dev/null +++ b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst @@ -0,0 +1,213 @@ +.. _sky130-openroad-tutorial: + +Sky130 + OpenROAD Tutorial +========================== +The ``vlsi`` folder of this repository contains an example Hammer flow with the TinyRocketConfig from Chipyard. This example tutorial uses the built-in Sky130 technology plugin and OpenROAD tool plugin. + +Project Structure +----------------- + +This example gives a suggested file structure and build system. The ``vlsi/`` folder will eventually contain the following files and folders: + +* ``Makefile``, ``sim.mk``, ``power.mk`` + + * Integration of Hammer's build system into Chipyard and abstracts away some Hammer commands. + +* ``build`` + + * Hammer output directory. Can be changed with the ``OBJ_DIR`` variable. + * Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files. + +* ``example-vlsi-sky130`` + + * Entry point to Hammer. Contains example placeholders for hooks. + +* ``example-sky130.yml``, ``example-openroad.yml`` + + * Hammer IR for this tutorial. + +* ``example-design.yml``, ``example-asap7.yml``, ``example-tech.yml`` + + * Hammer IR not used for this tutorial but provided as templates. + +* ``generated-src`` + + * All of the elaborated Chisel and FIRRTL. + +* ``hammer``, ``hammer/src/hammer-vlsi//``, ``hammer/src/hammer-vlsi/technology/`` + + * Core repository, and open-source tool and technology plugins. + +Prerequisites +------------- + +* Python 3.6+ +* numpy package +* OpenROAD flow tools: + + * Yosys (synthesis), install `from source `__ or `using conda `__ + * OpenROAD (place-and-route), install `from source `__ + * Magic (DRC), install `from source `__ + * NetGen (LVS), install `from source `__ or `using conda `__ + +* Sky130 PDK, install using `these directions `__ + +Initial Setup +------------- +In the Chipyard root, run: + +.. code-block:: shell + + ./scripts/init-vlsi.sh sky130 openroad + +to pull the Hammer submodule. Note that for technologies other than ``sky130`` or ``asap7``, the tech plugin submodule is cloned into the ``vlsi`` folder, +and for the commercial tool flow (set up by omitting the ``openroad`` argument), the tool plugin submodules are cloned into the ``vlsi`` folder. + +Pull the Hammer environment into the shell: + +.. code-block:: shell + + cd vlsi + export HAMMER_HOME=$PWD/hammer + source $HAMMER_HOME/sourceme.sh + +Running the VLSI Flow +--------------------- + +For this tutorial we will be setting the Make variable ``tutorial=sky130-openroad`` to abbreviate the configuration. +The current options for this variable are defined in ``tutorial.mk``, a few of which are summarized as follows: + +* ``CONFIG=TinyRocketConfig`` selects the ``TinyRocketConfig`` from the Chipyard configurations. +* ``tech_name`` sets a few more necessary paths in the ``Makefile``, such as the appropriate Hammer plugin +* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-openroad.yml`` and ``example-sky130.yml``, which are described below +* ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml`` +* ``VLSI_OBJ_DIR`` gives the build directory a unique name to allow running multiple flows in the same repo. + +example-vlsi-sky130 +^^^^^^^^^^^^^^^^^^^ +This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. + + +example-sky130.yml +^^^^^^^^^^^^^^^^^^ +This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom. + +First, set ``technology.sky130.`` to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the +`Sky130 Hammer plugin README `__ +for details about the PDK setup. + + +example-openroad.yml +^^^^^^^^^^^^^^^^^^^^ +This contains the Hammer configuration for the OpenROAD tool flow. +It selects tools for synthesis (Yosys), place and route (OpenROAD), DRC (Magic), and LVS (NetGen). +For the remaining commands, we will need to specify this file as the tool configuration to hammer via the ``TOOLS_CONF`` Makefile variable. + + +Generating SRAMs +^^^^^^^^^^^^^^^^ +To map the generic memory macros in the generarted Verilog to the SRAMs in your technology process, run the following command: + +.. code-block:: shell + + make srams tutorial=sky130-openroad + +Generating Verilog +^^^^^^^^^^^^^^^^^^ +To elaborate the ``TinyRocketConfig`` from Chisel to Verilog, run: + +.. code-block:: shell + + make verilog tutorial=sky130-openroad + +The ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime. The resulting verilog is located in ``./generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.v``. + +Note that in the generated Verilog, there are generic memory macros for the various memory components (dcache, icache, tag array, PTW). +This is the same Verilog that is generated for RTL simulations in the ``~chipyard/sims/verilator`` directory, see :ref:`Simulation/Software-RTL-Simulation:Software RTL Simulation` for directions on how to run these simulations. + +Building the Design +^^^^^^^^^^^^^^^^^^^ +To set up all prerequisites for the build system to push the design and SRAM macros through the flow: + +.. code-block:: shell + + make buildfile tech_name=sky130 TOOLS_CONF=example-openroad.yml CONFIG=TinyRocketConfig + +The command ``make buildfile`` generates a set of Make targets in ``build/hammer.d``. +It needs to be re-run if environment variables are changed. +It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment. + + +Synthesis +^^^^^^^^^ + +.. code-block:: shell + + make syn tutorial=sky130-openroad + +Post-synthesis logs and collateral are in ``build/syn-rundir``. + +.. The raw quality of results data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a work in progress. + +Place-and-Route +^^^^^^^^^^^^^^^ +.. code-block:: shell + + make par tutorial=sky130-openroad + +After completion, the final database can be opened in an interactive OpenROAD session. + +.. code-block:: shell + + cd ./build/par-rundir + ./generated-scripts/open_chip + + +Below is the post-PnR layout for the TinyRocketConfig in Sky130 generated by OpenROAD. + +.. image:: ../_static/images/vlsi-openroad-par-tinyrocketconfig.png + +Intermediate databases are written in ``build/par-rundir`` between each step of the ``par`` action. These databases can be restored in an interactive OpenROAD session as desired for debugging purposes. + +.. code-block:: shell + + openroad # launch OpenROAD tool + openroad> read_db pre_global_route + +.. Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files. + +DRC & LVS +^^^^^^^^^ +To run DRC & LVS: + +.. code-block:: shell + + make drc tutorial=sky130-openroad + make lvs tutorial=sky130-openroad + +Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the +`Sky130 Hammer plugin README `__. + + +VLSI Flow Control +^^^^^^^^^^^^^^^^^ +Firt, refer to the :ref:`VLSI/Hammer:VLSI Flow Control` documentation. The below examples use the ``redo-par`` Make target to re-run only place-and-route. ``redo-`` may be prepended to any of the VLSI flow actions to re-run only that action. + +.. code-block:: shell + + # the following two statements are equivalent because the + # extraction step immediately precedes the write_design step + make redo-par HAMMER_EXTRA_ARGS="--start_after_step extraction" + make redo-par HAMMER_EXTRA_ARGS="--start_before_step write_design" + + # example of re-running only floorplanning to test out a new floorplan configuration + make redo-par HAMMER_EXTRA_ARGS="--only_step floorplan_design -p example-sky130.yml" + +See the `OpenROAD tool plugin `__ for the full list of OpenROAD tool steps and their implementations. + +Documentation +------------- +For more information about Hammer's underlying implementation, visit the `Hammer documentation website `__. + +For details about the plugins used in this tutorial, check out the `OpenROAD tool plugin repo + README `__ +and `Sky130 tech plugin repo + README `__. \ No newline at end of file diff --git a/docs/VLSI/index.rst b/docs/VLSI/index.rst index 1758a65a..727c9310 100644 --- a/docs/VLSI/index.rst +++ b/docs/VLSI/index.rst @@ -12,5 +12,6 @@ In particular, we aim to support the Hammer physical design generator flow. Hammer Basic-Flow ASAP7-Tutorial - Sky130-Tutorial + Sky130-Commercial-Tutorial + Sky130-OpenROAD-Tutorial Advanced-Usage diff --git a/docs/_static/images/vlsi-openroad-par-tinyrocketconfig.png b/docs/_static/images/vlsi-openroad-par-tinyrocketconfig.png new file mode 100644 index 00000000..0d8ce137 Binary files /dev/null and b/docs/_static/images/vlsi-openroad-par-tinyrocketconfig.png differ diff --git a/scripts/init-vlsi.sh b/scripts/init-vlsi.sh index 8b9ed6b2..8613bf61 100755 --- a/scripts/init-vlsi.sh +++ b/scripts/init-vlsi.sh @@ -6,9 +6,11 @@ set -o pipefail # Initialize HAMMER and CAD-plugins git submodule update --init --recursive vlsi/hammer -git submodule update --init --recursive vlsi/hammer-cadence-plugins -git submodule update --init --recursive vlsi/hammer-synopsys-plugins -git submodule update --init --recursive vlsi/hammer-mentor-plugins +if [[ $1 != *openroad* ]] && [[ $2 != *openroad* ]]; then + git submodule update --init --recursive vlsi/hammer-cadence-plugins + git submodule update --init --recursive vlsi/hammer-synopsys-plugins + git submodule update --init --recursive vlsi/hammer-mentor-plugins +fi # Initialize HAMMER tech plugin if [[ $1 != *asap7* ]] && [[ $1 != *sky130* ]]; then diff --git a/vlsi/Makefile b/vlsi/Makefile index 924fa964..80ea52b0 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -12,6 +12,7 @@ sim_dir=$(abspath .) ######################################################################################### # include shared variables ######################################################################################### +include $(vlsi_dir)/tutorial.mk include $(base_dir)/variables.mk ######################################################################################### @@ -30,15 +31,13 @@ ifdef USE_SRAM_COMPILER MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict else MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict -endif +endif ENV_YML ?= $(vlsi_dir)/env.yml -INPUT_CONFS ?= example-tools.yml \ - $(if $(filter $(tech_name),nangate45),\ - example-nangate45.yml,\ - $(if $(filter $(tech_name),asap7),\ - example-asap7.yml,\ - example-sky130.yml)) +TECH_CONF ?= $(if $(filter $(tech_name),asap7), example-asap7.yml,\ + example-sky130.yml)) +TOOLS_CONF ?= example-tools.yml +INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) HAMMER_EXEC ?= $(if $(filter $(tech_name),sky130),\ ./example-vlsi-sky130,\ ./example-vlsi) diff --git a/vlsi/example-designs/sky130-commercial.yml b/vlsi/example-designs/sky130-commercial.yml new file mode 100644 index 00000000..44b30e39 --- /dev/null +++ b/vlsi/example-designs/sky130-commercial.yml @@ -0,0 +1,151 @@ +# Override configurations in ../example-sky130.yml + +# Specify clock signals +vlsi.inputs.clocks: [ + {name: "clock_clock", period: "5ns", uncertainty: "1ns"} +] + +# Power Straps +par.power_straps_mode: generate +par.generate_power_straps_method: by_tracks +par.blockage_spacing: 40.0 +par.blockage_spacing_top_layer: met4 +par.generate_power_straps_options: + by_tracks: + strap_layers: + - met4 + - met5 + pin_layers: + - met5 + blockage_spacing_met2: 4.0 + blockage_spacing_met4: 2.0 + blockage_spacing_met4: 2.0 + track_width: 3 + track_width_met5: 1 + track_spacing: 5 + track_start: 10 + track_start_met5: 1 + power_utilization: 0.1 + power_utilization_met4: 0.1 + power_utilization_met5: 0.1 + +# Placement Constraints +vlsi.inputs.placement_constraints: + - path: "ChipTop" + type: toplevel + x: 0 + y: 0 + width: 4000 + height: 2500 + margins: + left: 0 + right: 0 + top: 0 + bottom: 0 + + # Place data cache SRAM instances + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" + type: hardmacro + x: 50 + y: 100 + orientation: r0 + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" + type: hardmacro + x: 50 + y: 700 + orientation: r0 + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0" + type: hardmacro + x: 50 + y: 1300 + orientation: r0 + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0" + type: hardmacro + x: 50 + y: 1900 + orientation: r0 + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0" + type: hardmacro + x: 1000 + y: 1900 + orientation: r0 + + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0" + type: hardmacro + x: 1000 + y: 1300 + orientation: r0 + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0" + type: hardmacro + x: 1000 + y: 700 + orientation: r0 + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0" + type: hardmacro + x: 1000 + y: 100 + orientation: r0 + + # Place instruction cache SRAM instances + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0" + type: hardmacro + x: 3250 + y: 100 + orientation: r0 + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0" + type: hardmacro + x: 3250 + y: 700 + orientation: r0 + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0" + type: hardmacro + x: 3450 + y: 1300 + orientation: r0 + + # Place L2 TLB SRAM instances + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0" + type: hardmacro + x: 2000 + y: 1300 + orientation: "r0" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1" + type: hardmacro + x: 2000 + y: 1900 + orientation: "r0" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2" + type: hardmacro + x: 2750 + y: 1300 + orientation: "r0" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3" + type: hardmacro + x: 2750 + y: 1900 + orientation: "r0" + + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4" + type: hardmacro + x: 3460 + y: 1900 + orientation: "r0" + +# Pin placement constraints +vlsi.inputs.pin_mode: generated +vlsi.inputs.pin.generate_mode: semi_auto +vlsi.inputs.pin.assignments: [ + {pins: "*", layers: ["met2", "met4"], side: "bottom"} +] diff --git a/vlsi/example-designs/sky130-openroad.yml b/vlsi/example-designs/sky130-openroad.yml new file mode 100644 index 00000000..5bbef50f --- /dev/null +++ b/vlsi/example-designs/sky130-openroad.yml @@ -0,0 +1,90 @@ +# Override configurations in ../example-sky130.yml + +# Specify clock signals +# Relax the clock period for OpenROAD to meet timing +vlsi.inputs.clocks: [ + {name: "clock_clock", period: "30ns", uncertainty: "1ns"} +] + +# Placement Constraints +vlsi.inputs.placement_constraints: + - path: "ChipTop" + type: toplevel + x: 0 + y: 0 + width: 4000 + height: 2500 + margins: + left: 10 + right: 10 + top: 10 + bottom: 10 + + # Place data cache SRAM instances + - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_0" + type: hardmacro + x: 50 + y: 100 + orientation: r0 + + - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_0" + type: hardmacro + x: 50 + y: 700 + orientation: r0 + + - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_0" + type: hardmacro + x: 50 + y: 1300 + orientation: r0 + + - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_0" + type: hardmacro + x: 50 + y: 1900 + orientation: r0 + + - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_4_0" + type: hardmacro + x: 1000 + y: 1900 + orientation: r0 + + + - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_5_0" + type: hardmacro + x: 1000 + y: 1300 + orientation: r0 + + - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_6_0" + type: hardmacro + x: 1000 + y: 700 + orientation: r0 + + - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_7_0" + type: hardmacro + x: 1000 + y: 100 + orientation: r0 + + # Place instruction cache SRAM instances + - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_0_0" + type: hardmacro + x: 3250 + y: 100 + orientation: r0 + + - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_1_0" + type: hardmacro + x: 3250 + y: 700 + orientation: r0 + + - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.tag_array.tag_array_ext.mem_0_0" + type: hardmacro + x: 3450 + y: 1300 + orientation: r0 \ No newline at end of file diff --git a/vlsi/example-designs/sky130-rocket.yml b/vlsi/example-designs/sky130-rocket.yml new file mode 100644 index 00000000..ed1c7bbc --- /dev/null +++ b/vlsi/example-designs/sky130-rocket.yml @@ -0,0 +1,22 @@ +# Override configurations in ../example-sky130.yml and example-designs + +# Specify clock signals +# Rocket/RocketTile names clock signal "clock" instead of "clock_clock" +vlsi.inputs.clocks: [ + {name: "clock", period: "5ns", uncertainty: "1ns"} +] + +# Placement Constraints +# Rocket/RocketTile requires a much smaller footprint +vlsi.inputs.placement_constraints: + - path: "Rocket" + type: toplevel + x: 0 + y: 0 + width: 2500 + height: 1500 + margins: + left: 10 + right: 10 + top: 10 + bottom: 10 \ No newline at end of file diff --git a/vlsi/example-nangate45.yml b/vlsi/example-nangate45.yml deleted file mode 100644 index 5b4a59ea..00000000 --- a/vlsi/example-nangate45.yml +++ /dev/null @@ -1,73 +0,0 @@ -#---------------------- -# Technology Setup -#---------------------- - -vlsi.core.technology: nangate45 - -# the nangate45.tech.json can't reference the $OPENROAD environment variable, -# so we need to set the install dir here. -# TODO: figure out how to remove this, or override it within OpenROADTool -technology.nangate45.install_dir: "/k/work/OpenROAD-flow/tools/OpenROAD" - -vlsi.core.max_threads: 12 - -#---------------------- -# General Hammer Inputs -#---------------------- - -# Hammer will auto-generate a CPF for simple power designs; -# see hammer/src/hammer-vlsi/defaults.yml for more info -vlsi.inputs.power_spec_mode: "auto" -vlsi.inputs.power_spec_type: "cpf" - -# Specify clock signals -vlsi.inputs.clocks: [ - {name: "clock_clock", period: "5ns", uncertainty: "0.5ns"} -] - -# Generate Make include to aid in flow -vlsi.core.build_system: make - -#---------------------- -# Placement Constraints -#---------------------- - -# For nangate45, size should be multiple of (0.19,1.4) placement grid -vlsi.inputs.placement_constraints: - - path: "ChipTop" - type: toplevel - x: 0 - y: 0 - width: 3334.72 - height: 3798.2 - margins: - left: 0 - right: 0 - top: 0 - bottom: 0 - -# SRAM Compiler compiler options -vlsi.core.sram_generator_tool: "sram_compiler" -## You should specify a location for the SRAM generator in the tech plugin -vlsi.core.sram_generator_tool_path: [ - "hammer/src/hammer-vlsi/technology/nangate45"] -vlsi.core.sram_generator_tool_path_meta: "append" - -#---------------------- -# Tool options. Replace with your tool plugin of choice. -#---------------------- - -# OpenROAD-yosys options -vlsi.core.synthesis_tool: "yosys" -vlsi.core.synthesis_tool_path: ["hammer/src/hammer-vlsi/synthesis/yosys"] -vlsi.core.synthesis_tool_path_meta: "append" - -# OpenROAD-par options -vlsi.core.par_tool: "openroad" -vlsi.core.par_tool_path: ["hammer/src/hammer-vlsi/par"] -vlsi.core.par_tool_path_meta: "append" - -# OpenROAD-drc options (no lvs) -vlsi.core.drc_tool: "openroad" -vlsi.core.drc_tool_path: ["hammer/src/hammer-vlsi/drc"] -vlsi.core.drc_tool_path_meta: "append" diff --git a/vlsi/example-openroad.yml b/vlsi/example-openroad.yml index f87afdd8..d555a19e 100644 --- a/vlsi/example-openroad.yml +++ b/vlsi/example-openroad.yml @@ -16,6 +16,7 @@ vlsi.core.par_tool_path_meta: "append" # Magic options vlsi.core.drc_tool: "magic" vlsi.core.drc_tool_path: ["hammer/src/hammer-vlsi/drc"] +drc.magic.magic_bin: "magic" # Netgen options vlsi.core.lvs_tool: "netgen" vlsi.core.lvs_tool_path: ["hammer/src/hammer-vlsi/lvs"] diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml index e8cae39a..ebfc1ae4 100644 --- a/vlsi/example-sky130.yml +++ b/vlsi/example-sky130.yml @@ -6,10 +6,11 @@ vlsi.core.max_threads: 12 # Technology paths technology.sky130: - sky130_pdk: "path-to-skywater-pdk/" - sky130A: "path-to-sky130A/" - sky130_nda: "path-to-skywater-src-nda/" - openram_lib: "path-to-sky130_sram_macros/" + sky130A: "/path/to/sky130A" + openram_lib: "/path/to/sky130_sram_macros" + + # this key is OPTIONAL, no NDA files will be used if it does not point to a valid path + sky130_nda: "/path/to/skywater-src-nda" # General Hammer Inputs @@ -19,16 +20,30 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "130ns", uncertainty: "1ns"} + {name: "clock_clock", period: "10ns", uncertainty: "1ns"} ] # Generate Make include to aid in flow vlsi.core.build_system: make +# Placement Constraints +vlsi.inputs.placement_constraints: + - path: "ChipTop" + type: toplevel + x: 0 + y: 0 + width: 3500 + height: 2500 + margins: + left: 10 + right: 10 + top: 10 + bottom: 10 + # Power Straps par.power_straps_mode: generate par.generate_power_straps_method: by_tracks -par.blockage_spacing: 2.0 +par.blockage_spacing: 40.0 par.blockage_spacing_top_layer: met4 par.generate_power_straps_options: by_tracks: @@ -38,128 +53,16 @@ par.generate_power_straps_options: pin_layers: - met5 blockage_spacing_met2: 4.0 - track_width: 6 - track_width_met5: 2 - track_spacing: 1 + blockage_spacing_met4: 2.0 + blockage_spacing_met4: 2.0 + track_width: 3 + track_width_met5: 1 + track_spacing: 5 track_start: 10 track_start_met5: 1 power_utilization: 0.1 - power_utilization_met4: 0.3 - power_utilization_met5: 0.5 - -# Placement Constraints -vlsi.inputs.placement_constraints: - - path: "ChipTop" - type: toplevel - x: 0 - y: 0 - width: 4500 - height: 2500 - margins: - left: 0 - right: 0 - top: 0 - bottom: 0 - - # Place data cache SRAM instances - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" - type: hardmacro - x: 50 - y: 100 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" - type: hardmacro - x: 50 - y: 700 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0" - type: hardmacro - x: 50 - y: 1300 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0" - type: hardmacro - x: 50 - y: 1900 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0" - type: hardmacro - x: 1000 - y: 1900 - orientation: r0 - - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0" - type: hardmacro - x: 1000 - y: 1300 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0" - type: hardmacro - x: 1000 - y: 700 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0" - type: hardmacro - x: 1000 - y: 100 - orientation: r0 - - # Place instruction cache SRAM instances - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0" - type: hardmacro - x: 3700 - y: 100 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0" - type: hardmacro - x: 3700 - y: 700 - orientation: r0 - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0" - type: hardmacro - x: 3000 - y: 100 - orientation: r0 - - # Place L2 TLB SRAM instances - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0" - type: hardmacro - x: 1900 - y: 1900 - orientation: "r0" - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1" - type: hardmacro - x: 2600 - y: 1900 - orientation: "r0" - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2" - type: hardmacro - x: 3300 - y: 1900 - orientation: "r0" - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3" - type: hardmacro - x: 3950 - y: 1900 - orientation: "r0" - - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4" - type: hardmacro - x: 3950 - y: 1300 - orientation: "r0" + power_utilization_met4: 0.1 + power_utilization_met5: 0.1 # Pin placement constraints vlsi.inputs.pin_mode: generated diff --git a/vlsi/example-vlsi-sky130 b/vlsi/example-vlsi-sky130 index 8aef8ddc..056d5c21 100755 --- a/vlsi/example-vlsi-sky130 +++ b/vlsi/example-vlsi-sky130 @@ -48,7 +48,7 @@ class ExampleDriver(CLIDriver): # hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), # make_post_insertion_hook will execute the custom hook after the specified step - hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings), + # hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings), # make_replacement_hook will replace the specified step with a custom hook # hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells), diff --git a/vlsi/hammer b/vlsi/hammer index 0ddd5dd7..41105f96 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 0ddd5dd7819851e88d2a53628e868c7ddfc43453 +Subproject commit 41105f964fa235820e27136fd0faa87b33c62b2b diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index 08a4a0af..80f0e276 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit 08a4a0af8934525519e722c541c42a79cf3db4f1 +Subproject commit 80f0e276cf6a358f6d38288f5f69ccac41ea22ca diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index 7a8bffb0..7f9ae30e 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit 7a8bffb0c6490526b1c628cc756ea4b1df612e84 +Subproject commit 7f9ae30eb4184c15e0e359601286581198212e77 diff --git a/vlsi/tutorial.mk b/vlsi/tutorial.mk new file mode 100644 index 00000000..1fcd98ef --- /dev/null +++ b/vlsi/tutorial.mk @@ -0,0 +1,36 @@ +######################################################################################### +# makefile variables for Hammer tutorials +######################################################################################### +tutorial ?= none + +# TODO: eventually have asap7 commercial/openroad tutorial flavors +ifeq ($(tutorial),asap7) + tech_name ?= asap7 + CONFIG ?= TinyRocketConfig + TOOLS_CONF ?= example-tools.yml + TECH_CONF ?= example-asap7.yml + INPUT_CONFS ?= $(EXTRA_CONFS) $(TOOLS_CONF) $(TECH_CONF) + VLSI_OBJ_DIR ?= build-asap7-commercial +endif + +ifeq ($(tutorial),sky130-commercial) + tech_name ?= sky130 + CONFIG ?= TinyRocketConfig + TOOLS_CONF ?= example-tools.yml + TECH_CONF ?= example-sky130.yml + DESIGN_CONF ?= example-designs/sky130-commercial.yml + EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, ) + INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS) + VLSI_OBJ_DIR ?= build-sky130-commercial +endif + +ifeq ($(tutorial),sky130-openroad) + tech_name ?= sky130 + CONFIG ?= TinyRocketConfig + TOOLS_CONF ?= example-openroad.yml + TECH_CONF ?= example-sky130.yml + DESIGN_CONF ?= example-designs/sky130-openroad.yml + EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, ) + INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS) + VLSI_OBJ_DIR ?= build-sky130-openroad +endif