From f9faac32fc06b9c823bd7ee388b48f24a769fb53 Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Wed, 3 Jun 2020 17:19:42 -0700 Subject: [PATCH 1/9] [skip ci] Update reference to 'REBAR' in script comment --- scripts/firesim-setup.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/firesim-setup.sh b/scripts/firesim-setup.sh index 959777d7..bb14f39e 100755 --- a/scripts/firesim-setup.sh +++ b/scripts/firesim-setup.sh @@ -1,6 +1,6 @@ #!/usr/bin/env bash -# Sets up FireSim for use as a library within REBAR +# Sets up FireSim for use as a library within Chipyard set -e set -o pipefail From 4bfd89be6b7aa93d418219f2f766cab2aea2db24 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Thu, 11 Jun 2020 11:18:34 -0700 Subject: [PATCH 2/9] Use an accurate name for the ci skip list --- .githooks/ignore-certain-dirs-commit-msg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.githooks/ignore-certain-dirs-commit-msg b/.githooks/ignore-certain-dirs-commit-msg index 3ab0e7b4..8756b916 100644 --- a/.githooks/ignore-certain-dirs-commit-msg +++ b/.githooks/ignore-certain-dirs-commit-msg @@ -8,9 +8,9 @@ fi changes=( `git diff --name-only --cached` ) # Load the patterns we want to skip into an array -mapfile -t blacklist < .ciignore +mapfile -t blocklist < .ciignore -for i in "${blacklist[@]}" +for i in "${blocklist[@]}" do # Remove the current pattern from the list of changes changes=( ${changes[@]/$i/} ) From d245df91338c2dfcba34fdb6c8d5cecdc8415c82 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 18 Jun 2020 10:48:32 -0700 Subject: [PATCH 3/9] Bump Rocketchip to June 2020 for Tile changes --- generators/ariane | 2 +- generators/boom | 2 +- .../src/main/scala/ConfigFragments.scala | 86 +++----- .../chipyard/src/main/scala/DigitalTop.scala | 4 +- .../chipyard/src/main/scala/IOBinders.scala | 4 +- .../chipyard/src/main/scala/Subsystem.scala | 87 ++------ .../chipyard/src/main/scala/System.scala | 6 +- .../chipyard/src/main/scala/TestSuites.scala | 192 ++++++++++-------- .../src/main/scala/config/BoomConfigs.scala | 45 +--- .../src/main/scala/config/HeteroConfigs.scala | 70 +------ .../main/scala/config/TracegenConfigs.scala | 10 +- .../main/scala/config/TutorialConfigs.scala | 9 +- .../src/main/scala/BridgeBinders.scala | 11 +- .../src/main/scala/FireSimMulticlockPOC.scala | 20 +- .../src/main/scala/TargetConfigs.scala | 10 +- generators/rocket-chip | 2 +- generators/testchipip | 2 +- .../tracegen/src/main/scala/Configs.scala | 183 ++++++++++------- .../tracegen/src/main/scala/System.scala | 50 ++--- generators/tracegen/src/main/scala/Tile.scala | 114 +++++------ tools/dsptools | 2 +- 21 files changed, 375 insertions(+), 536 deletions(-) diff --git a/generators/ariane b/generators/ariane index 651134f3..0ed91074 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit 651134f3c43ff8c0fa55a0f65faeb12b9500fcfa +Subproject commit 0ed9107485281545bf5abf2a042dface55e740bf diff --git a/generators/boom b/generators/boom index d77c2c3f..0b60c278 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit d77c2c3ff648bd5b18a932aa9f6b64dead7e3476 +Subproject commit 0b60c27879f8aa309537d5a535ea2c42e3dabefe diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 72eaa414..ad33fa47 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -4,20 +4,23 @@ import chisel3._ import chisel3.util.{log2Up} import freechips.rocketchip.config.{Field, Parameters, Config} -import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, CacheBlockBytes} +import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.debug.{Debug} -import freechips.rocketchip.tile.{XLen, BuildRoCC, TileKey, LazyRoCC, RocketTileParams, MaxHartIdBits} +import freechips.rocketchip.groundtest.{GroundTestSubsystem} +import freechips.rocketchip.tile._ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams} import freechips.rocketchip.util.{AsyncResetReg} -import boom.common.{BoomTilesKey} -import ariane.{ArianeTilesKey} import testchipip._ +import tracegen.{TraceGenSystem} import hwacha.{Hwacha} +import boom.common.{BoomTileAttachParams} +import ariane.{ArianeTileAttachParams} + import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ @@ -60,26 +63,17 @@ class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => }) class WithL2TLBs(entries: Int) extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( - core = tile.core.copy(nL2TLBEntries = entries) - )) - case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy( - core = tile.core.copy(nL2TLBEntries = entries) - )) + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nL2TLBEntries = entries))) + case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nL2TLBEntries = entries))) + case other => other + } }) class WithTracegenSystem extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => LazyModule(new tracegen.TraceGenSystem()(p)) -}) - -class WithRenumberHarts(rocketFirst: Boolean = false) extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) => - r.copy(hartId = i + (if(rocketFirst) 0 else up(BoomTilesKey, site).length)) - } - case BoomTilesKey => up(BoomTilesKey, site).zipWithIndex map { case (b, i) => - b.copy(hartId = i + (if(rocketFirst) up(RocketTilesKey, site).length else 0)) - } - case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size) + case BuildSystem => (p: Parameters) => LazyModule(new TraceGenSystem()(p)) }) /** @@ -107,7 +101,6 @@ class WithMultiRoCC extends Config((site, here, up) => { */ class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => { case MultiRoCCKey => { - require(harts.max <= ((up(RocketTilesKey, site).length + up(BoomTilesKey, site).length) - 1)) up(MultiRoCCKey, site) ++ harts.distinct.map{ i => (i -> Seq((p: Parameters) => { LazyModule(new Hwacha()(p)).suggestName("hwacha") @@ -117,38 +110,23 @@ class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => { }) -/** - * Config fragment to add a small Rocket core to the system as a "control" core. - * Used as an example of a PMU core. - */ -class WithControlCore extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey, site) :+ - RocketTileParams( - core = RocketCoreParams( - useVM = false, - fpu = None, - mulDiv = Some(MulDivParams(mulUnroll = 8))), - btb = None, - dcache = Some(DCacheParams( - rowBits = site(SystemBusKey).beatBits, - nSets = 64, - nWays = 1, - nTLBEntries = 4, - nMSHRs = 0, - blockBytes = site(CacheBlockBytes))), - icache = Some(ICacheParams( - rowBits = site(SystemBusKey).beatBits, - nSets = 64, - nWays = 1, - nTLBEntries = 4, - blockBytes = site(CacheBlockBytes))), - hartId = up(RocketTilesKey, site).size + up(BoomTilesKey, site).size - ) - case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1) -}) - class WithTraceIO extends Config((site, here, up) => { - case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) - case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true)) + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + trace = true)) + case tp: ArianeTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + trace = true)) + case other => other + } case TracePortKey => Some(TracePortParams()) }) + +class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nPerfCounters = n))) + case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(nPerfCounters = n))) + case other => other + } +}) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index ae363539..81d0003d 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.devices.tilelink._ // ------------------------------------ // DOC include start: DigitalTop -class DigitalTop(implicit p: Parameters) extends System +class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device @@ -30,7 +30,7 @@ class DigitalTop(implicit p: Parameters) extends System override lazy val module = new DigitalTopModule(this) } -class DigitalTopModule[+L <: DigitalTop](l: L) extends SystemModule(l) +class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with testchipip.CanHaveTraceIOModuleImp with testchipip.CanHavePeripheryBlockDeviceModuleImp with testchipip.CanHavePeripherySerialModuleImp diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 94fb50f4..7d1ae8fa 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -11,6 +11,7 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system.{SimAXIMem} import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4EdgeParameters} import freechips.rocketchip.util._ +import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ @@ -20,7 +21,6 @@ import barstools.iocell.chisel._ import testchipip._ import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey} -import tracegen.{HasTraceGenTilesModuleImp} import scala.reflect.{ClassTag} @@ -389,7 +389,7 @@ class WithSimSerial extends OverrideIOBinder({ }) class WithTraceGenSuccessBinder extends OverrideIOBinder({ - (system: HasTraceGenTilesModuleImp) => { + (system: GroundTestSubsystemModuleImp[GroundTestSubsystem]) => { val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success")) successPort.suggestName("success") val harnessFn = (th: chipyard.TestHarness) => { when (successPort) { th.success := true.B }; Nil } diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 99c31472..baed154b 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -21,93 +21,36 @@ import freechips.rocketchip.util._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.amba.axi4._ -import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} -import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} +import boom.common.{BoomTile} + import testchipip.{DromajoHelper} -trait HasChipyardTiles extends HasTiles - with CanHavePeripheryPLIC - with CanHavePeripheryCLINT - with HasPeripheryDebug -{ this: BaseSubsystem => - - val module: HasChipyardTilesModuleImp - - protected val rocketTileParams = p(RocketTilesKey) - protected val boomTileParams = p(BoomTilesKey) - protected val arianeTileParams = p(ArianeTilesKey) - - // crossing can either be per tile or global (aka only 1 crossing specified) - private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) - private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size) - private val arianeCrossings = perTileOrGlobalSetting(p(ArianeCrossingKey), arianeTileParams.size) - - val allTilesInfo = (rocketTileParams ++ boomTileParams ++ arianeTileParams) zip (rocketCrossings ++ boomCrossings ++ arianeCrossings) - - // Make a tile and wire its nodes into the system, - // according to the specified type of clock crossing. - // Note that we also inject new nodes into the tile itself, - // also based on the crossing type. - // This MUST be performed in order of hartid - // There is something weird with registering tile-local interrupt controllers to the CLINT. - // TODO: investigate why - val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map { - case (param, crossing) => { - - val tile = param match { - case r: RocketTileParams => { - LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode)) - } - case b: BoomTileParams => { - LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode)) - } - case a: ArianeTileParams => { - LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode)) - } - } - connectMasterPortsToSBus(tile, crossing) - connectSlavePortsToCBus(tile, crossing) - connectInterrupts(tile, debugOpt, clintOpt, plicOpt) - - tile - } - } - - +class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem + with HasTiles +{ def coreMonitorBundles = tiles.map { case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle case b: BoomTile => b.module.core.coreMonitorBundle }.toList + override lazy val module = new ChipyardSubsystemModuleImp(this) } -trait HasChipyardTilesModuleImp extends HasTilesModuleImp - with HasPeripheryDebugModuleImp -{ - val outer: HasChipyardTiles -} - -class Subsystem(implicit p: Parameters) extends BaseSubsystem - with HasChipyardTiles -{ - override lazy val module = new SubsystemModuleImp(this) - - def getOMInterruptDevice(resourceBindingsMap: ResourceBindingsMap): Seq[OMInterrupt] = Nil -} - -class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) +class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) with HasResetVectorWire - with HasChipyardTilesModuleImp + with HasTilesModuleImp { - tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) => - wire.hartid := i.U + + for (i <- 0 until outer.tiles.size) { + val wire = tile_inputs(i) + wire.hartid := outer.hartIdList(i).U wire.reset_vector := global_reset_vector } - // create file with boom params + // create file with core params ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n")) - // Generate C header with relevant information for Dromajo // This is included in the `dromajo_params.h` header file - DromajoHelper.addArtefacts + DromajoHelper.addArtefacts() } + diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index 222ff77c..b0ae8a44 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -21,20 +21,20 @@ import freechips.rocketchip.util.{DontTouch} /** * Base top with periphery devices and ports, and a BOOM + Rocket subsystem */ -class System(implicit p: Parameters) extends Subsystem +class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem with HasAsyncExtInterrupts with CanHaveMasterAXI4MemPort with CanHaveMasterAXI4MMIOPort with CanHaveSlaveAXI4Port with HasPeripheryBootROM { - override lazy val module = new SystemModule(this) + override lazy val module = new ChipyardSystemModule(this) } /** * Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem */ -class SystemModule[+L <: System](_outer: L) extends SubsystemModuleImp(_outer) +class ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer) with HasRTCModuleImp with HasExtInterruptsModuleImp with HasPeripheryBootROMModuleImp diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 9fdef05a..6edf4b03 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -2,13 +2,13 @@ package chipyard import scala.collection.mutable.{LinkedHashSet} -import freechips.rocketchip.subsystem.{RocketTilesKey} +import freechips.rocketchip.subsystem._ import freechips.rocketchip.tile.{XLen} import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite} -import boom.common.{BoomTilesKey} -import ariane.{ArianeTilesKey} +import boom.common.{BoomTileAttachParams} +import ariane.{ArianeTileAttachParams} /** * A set of pre-chosen regression tests @@ -68,39 +68,43 @@ class TestSuiteHelper */ def addBoomTestSuites(implicit p: Parameters) = { val xlen = p(XLen) - p(BoomTilesKey).find(_.hartId == 0).map { tileParams => - val coreParams = tileParams.core - val vm = coreParams.useVM - val env = if (vm) List("p","v") else List("p") - coreParams.fpu foreach { case cfg => - if (xlen == 32) { - addSuites(env.map(rv32uf)) - if (cfg.fLen >= 64) { - addSuites(env.map(rv32ud)) + p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map { + case tp: BoomTileAttachParams => { + val tileParams = tp.tileParams + val coreParams = tileParams.core + val vm = coreParams.useVM + val env = if (vm) List("p","v") else List("p") + coreParams.fpu foreach { case cfg => + if (xlen == 32) { + addSuites(env.map(rv32uf)) + if (cfg.fLen >= 64) { + addSuites(env.map(rv32ud)) + } + } else if (cfg.fLen >= 64) { + addSuites(env.map(rv64ud)) + addSuites(env.map(rv64uf)) + addSuite(rv32udBenchmarks) } - } else if (cfg.fLen >= 64) { - addSuites(env.map(rv64ud)) - addSuites(env.map(rv64uf)) - addSuite(rv32udBenchmarks) } - } - if (coreParams.useAtomics) { - if (tileParams.dcache.flatMap(_.scratch).isEmpty) { - addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) - } else { - addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + if (coreParams.useAtomics) { + if (tileParams.dcache.flatMap(_.scratch).isEmpty) { + addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + } else { + addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + } } - } - if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) - val (rvi, rvu) = - if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) - else ((if (vm) rv32i else rv32pi), rv32u) + if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) - addSuites(rvi.map(_("p"))) - addSuites(rvu.map(_("p"))) - addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) - addSuite(benchmarks) - addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + addSuites(rvi.map(_("p"))) + addSuites(rvu.map(_("p"))) + addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + addSuite(benchmarks) + addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + } + case _ => } } @@ -109,37 +113,41 @@ class TestSuiteHelper */ def addRocketTestSuites(implicit p: Parameters) = { val xlen = p(XLen) - p(RocketTilesKey).find(_.hartId == 0).map { tileParams => - val coreParams = tileParams.core - val vm = coreParams.useVM - val env = if (vm) List("p","v") else List("p") - coreParams.fpu foreach { case cfg => - if (xlen == 32) { - addSuites(env.map(rv32uf)) - if (cfg.fLen >= 64) - addSuites(env.map(rv32ud)) - } else { - addSuite(rv32udBenchmarks) - addSuites(env.map(rv64uf)) - if (cfg.fLen >= 64) - addSuites(env.map(rv64ud)) + p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map { + case tp: RocketTileAttachParams => { + val tileParams = tp.tileParams + val coreParams = tileParams.core + val vm = coreParams.useVM + val env = if (vm) List("p","v") else List("p") + coreParams.fpu foreach { case cfg => + if (xlen == 32) { + addSuites(env.map(rv32uf)) + if (cfg.fLen >= 64) + addSuites(env.map(rv32ud)) + } else { + addSuite(rv32udBenchmarks) + addSuites(env.map(rv64uf)) + if (cfg.fLen >= 64) + addSuites(env.map(rv64ud)) + } } - } - if (coreParams.useAtomics) { - if (tileParams.dcache.flatMap(_.scratch).isEmpty) - addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) - else - addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) - } - if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) - val (rvi, rvu) = - if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) - else ((if (vm) rv32i else rv32pi), rv32u) + if (coreParams.useAtomics) { + if (tileParams.dcache.flatMap(_.scratch).isEmpty) + addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + else + addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + } + if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) - addSuites(rvi.map(_("p"))) - addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) - addSuite(benchmarks) - addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + addSuites(rvi.map(_("p"))) + addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + addSuite(benchmarks) + addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + } + case _ => } } @@ -148,37 +156,41 @@ class TestSuiteHelper */ def addArianeTestSuites(implicit p: Parameters) = { val xlen = p(XLen) - p(ArianeTilesKey).find(_.hartId == 0).map { tileParams => - val coreParams = tileParams.core - val vm = coreParams.useVM - val env = if (vm) List("p","v") else List("p") - coreParams.fpu foreach { case cfg => - if (xlen == 32) { - addSuites(env.map(rv32uf)) - if (cfg.fLen >= 64) - addSuites(env.map(rv32ud)) - } else { - addSuite(rv32udBenchmarks) - addSuites(env.map(rv64uf)) - if (cfg.fLen >= 64) - addSuites(env.map(rv64ud)) + p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map { + case tp: ArianeTileAttachParams => { + val tileParams = tp.tileParams + val coreParams = tileParams.core + val vm = coreParams.useVM + val env = if (vm) List("p","v") else List("p") + coreParams.fpu foreach { case cfg => + if (xlen == 32) { + addSuites(env.map(rv32uf)) + if (cfg.fLen >= 64) + addSuites(env.map(rv32ud)) + } else { + addSuite(rv32udBenchmarks) + addSuites(env.map(rv64uf)) + if (cfg.fLen >= 64) + addSuites(env.map(rv64ud)) + } } - } - if (coreParams.useAtomics) { - if (tileParams.dcache.flatMap(_.scratch).isEmpty) - addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) - else - addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) - } - if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) - val (rvi, rvu) = - if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) - else ((if (vm) rv32i else rv32pi), rv32u) + if (coreParams.useAtomics) { + if (tileParams.dcache.flatMap(_.scratch).isEmpty) + addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + else + addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + } + if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) - addSuites(rvi.map(_("p"))) - addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) - addSuite(benchmarks) - addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + addSuites(rvi.map(_("p"))) + addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + addSuite(benchmarks) + addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + } + case _ => } } } diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index e8358e95..7b66e3b3 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -20,8 +20,7 @@ class SmallBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new boom.common.WithSmallBooms ++ // small boom config - new boom.common.WithNBoomCores(1) ++ // single-core boom + new boom.common.WithNSmallBooms(1) ++ // small boom config new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system @@ -39,8 +38,7 @@ class MediumBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithMediumBooms ++ // medium boom config - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNMediumBooms(1) ++ // medium boom config new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -58,8 +56,7 @@ class LargeBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithLargeBooms ++ // large boom config - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNLargeBooms(1) ++ // large boom config new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -77,8 +74,7 @@ class MegaBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithMegaBooms ++ // mega boom config - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNMegaBooms(1) ++ // mega boom config new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -96,29 +92,7 @@ class DualSmallBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithSmallBooms ++ - new boom.common.WithNBoomCores(2) ++ // 2 boom cores - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) - -class SmallRV32BoomConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithoutBoomFPU ++ // no fp - new boom.common.WithBoomRV32 ++ // rv32 (32bit) - new boom.common.WithSmallBooms ++ - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNSmallBooms(2) ++ // 2 boom cores new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -137,8 +111,7 @@ class HwachaLargeBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNLargeBooms(1) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -158,8 +131,7 @@ class LoopbackNICLargeBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNLargeBooms(1) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -179,8 +151,7 @@ class DromajoBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new boom.common.WithSmallBooms ++ - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNSmallBooms(1) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala index 4388ca2b..a7d1c133 100644 --- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala @@ -16,9 +16,7 @@ class LargeBoomAndRocketConfig extends Config( new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs - new chipyard.config.WithRenumberHarts ++ // avoid hartid overlap - new boom.common.WithLargeBooms ++ // 3-wide boom - new boom.common.WithNBoomCores(1) ++ // single-core boom + new boom.common.WithNLargeBooms(1) ++ // single-core boom new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache @@ -39,9 +37,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config( new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts - new chipyard.config.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNLargeBooms(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ @@ -50,28 +46,6 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config( new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: BoomAndRocketWithHwacha - -class DualLargeBoomAndRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new chipyard.config.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(2) ++ // 2 boom cores - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) - // DOC include start: DualBoomAndRocketOneHwacha class LargeBoomAndHwachaRocketConfig extends Config( @@ -84,11 +58,9 @@ class LargeBoomAndHwachaRocketConfig extends Config( new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc - new chipyard.config.WithMultiRoCCHwacha(1) ++ // put hwacha on hart-2 (rocket) + new chipyard.config.WithMultiRoCCHwacha(1) ++ // put hwacha on hart-1 (rocket) new chipyard.config.WithL2TLBs(1024) ++ - new chipyard.config.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(1) ++ + new boom.common.WithNLargeBooms(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ @@ -99,30 +71,6 @@ class LargeBoomAndHwachaRocketConfig extends Config( // DOC include end: DualBoomAndRocketOneHwacha - -class LargeBoomAndRV32RocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithBlackBoxSimMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new chipyard.config.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(1) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) - - // DOC include start: DualBoomAndRocket class DualLargeBoomAndDualRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ @@ -134,9 +82,7 @@ class DualLargeBoomAndDualRocketConfig extends Config( new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ - new chipyard.config.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(2) ++ // 2 boom cores + new boom.common.WithNLargeBooms(2) ++ // 2 boom cores new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ @@ -155,11 +101,9 @@ class LargeBoomAndRocketWithControlCoreConfig extends Config( new testchipip.WithTSI ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ - new chipyard.config.WithControlCore ++ // add small control core to last hartid new chipyard.config.WithL2TLBs(1024) ++ - new chipyard.config.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // Add a small control core + new boom.common.WithNLargeBooms(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index 2a31293f..ec834f9f 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -7,7 +7,7 @@ class TraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ - new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ + new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -15,7 +15,7 @@ class NonBlockingTraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ - new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ + new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -23,7 +23,7 @@ class BoomTraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ - new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ + new tracegen.WithBoomTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -32,7 +32,7 @@ class NonBlockingTraceGenL2Config extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ - new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ + new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -41,7 +41,7 @@ class NonBlockingTraceGenL2RingConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ - new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ + new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new testchipip.WithRingSystemBus ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index c11d103d..56e6362b 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -30,15 +30,13 @@ class TutorialStarterConfig extends Config( // of the Top new testchipip.WithTSI ++ // Add a TSI (Test Serial Interface) widget to bring-up the core new chipyard.config.WithBootROM ++ // Use the Chipyard BootROM - new chipyard.config.WithRenumberHarts ++ // WithRenumberHarts fixes hartids heterogeneous designs, if design is not heterogeneous, this is a no-op new chipyard.config.WithUART ++ // Add a UART // CUSTOMIZE THE CORE // Uncomment out one (or multiple) of the lines below, and choose // how many cores you want. - // new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Specify we want some number of Rocket cores - // new boom.common.WithSmallBooms ++ // Specify all BOOM cores should be Small-sized (NOTE: other options are Medium/Large/Mega) - // new boom.common.WithNBoomCores(1) ++ // Specify we want some number of BOOM cores + // new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Specify we want some number of Rocket cores + // new boom.common.WithNSmallBooms(1) ++ // Specify we want some number of BOOM cores // CUSTOMIZE the L2 // Uncomment this line, and specify a size if you want to have a L2 @@ -66,7 +64,6 @@ class TutorialMMIOConfig extends Config( new testchipip.WithTSI ++ new chipyard.config.WithBootROM ++ - new chipyard.config.WithRenumberHarts ++ new chipyard.config.WithUART ++ // Attach either a TileLink or AXI4 version of GCD @@ -94,7 +91,6 @@ class TutorialSha3Config extends Config( new testchipip.WithTSI ++ new chipyard.config.WithBootROM ++ - new chipyard.config.WithRenumberHarts ++ new chipyard.config.WithUART ++ // Uncomment this line once you added SHA3 to the build.sbt, and cloned the SHA3 repo @@ -120,7 +116,6 @@ class TutorialSha3BlackBoxConfig extends Config( new testchipip.WithTSI ++ new chipyard.config.WithBootROM ++ - new chipyard.config.WithRenumberHarts ++ new chipyard.config.WithUART ++ // Uncomment these lines once SHA3 is integrated diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 772d0b8d..eeb19559 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -8,7 +8,7 @@ import chisel3.experimental.annotate import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp} -import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem} +import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp} import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} @@ -21,13 +21,12 @@ import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig} import midas.targetutils.{MemModelAnnotation} import firesim.bridges._ import firesim.configs.MemModelKey -import tracegen.HasTraceGenTilesModuleImp +import tracegen.{TraceGenSystemModuleImp} import ariane.ArianeTile import boom.common.{BoomTile} import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder} -import chipyard.{HasChipyardTilesModuleImp} import testchipip.{CanHaveTraceIOModuleImp} object MainMemoryConsts { @@ -88,12 +87,12 @@ class WithDromajoBridge extends ComposeIOBinder({ class WithTraceGenBridge extends OverrideIOBinder({ - (system: HasTraceGenTilesModuleImp) => + (system: TraceGenSystemModuleImp) => GroundTestBridge(system.clock, system.success)(system.p); Nil }) class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ - (system: HasChipyardTilesModuleImp) => { + (system: HasTilesModuleImp) => { system.outer.tiles.map { case r: RocketTile => { annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) @@ -110,7 +109,7 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ case _ => Nil } } - case a: ArianeTile => Nil + case _ => } Nil } diff --git a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala index 1f1ae06a..bf0e0e26 100644 --- a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala +++ b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala @@ -9,11 +9,11 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, RationalCrossi import freechips.rocketchip.subsystem._ import freechips.rocketchip.util.{ResetCatchAndSync} -import boom.common.{BoomTilesKey, BoomCrossingKey} - import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock} import firesim.configs._ +import boom.common.{WithRationalBoomTiles} + import chipyard.{BuildSystem, DigitalTop, DigitalTopModule} import chipyard.config.ConfigValName._ import chipyard.iobinders.{IOBinders} @@ -51,15 +51,13 @@ trait HasFireSimClockingImp extends HasAdditionalClocks { } // Config Fragment -class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config((site, here, up) => { - case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor))) - case RocketCrossingKey => up(RocketCrossingKey, site) map { r => - r.copy(crossingType = RationalCrossing()) - } - case BoomCrossingKey => up(BoomCrossingKey, site) map { r => - r.copy(crossingType = RationalCrossing()) - } -}) +class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config( + new WithRationalRocketTiles ++ + new WithRationalBoomTiles ++ + new Config((site, here, up) => { + case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor))) + }) +) class HalfRateUncore extends WithSingleRationalTileDomain(2,1) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 63b4d2fe..2828580a 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -13,13 +13,11 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} import freechips.rocketchip.diplomacy.LazyModule -import boom.common.BoomTilesKey import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import scala.math.{min, max} -import tracegen.TraceGenKey + import icenet._ -import ariane.ArianeTilesKey import testchipip.WithRingSystemBus import firesim.bridges._ @@ -44,12 +42,6 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq)) }) -class WithPerfCounters extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( - core = tile.core.copy(nPerfCounters = 29) - )) -}) - // Disables clock-gating; doesn't play nice with our FAME-1 pass class WithoutClockGating extends Config((site, here, up) => { case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false)) diff --git a/generators/rocket-chip b/generators/rocket-chip index 1872f5d5..1cec6e69 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 1872f5d501221f13950aa2293939634a1e0d1735 +Subproject commit 1cec6e697ce9ea8ffa13a6d95e0734946db3adb1 diff --git a/generators/testchipip b/generators/testchipip index bb038fea..26891fac 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit bb038feaa1db73bffb3fca55c6d24cb0109875bd +Subproject commit 26891fac1d40c31348b6e6f16d730de705707094 diff --git a/generators/tracegen/src/main/scala/Configs.scala b/generators/tracegen/src/main/scala/Configs.scala index c22b0e3d..01b23b24 100644 --- a/generators/tracegen/src/main/scala/Configs.scala +++ b/generators/tracegen/src/main/scala/Configs.scala @@ -3,87 +3,126 @@ package tracegen import chisel3._ import chisel3.util.log2Ceil import freechips.rocketchip.config.{Config, Parameters} -import freechips.rocketchip.groundtest.{TraceGenParams} -import freechips.rocketchip.subsystem.{ExtMem, SystemBusKey, WithInclusiveCache, InclusiveCacheKey} +import freechips.rocketchip.groundtest.{TraceGenParams, TraceGenTileAttachParams} +import freechips.rocketchip.subsystem._ import freechips.rocketchip.system.BaseConfig import freechips.rocketchip.rocket.DCacheParams import freechips.rocketchip.tile.{MaxHartIdBits, XLen} import scala.math.{max, min} -class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) - extends Config((site, here, up) => { - case TraceGenKey => params.map { dcp => TraceGenParams( - dcache = Some(dcp), - wordBits = site(XLen), - addrBits = 48, - addrBag = { - val nSets = dcp.nSets - val nWays = dcp.nWays - val blockOffset = site(SystemBusKey).blockOffset - val nBeats = min(2, site(SystemBusKey).blockBeats) - val beatBytes = site(SystemBusKey).beatBytes - List.tabulate(2 * nWays) { i => - Seq.tabulate(nBeats) { j => - BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) - } - }.flatten - }, - maxRequests = nReqs, - memStart = site(ExtMem).get.master.base, - numGens = params.size) +class WithTraceGen( + n: Int = 2, + overrideIdOffset: Option[Int] = None, + overrideMemOffset: Option[BigInt] = None)( + params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) }, + nReqs: Int = 8192 +) extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => { + val prev = up(TilesLocated(InSubsystem), site) + val idOffset = overrideIdOffset.getOrElse(prev.size) + val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L) + params.zipWithIndex.map { case (dcp, i) => + TraceGenTileAttachParams( + tileParams = TraceGenParams( + hartId = i + idOffset, + dcache = Some(dcp), + wordBits = site(XLen), + addrBits = 48, + addrBag = { + val nSets = dcp.nSets + val nWays = dcp.nWays + val blockOffset = site(SystemBusKey).blockOffset + val nBeats = min(2, site(SystemBusKey).blockBeats) + val beatBytes = site(SystemBusKey).beatBytes + List.tabulate(2 * nWays) { i => + Seq.tabulate(nBeats) { j => + BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) + } + }.flatten + }, + maxRequests = nReqs, + memStart = memOffset, + numGens = params.size), + crossingParams = RocketCrossingParams() + ) + } ++ prev } - case MaxHartIdBits => log2Ceil(params.size + up(BoomTraceGenKey, site).length) max 1 }) -class WithBoomTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) - extends Config((site, here, up) => { - case BoomTraceGenKey => params.map { dcp => TraceGenParams( - dcache = Some(dcp), - wordBits = site(XLen), - addrBits = 48, - addrBag = { - val nSets = dcp.nSets - val nWays = dcp.nWays - val blockOffset = site(SystemBusKey).blockOffset - val nBeats = min(2, site(SystemBusKey).blockBeats) - val beatBytes = site(SystemBusKey).beatBytes - List.tabulate(2 * nWays) { i => - Seq.tabulate(nBeats) { j => - BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) - } - }.flatten - }, - maxRequests = nReqs, - memStart = site(ExtMem).get.master.base, - numGens = params.size) +class WithBoomTraceGen( + n: Int = 2, + overrideIdOffset: Option[Int] = None, + overrideMemOffset: Option[BigInt] = None)( + params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) }, + nReqs: Int = 8192 +) extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => { + val prev = up(TilesLocated(InSubsystem), site) + val idOffset = overrideIdOffset.getOrElse(prev.size) + val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L) + params.zipWithIndex.map { case (dcp, i) => + BoomTraceGenTileAttachParams( + tileParams = BoomTraceGenParams( + hartId = i + idOffset, + dcache = Some(dcp), + wordBits = site(XLen), + addrBits = 48, + addrBag = { + val nSets = dcp.nSets + val nWays = dcp.nWays + val blockOffset = site(SystemBusKey).blockOffset + val nBeats = site(SystemBusKey).blockBeats + List.tabulate(nWays) { i => + Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) } + }.flatten + }, + maxRequests = nReqs, + memStart = memOffset, + numGens = params.size), + crossingParams = RocketCrossingParams() + ) + } ++ prev } - case MaxHartIdBits => log2Ceil(params.size + up(TraceGenKey, site).length) max 1 }) -class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) - extends Config((site, here, up) => { - case TraceGenKey => params.map { dcp => TraceGenParams( - dcache = Some(dcp), - wordBits = site(XLen), - addrBits = 48, - addrBag = { - val sbp = site(SystemBusKey) - val l2p = site(InclusiveCacheKey) - val nSets = max(l2p.sets, dcp.nSets) - val nWays = max(l2p.ways, dcp.nWays) - val blockOffset = sbp.blockOffset - val nBeats = min(2, sbp.blockBeats) - val beatBytes = sbp.beatBytes - List.tabulate(2 * nWays) { i => - Seq.tabulate(nBeats) { j => - BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) - } - }.flatten - }, - maxRequests = nReqs, - memStart = site(ExtMem).get.master.base, - numGens = params.size) - } - case MaxHartIdBits => if (params.size == 1) 1 else log2Ceil(params.size) -}) +class WithL2TraceGen( + n: Int = 2, + overrideIdOffset: Option[Int] = None, + overrideMemOffset: Option[BigInt] = None)( + params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) }, + nReqs: Int = 8192 +) extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => { + val prev = up(TilesLocated(InSubsystem), site) + val idOffset = overrideIdOffset.getOrElse(prev.size) + val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L) + params.zipWithIndex.map { case (dcp, i) => + TraceGenTileAttachParams( + tileParams = TraceGenParams( + hartId = i + idOffset, + dcache = Some(dcp), + wordBits = site(XLen), + addrBits = 48, + addrBag = { + val sbp = site(SystemBusKey) + val l2p = site(InclusiveCacheKey) + val nSets = max(l2p.sets, dcp.nSets) + val nWays = max(l2p.ways, dcp.nWays) + val blockOffset = sbp.blockOffset + val nBeats = min(2, sbp.blockBeats) + val beatBytes = sbp.beatBytes + List.tabulate(2 * nWays) { i => + Seq.tabulate(nBeats) { j => + BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) + } + }.flatten + }, + maxRequests = nReqs, + memStart = memOffset, + numGens = params.size), + crossingParams = RocketCrossingParams() + ) + } ++ prev + } +}) diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index 1653ba79..d6b72d4a 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -3,48 +3,26 @@ package tracegen import chisel3._ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams} -import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams} +import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple} +import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile} import freechips.rocketchip.subsystem._ -case object BoomTraceGenKey extends Field[Seq[TraceGenParams]](Nil) -case object TraceGenKey extends Field[Seq[TraceGenParams]](Nil) - -trait HasTraceGenTiles { this: BaseSubsystem => - val rocket_tiles = p(TraceGenKey).zipWithIndex.map { case (params, i) => - LazyModule(new TraceGenTile(i, params, p)) - } - val boom_tiles = p(BoomTraceGenKey).zipWithIndex.map { case (params, i) => - LazyModule(new BoomTraceGenTile(i, params, p)) - } - - val tiles = rocket_tiles ++ boom_tiles - - tiles.foreach { t => - sbus.fromTile(None, buffer = BufferParams.default) { t.masterNode } - } -} - -trait HasTraceGenTilesModuleImp extends LazyModuleImp { - val outer: HasTraceGenTiles - val success = IO(Output(Bool())) - - outer.tiles.zipWithIndex.map { case(t, i) => - t.module.constants.hartid := i.U - } - - val status = DebugCombiner( - outer.rocket_tiles.map(_.module.status) ++ - outer.boom_tiles.map(_.module.status) - ) - success := status.finished -} - class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem - with HasTraceGenTiles + with HasTiles with CanHaveMasterAXI4MemPort { + + def coreMonitorBundles = Nil override lazy val module = new TraceGenSystemModuleImp(this) } class TraceGenSystemModuleImp(outer: TraceGenSystem) extends BaseSubsystemModuleImp(outer) - with HasTraceGenTilesModuleImp +{ + val success = IO(Output(Bool())) + + outer.tiles.zipWithIndex.map { case(t, i) => t.module.constants.hartid := i.U } + + val status = dontTouch(DebugCombiner(outer.tiles.collect { case t: GroundTestTile => t.module.status })) + success := outer.tileCeaseSinkNode.in.head._1.asUInt.andR + +} diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala index d395211f..329203e2 100644 --- a/generators/tracegen/src/main/scala/Tile.scala +++ b/generators/tracegen/src/main/scala/Tile.scala @@ -3,36 +3,17 @@ package tracegen import chisel3._ import chisel3.util._ import freechips.rocketchip.config.Parameters -import freechips.rocketchip.diplomacy.{LazyModule, SynchronousCrossing} -import freechips.rocketchip.groundtest.{TraceGenerator, TraceGenParams, DummyPTW, GroundTestStatus} -import freechips.rocketchip.rocket.{DCache, NonBlockingDCache, SimpleHellaCacheIF, HellaCacheExceptions, HellaCacheReq, HellaCacheIO} +import freechips.rocketchip.diplomacy.{LazyModule, SynchronousCrossing, ClockCrossingType} +import freechips.rocketchip.groundtest._ +import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.constants.{MemoryOpConstants} -import freechips.rocketchip.tile.{BaseTile, BaseTileModuleImp, HartsWontDeduplicate, TileKey} -import freechips.rocketchip.tilelink.{TLInwardNode, TLIdentityNode} +import freechips.rocketchip.tile._ +import freechips.rocketchip.tilelink.{TLInwardNode, TLIdentityNode, TLOutwardNode, TLTempNode} import freechips.rocketchip.interrupts._ - +import freechips.rocketchip.subsystem._ import boom.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO} import boom.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule} -class TraceGenTile(val id: Int, val params: TraceGenParams, q: Parameters) - extends BaseTile(params, SynchronousCrossing(), HartsWontDeduplicate(params), q) { - val dcache = params.dcache.map { dc => LazyModule( - if (dc.nMSHRs == 0) new DCache(hartId, crossing) - else new NonBlockingDCache(hartId)) - }.get - - val intInwardNode: IntInwardNode = IntIdentityNode() - val intOutwardNode: IntOutwardNode = IntIdentityNode() - val slaveNode: TLInwardNode = TLIdentityNode() - val ceaseNode: IntOutwardNode = IntIdentityNode() - val haltNode: IntOutwardNode = IntIdentityNode() - val wfiNode: IntOutwardNode = IntIdentityNode() - - val masterNode = visibilityNode - masterNode := dcache.node - - override lazy val module = new TraceGenTileModuleImp(this) -} class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) with MemoryOpConstants { @@ -179,32 +160,58 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) } -class BoomTraceGenTile(val id: Int, val params: TraceGenParams, q: Parameters) - extends BaseTile(params, SynchronousCrossing(), HartsWontDeduplicate(params), q) { +case class BoomTraceGenTileAttachParams( + tileParams: BoomTraceGenParams, + crossingParams: TileCrossingParamsLike +) extends CanAttachTile { + type TileType = BoomTraceGenTile + val lookup: LookupByHartIdImpl = HartsWontDeduplicate(tileParams) +} + + +case class BoomTraceGenParams( + wordBits: Int, + addrBits: Int, + addrBag: List[BigInt], + maxRequests: Int, + memStart: BigInt, + numGens: Int, + dcache: Option[DCacheParams] = Some(DCacheParams()), + hartId: Int = 0 +) extends InstantiableTileParams[BoomTraceGenTile] with GroundTestTileParams +{ + def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): BoomTraceGenTile = { + new BoomTraceGenTile(this, crossing, lookup) + } + val beuAddr = None + val blockerCtrlAddr = None + val name = None + val traceParams = TraceGenParams(wordBits, addrBits, addrBag, maxRequests, memStart, numGens, dcache, hartId) +} + +class BoomTraceGenTile private( + val params: BoomTraceGenParams, + crossing: ClockCrossingType, + lookup: LookupByHartIdImpl, + q: Parameters) extends GroundTestTile(params, crossing, lookup, q) +{ + def this(params: BoomTraceGenParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = + this(params, crossing.crossingType, lookup, p) + val boom_params = p.alterMap(Map(TileKey -> BoomTileParams( dcache=params.dcache, core=BoomCoreParams(nPMPs=0, numLdqEntries=32, numStqEntries=32, useVM=false)))) val dcache = LazyModule(new BoomNonBlockingDCache(hartId)(boom_params)) - val intInwardNode: IntInwardNode = IntIdentityNode() - val intOutwardNode: IntOutwardNode = IntIdentityNode() - val slaveNode: TLInwardNode = TLIdentityNode() - val ceaseNode: IntOutwardNode = IntIdentityNode() - val haltNode: IntOutwardNode = IntIdentityNode() - val wfiNode: IntOutwardNode = IntIdentityNode() - - val masterNode = visibilityNode - masterNode := dcache.node + val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcacheOpt.map(_.node).getOrElse(TLTempNode()) override lazy val module = new BoomTraceGenTileModuleImp(this) } class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile) - extends BaseTileModuleImp(outer){ + extends GroundTestTileModuleImp(outer){ - val status = IO(new GroundTestStatus) - - val tracegen = Module(new TraceGenerator(outer.params)) + val tracegen = Module(new TraceGenerator(outer.params.traceParams)) tracegen.io.hartid := constants.hartid val ptw = Module(new DummyPTW(1)) @@ -219,31 +226,14 @@ class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile) lsu.io.hellacache := DontCare lsu.io.hellacache.req.valid := false.B - status.finished := tracegen.io.finished - status.timeout.valid := tracegen.io.timeout - status.timeout.bits := 0.U - status.error.valid := false.B -} + outer.reportCease(Some(tracegen.io.finished)) + outer.reportHalt(Some(tracegen.io.timeout)) + outer.reportWFI(None) -class TraceGenTileModuleImp(outer: TraceGenTile) - extends BaseTileModuleImp(outer) { - val status = IO(new GroundTestStatus) - val halt_and_catch_fire = None - - val ptw = Module(new DummyPTW(1)) - ptw.io.requestors.head <> outer.dcache.module.io.ptw - - val tracegen = Module(new TraceGenerator(outer.params)) - tracegen.io.hartid := constants.hartid - - val dcacheIF = Module(new SimpleHellaCacheIF()) - dcacheIF.io.requestor <> tracegen.io.mem - outer.dcache.module.io.cpu <> dcacheIF.io.cache - - status.finished := tracegen.io.finished status.timeout.valid := tracegen.io.timeout status.timeout.bits := 0.U status.error.valid := false.B - assert(!tracegen.io.timeout, s"TraceGen tile ${outer.id}: request timed out") + assert(!tracegen.io.timeout, s"TraceGen tile ${outer.tileParams.hartId}: request timed out") + } diff --git a/tools/dsptools b/tools/dsptools index 211166e6..e32ab8a0 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit 211166e635861fb1937828aee38c166baf0840b5 +Subproject commit e32ab8a0c77d419b52376064534090ff2583929d From f87522bf0e47cf179e8920f44d239b96cf7b14aa Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 18 Jun 2020 17:36:51 -0700 Subject: [PATCH 4/9] Fix AXI4 IOBinder for multi-channel systems --- generators/chipyard/src/main/scala/IOBinders.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 7d1ae8fa..18da543e 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -185,9 +185,9 @@ object AddIOCells { } def axi4(io: Seq[AXI4Bundle], node: AXI4SlaveNode): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = { - io.zip(node.in).map{ case (mem_axi4, (_, edge)) => { - val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some("iocell_mem_axi4")) - port.suggestName("mem_axi4") + io.zip(node.in).zipWithIndex.map{ case ((mem_axi4, (_, edge)), i) => { + val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_mem_axi4_${i}")) + port.suggestName(s"mem_axi4_${i}") (port, edge, ios) }} } From a9d349cb851713d41064ce1a889fc7836bc4c62a Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Thu, 18 Jun 2020 01:31:15 -0700 Subject: [PATCH 5/9] Emit htif node in device tree --- .../chipyard/src/main/scala/Subsystem.scala | 25 +++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 99c31472..c22bbbee 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -10,7 +10,7 @@ import chisel3.internal.sourceinfo.{SourceInfo} import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt} import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree} @@ -24,7 +24,7 @@ import freechips.rocketchip.amba.axi4._ import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} -import testchipip.{DromajoHelper} +import testchipip.{DromajoHelper, CanHavePeripherySerial, SerialKey} trait HasChipyardTiles extends HasTiles with CanHavePeripheryPLIC @@ -87,8 +87,29 @@ trait HasChipyardTilesModuleImp extends HasTilesModuleImp val outer: HasChipyardTiles } +trait CanHaveHTIF { this: BaseSubsystem => + // Advertise HTIF if system can communicate with fesvr + if (this match { + case _: CanHavePeripherySerial if p(SerialKey) => true + case _: HasPeripheryDebug if p(ExportDebug).protocols.nonEmpty => true + case _ => false + }) { + ResourceBinding { + val htif = new Device { + def describe(resources: ResourceBindings): Description = { + val compat = resources("compat").map(_.value) + Description("htif", Map( + "compatible" -> compat)) + } + } + Resource(htif, "compat").bind(ResourceString("ucb,htif0")) + } + } +} + class Subsystem(implicit p: Parameters) extends BaseSubsystem with HasChipyardTiles + with CanHaveHTIF { override lazy val module = new SubsystemModuleImp(this) From 2bfc4f6dd443df68b40de5c694c31c9eb3e4e3dc Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 19 Jun 2020 14:44:07 -0700 Subject: [PATCH 6/9] More fixes for RC bump --- generators/boom | 2 +- .../src/main/scala/config/TracegenConfigs.scala | 10 +++++----- generators/testchipip | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/generators/boom b/generators/boom index 0b60c278..96ac46f6 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 0b60c27879f8aa309537d5a535ea2c42e3dabefe +Subproject commit 96ac46f60261a98f1f1fa62fbd6a2fe9df5ba4bb diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index ec834f9f..e8aeeb29 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -9,7 +9,7 @@ class TraceGenConfig extends Config( new chipyard.config.WithTracegenSystem ++ new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.groundtest.GroundTestBaseConfig) class NonBlockingTraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ @@ -17,7 +17,7 @@ class NonBlockingTraceGenConfig extends Config( new chipyard.config.WithTracegenSystem ++ new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.groundtest.GroundTestBaseConfig) class BoomTraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ @@ -26,7 +26,7 @@ class BoomTraceGenConfig extends Config( new tracegen.WithBoomTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.groundtest.GroundTestBaseConfig) class NonBlockingTraceGenL2Config extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ @@ -35,7 +35,7 @@ class NonBlockingTraceGenL2Config extends Config( new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.groundtest.GroundTestBaseConfig) class NonBlockingTraceGenL2RingConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ @@ -45,4 +45,4 @@ class NonBlockingTraceGenL2RingConfig extends Config( new testchipip.WithRingSystemBus ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.groundtest.GroundTestBaseConfig) diff --git a/generators/testchipip b/generators/testchipip index 26891fac..29eb87c9 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 26891fac1d40c31348b6e6f16d730de705707094 +Subproject commit 29eb87c938a2106249b85e3b3dffd00046f5077c From a1cc62b85aa4a53c5c69c1e9114ab0aafed8446f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 19 Jun 2020 19:18:33 -0700 Subject: [PATCH 7/9] Bump Rocket-chip again --- .../chipyard/src/main/scala/IOBinders.scala | 3 ++- generators/rocket-chip | 2 +- .../tracegen/src/main/scala/System.scala | 5 ++++- generators/tracegen/src/main/scala/Tile.scala | 22 ++++++++++++++----- 4 files changed, 24 insertions(+), 8 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 18da543e..1a366d19 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -16,6 +16,7 @@ import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTest import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ +import tracegen.{TraceGenSystemModuleImp} import barstools.iocell.chisel._ @@ -389,7 +390,7 @@ class WithSimSerial extends OverrideIOBinder({ }) class WithTraceGenSuccessBinder extends OverrideIOBinder({ - (system: GroundTestSubsystemModuleImp[GroundTestSubsystem]) => { + (system: TraceGenSystemModuleImp) => { val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success")) successPort.suggestName("success") val harnessFn = (th: chipyard.TestHarness) => { when (successPort) { th.success := true.B }; Nil } diff --git a/generators/rocket-chip b/generators/rocket-chip index 1cec6e69..653efa99 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 1cec6e697ce9ea8ffa13a6d95e0734946db3adb1 +Subproject commit 653efa99a27dc155bd4b4706a7e71c5c930f62b1 diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index d6b72d4a..ca3572d7 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -22,7 +22,10 @@ class TraceGenSystemModuleImp(outer: TraceGenSystem) outer.tiles.zipWithIndex.map { case(t, i) => t.module.constants.hartid := i.U } - val status = dontTouch(DebugCombiner(outer.tiles.collect { case t: GroundTestTile => t.module.status })) + val status = dontTouch(DebugCombiner(outer.tiles.collect { + case t: GroundTestTile => t.module.status + case t: BoomTraceGenTile => t.module.status + })) success := outer.tileCeaseSinkNode.in.head._1.asUInt.andR } diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala index 329203e2..1ddf0d84 100644 --- a/generators/tracegen/src/main/scala/Tile.scala +++ b/generators/tracegen/src/main/scala/Tile.scala @@ -3,7 +3,7 @@ package tracegen import chisel3._ import chisel3.util._ import freechips.rocketchip.config.Parameters -import freechips.rocketchip.diplomacy.{LazyModule, SynchronousCrossing, ClockCrossingType} +import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule, SynchronousCrossing, ClockCrossingType} import freechips.rocketchip.groundtest._ import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.constants.{MemoryOpConstants} @@ -178,11 +178,14 @@ case class BoomTraceGenParams( numGens: Int, dcache: Option[DCacheParams] = Some(DCacheParams()), hartId: Int = 0 -) extends InstantiableTileParams[BoomTraceGenTile] with GroundTestTileParams +) extends InstantiableTileParams[BoomTraceGenTile] { def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): BoomTraceGenTile = { new BoomTraceGenTile(this, crossing, lookup) } + val core = RocketCoreParams(nPMPs = 0) //TODO remove this + val btb = None + val icache = Some(ICacheParams()) val beuAddr = None val blockerCtrlAddr = None val name = None @@ -193,23 +196,32 @@ class BoomTraceGenTile private( val params: BoomTraceGenParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, - q: Parameters) extends GroundTestTile(params, crossing, lookup, q) + q: Parameters) extends BaseTile(params, crossing, lookup, q) + with SinksExternalInterrupts + with SourcesExternalNotifications { def this(params: BoomTraceGenParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = this(params, crossing.crossingType, lookup, p) + val cpuDevice: SimpleDevice = new SimpleDevice("groundtest", Nil) + val intOutwardNode: IntOutwardNode = IntIdentityNode() + val slaveNode: TLInwardNode = TLIdentityNode() + val boom_params = p.alterMap(Map(TileKey -> BoomTileParams( dcache=params.dcache, core=BoomCoreParams(nPMPs=0, numLdqEntries=32, numStqEntries=32, useVM=false)))) val dcache = LazyModule(new BoomNonBlockingDCache(hartId)(boom_params)) - val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcacheOpt.map(_.node).getOrElse(TLTempNode()) + val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcache.node override lazy val module = new BoomTraceGenTileModuleImp(this) } class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile) - extends GroundTestTileModuleImp(outer){ + extends BaseTileModuleImp(outer){ + + val status = IO(new GroundTestStatus) + val halt_and_catch_fire = None val tracegen = Module(new TraceGenerator(outer.params.traceParams)) tracegen.io.hartid := constants.hartid From 6b31afb1c3fffbc61a82e2ea8f95143e015a9f88 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 21 Jun 2020 11:56:45 -0700 Subject: [PATCH 8/9] Bump boom --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 96ac46f6..859c6055 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 96ac46f60261a98f1f1fa62fbd6a2fe9df5ba4bb +Subproject commit 859c60553b0cd2e84ee586ad6de25223baefb722 From 16c8f47202ec743acaa84516a0ff79da0f13492a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 23 Jun 2020 16:31:41 +0000 Subject: [PATCH 9/9] Bump Firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index c2d8e3a4..82ce80bc 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit c2d8e3a46e59222e115a1fdaa7267592e1d3c503 +Subproject commit 82ce80bc129905834426629279098fcd970a9ed3