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Merge pull request #1342 from ucb-bar/remove-gen-collateral

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Remove gen-collateral when rebuilding
This commit is contained in:
Abraham Gonzalez
2023-02-15 16:40:40 -08:00
committed by GitHub
parent 089dbc1fb6 55950b61b9
commit df903f0cb6
7 changed files with 30 additions and 28 deletions
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16
common.mk
View File

@@ -91,7 +91,7 @@ endif
######################################################################################### #########################################################################################
# copy over bootrom files # copy over bootrom files
######################################################################################### #########################################################################################
$(build_dir) $(OUT_DIR): $(build_dir):
mkdir -p $@ mkdir -p $@
$(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip/bootrom/bootrom.%.img | $(build_dir) $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip/bootrom/bootrom.%.img | $(build_dir)
@@ -101,7 +101,7 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
# create firrtl file rule and variables # create firrtl file rule and variables
######################################################################################### #########################################################################################
# AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile # AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile
$(FIRRTL_FILE) $(ANNO_FILE) &: $(SCALA_SOURCES) $(sim_files) $(SCALA_BUILDTOOL_DEPS) $(EXTRA_GENERATOR_REQS) $(FIRRTL_FILE) $(ANNO_FILE) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(EXTRA_GENERATOR_REQS)
mkdir -p $(build_dir) mkdir -p $(build_dir)
$(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\ $(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\
--target-dir $(build_dir) \ --target-dir $(build_dir) \
@@ -144,7 +144,8 @@ SFC_MFC_TARGETS = \
$(MFC_MODEL_HRCHY_JSON) \ $(MFC_MODEL_HRCHY_JSON) \
$(MFC_MODEL_SMEMS_JSON) \ $(MFC_MODEL_SMEMS_JSON) \
$(MFC_FILELIST) \ $(MFC_FILELIST) \
$(MFC_BB_MODS_FILELIST) $(MFC_BB_MODS_FILELIST) \
$(GEN_COLLATERAL_DIR)
SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF) SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
@@ -161,6 +162,7 @@ SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
# hack: when using dontTouch, io.cpu annotations are not removed by SFC, # hack: when using dontTouch, io.cpu annotations are not removed by SFC,
# hence we remove them manually by using jq before passing them to firtool # hence we remove them manually by using jq before passing them to firtool
$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES)
rm -rf $(GEN_COLLATERAL_DIR)
ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS)) ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS))
$(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none)) $(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none))
$(eval EXTRA_FIRRTL_OPTIONS += $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), $(SFC_REPL_SEQ_MEM),)) $(eval EXTRA_FIRRTL_OPTIONS += $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), $(SFC_REPL_SEQ_MEM),))
@@ -172,7 +174,7 @@ endif
--no-dedup \ --no-dedup \
--output-file $(SFC_FIRRTL_BASENAME) \ --output-file $(SFC_FIRRTL_BASENAME) \
--output-annotation-file $(SFC_ANNO_FILE) \ --output-annotation-file $(SFC_ANNO_FILE) \
--target-dir $(OUT_DIR) \ --target-dir $(GEN_COLLATERAL_DIR) \
--input-file $(FIRRTL_FILE) \ --input-file $(FIRRTL_FILE) \
--annotation-file $(FINAL_ANNO_FILE) \ --annotation-file $(FINAL_ANNO_FILE) \
--log-level $(FIRRTL_LOGLEVEL) \ --log-level $(FIRRTL_LOGLEVEL) \
@@ -200,7 +202,7 @@ endif
--repl-seq-mem-circuit=$(MODEL) \ --repl-seq-mem-circuit=$(MODEL) \
--annotation-file=$(SFC_ANNO_FILE) \ --annotation-file=$(SFC_ANNO_FILE) \
--split-verilog \ --split-verilog \
-o $(OUT_DIR) \ -o $(GEN_COLLATERAL_DIR) \
$(SFC_FIRRTL_FILE) $(SFC_FIRRTL_FILE)
-mv $(SFC_SMEMS_CONF) $(MFC_SMEMS_CONF) -mv $(SFC_SMEMS_CONF) $(MFC_SMEMS_CONF)
$(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler $(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler
@@ -213,8 +215,8 @@ $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILEL
--out-dut-filelist $(TOP_MODS_FILELIST) \ --out-dut-filelist $(TOP_MODS_FILELIST) \
--out-model-filelist $(MODEL_MODS_FILELIST) \ --out-model-filelist $(MODEL_MODS_FILELIST) \
--in-all-filelist $(MFC_FILELIST) \ --in-all-filelist $(MFC_FILELIST) \
--target-dir $(OUT_DIR) --target-dir $(GEN_COLLATERAL_DIR)
$(SED) -e 's;^;$(OUT_DIR)/;' $(MFC_BB_MODS_FILELIST) > $(BB_MODS_FILELIST) $(SED) -e 's;^;$(GEN_COLLATERAL_DIR)/;' $(MFC_BB_MODS_FILELIST) > $(BB_MODS_FILELIST)
$(SED) -i 's/\.\///' $(TOP_MODS_FILELIST) $(SED) -i 's/\.\///' $(TOP_MODS_FILELIST)
$(SED) -i 's/\.\///' $(MODEL_MODS_FILELIST) $(SED) -i 's/\.\///' $(MODEL_MODS_FILELIST)
$(SED) -i 's/\.\///' $(BB_MODS_FILELIST) $(SED) -i 's/\.\///' $(BB_MODS_FILELIST)

6
fpga/Makefile
View File

@@ -94,13 +94,13 @@ SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v
# copy files but ignore *.h files in *.f (match vcs) # copy files but ignore *.h files in *.f (match vcs)
$(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR) $(sim_files): $(SIM_FILE_REQS) | $(GEN_COLLATERAL_DIR)
cp -f $^ $(OUT_DIR) cp -f $^ $(GEN_COLLATERAL_DIR)
$(foreach file,\ $(foreach file,\
$^,\ $^,\
$(if $(filter %.h,$(file)),\ $(if $(filter %.h,$(file)),\
,\ ,\
echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;)) echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;))
######################################################################################### #########################################################################################
# import other necessary rules and variables # import other necessary rules and variables

2
sims/common-sim-flags.mk
View File

@@ -20,7 +20,7 @@ SIM_CXXFLAGS = \
-std=c++17 \ -std=c++17 \
-I$(RISCV)/include \ -I$(RISCV)/include \
-I$(dramsim_dir) \ -I$(dramsim_dir) \
-I$(OUT_DIR) \ -I$(GEN_COLLATERAL_DIR) \
$(EXTRA_SIM_CXXFLAGS) $(EXTRA_SIM_CXXFLAGS)
SIM_LDFLAGS = \ SIM_LDFLAGS = \

6
sims/vcs/Makefile
View File

@@ -38,13 +38,13 @@ SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir) # copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir)
$(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR) $(sim_files): $(SIM_FILE_REQS) | $(GEN_COLLATERAL_DIR)
cp -f $^ $(OUT_DIR) cp -f $^ $(GEN_COLLATERAL_DIR)
$(foreach file,\ $(foreach file,\
$^,\ $^,\
$(if $(filter %.h,$(file)),\ $(if $(filter %.h,$(file)),\
,\ ,\
echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;)) echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;))
######################################################################################### #########################################################################################
# import other necessary rules and variables # import other necessary rules and variables

12
sims/verilator/Makefile
View File

@@ -66,13 +66,13 @@ SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc
# copy files and add -FI for *.h files in *.f # copy files and add -FI for *.h files in *.f
$(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR) $(sim_files): $(SIM_FILE_REQS) | $(GEN_COLLATERAL_DIR)
cp -f $^ $(OUT_DIR) cp -f $^ $(GEN_COLLATERAL_DIR)
$(foreach file,\ $(foreach file,\
$^,\ $^,\
$(if $(filter %.h,$(file)),\ $(if $(filter %.h,$(file)),\
echo "-FI $(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;,\ echo "-FI $(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;,\
echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;)) echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;))
######################################################################################### #########################################################################################
# import other necessary rules and variables # import other necessary rules and variables
@@ -143,7 +143,7 @@ CHIPYARD_VERILATOR_FLAGS := \
# options dependent on whether external IP (cva6/NVDLA) or just chipyard is used # options dependent on whether external IP (cva6/NVDLA) or just chipyard is used
# NOTE: defer the evaluation of this until it is used! # NOTE: defer the evaluation of this until it is used!
PLATFORM_OPTS = $(shell \ PLATFORM_OPTS = $(shell \
if grep -qiP "module\s+(CVA6|NVDLA)" $(OUT_DIR)/*.*v; \ if grep -qiP "module\s+(CVA6|NVDLA)" $(GEN_COLLATERAL_DIR)/*.*v; \
then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \ then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \
else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi) else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi)
@@ -181,7 +181,7 @@ VERILATOR_CXXFLAGS = \
-DTEST_HARNESS=V$(VLOG_MODEL) \ -DTEST_HARNESS=V$(VLOG_MODEL) \
-DVERILATOR \ -DVERILATOR \
-include $(build_dir)/$(long_name).plusArgs \ -include $(build_dir)/$(long_name).plusArgs \
-include $(OUT_DIR)/verilator.h -include $(GEN_COLLATERAL_DIR)/verilator.h
VERILATOR_LDFLAGS = $(SIM_LDFLAGS) VERILATOR_LDFLAGS = $(SIM_LDFLAGS)

14
variables.mk
View File

@@ -161,18 +161,18 @@ MFC_TOP_HRCHY_JSON ?= $(build_dir)/top_module_hierarchy.json
MFC_MODEL_HRCHY_JSON ?= $(build_dir)/model_module_hierarchy.json MFC_MODEL_HRCHY_JSON ?= $(build_dir)/model_module_hierarchy.json
MFC_SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf MFC_SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf
# hardcoded firtool outputs # hardcoded firtool outputs
MFC_FILELIST = $(OUT_DIR)/filelist.f MFC_FILELIST = $(GEN_COLLATERAL_DIR)/filelist.f
MFC_BB_MODS_FILELIST = $(OUT_DIR)/firrtl_black_box_resource_files.f MFC_BB_MODS_FILELIST = $(GEN_COLLATERAL_DIR)/firrtl_black_box_resource_files.f
MFC_TOP_SMEMS_JSON = $(OUT_DIR)/metadata/seq_mems.json MFC_TOP_SMEMS_JSON = $(GEN_COLLATERAL_DIR)/metadata/seq_mems.json
MFC_MODEL_SMEMS_JSON = $(OUT_DIR)/metadata/tb_seq_mems.json MFC_MODEL_SMEMS_JSON = $(GEN_COLLATERAL_DIR)/metadata/tb_seq_mems.json
# macrocompiler smems in/output # macrocompiler smems in/output
SFC_SMEMS_CONF ?= $(build_dir)/$(long_name).sfc.mems.conf SFC_SMEMS_CONF ?= $(build_dir)/$(long_name).sfc.mems.conf
TOP_SMEMS_CONF ?= $(build_dir)/$(long_name).top.mems.conf TOP_SMEMS_CONF ?= $(build_dir)/$(long_name).top.mems.conf
TOP_SMEMS_FILE ?= $(OUT_DIR)/$(long_name).top.mems.v TOP_SMEMS_FILE ?= $(GEN_COLLATERAL_DIR)/$(long_name).top.mems.v
TOP_SMEMS_FIR ?= $(build_dir)/$(long_name).top.mems.fir TOP_SMEMS_FIR ?= $(build_dir)/$(long_name).top.mems.fir
MODEL_SMEMS_CONF ?= $(build_dir)/$(long_name).model.mems.conf MODEL_SMEMS_CONF ?= $(build_dir)/$(long_name).model.mems.conf
MODEL_SMEMS_FILE ?= $(OUT_DIR)/$(long_name).model.mems.v MODEL_SMEMS_FILE ?= $(GEN_COLLATERAL_DIR)/$(long_name).model.mems.v
MODEL_SMEMS_FIR ?= $(build_dir)/$(long_name).model.mems.fir MODEL_SMEMS_FIR ?= $(build_dir)/$(long_name).model.mems.fir
# top module files to include # top module files to include
@@ -258,7 +258,7 @@ gen_dir=$(sim_dir)/generated-src
# per-project output directory # per-project output directory
build_dir=$(gen_dir)/$(long_name) build_dir=$(gen_dir)/$(long_name)
# final generated collateral per-project # final generated collateral per-project
OUT_DIR ?= $(build_dir)/gen-collateral GEN_COLLATERAL_DIR ?= $(build_dir)/gen-collateral
######################################################################################### #########################################################################################
# assembly/benchmark variables # assembly/benchmark variables

2
vcs.mk
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@@ -51,7 +51,7 @@ VCS_NONCC_OPTS = \
-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \ -sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \ +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
-debug_pp \ -debug_pp \
+incdir+$(OUT_DIR) +incdir+$(GEN_COLLATERAL_DIR)
PREPROC_DEFINES = \ PREPROC_DEFINES = \
+define+VCS \ +define+VCS \