Trim redundant MDF field

macros/src/main/scala/Utils.scala

@@ -68,7 +68,7 @@ class Macro(srcMacro: SRAMMacro) {
 object Utils {
   def filterForSRAM(s: Option[Seq[mdf.macrolib.Macro]]): Option[Seq[mdf.macrolib.SRAMMacro]] = {
     s match {
-      case Some(l:Seq[mdf.macrolib.Macro]) => Some(l filter { _.macroType == mdf.macrolib.SRAM } map { m => m.asInstanceOf[mdf.macrolib.SRAMMacro] })
+      case Some(l:Seq[mdf.macrolib.Macro]) => Some(l filter { _.isInstanceOf[mdf.macrolib.SRAMMacro] } map { m => m.asInstanceOf[mdf.macrolib.SRAMMacro] })
       case _ => None
     }
   }

macros/src/test/scala/CostFunction.scala

@@ -30,7 +30,6 @@ class SelectCostMetric extends MacroCompilerSpec with HasSRAMGenerator {
 
   val libSRAMs = Seq(
     SRAMMacro(
-      macroType=SRAM,
       name="SRAM_WIDTH_128",
       depth=1024,
       width=128,
@@ -40,7 +39,6 @@ class SelectCostMetric extends MacroCompilerSpec with HasSRAMGenerator {
       )
     ),
     SRAMMacro(
-      macroType=SRAM,
       name="SRAM_WIDTH_64",
       depth=1024,
       width=64,
@@ -50,7 +48,6 @@ class SelectCostMetric extends MacroCompilerSpec with HasSRAMGenerator {
       )
     ),
     SRAMMacro(
-      macroType=SRAM,
       name="SRAM_WIDTH_32",
       depth=1024,
       width=32,

macros/src/test/scala/MacroCompilerSpec.scala

@@ -174,7 +174,6 @@ trait HasSRAMGenerator {
   // Generate a "simple" SRAM (active high/positive edge, 1 read-write port).
   def generateSRAM(name: String, prefix: String, width: Int, depth: Int, maskGran: Option[Int] = None, extraPorts: Seq[MacroExtraPort] = List()): SRAMMacro = {
     SRAMMacro(
-      macroType=SRAM,
       name=name,
       width=width,
       depth=depth,

macros/src/test/scala/SimpleSplitDepth.scala

@@ -337,7 +337,6 @@ class SplitDepth_SplitPortsNonMasked extends MacroCompilerSpec with HasSRAMGener
     val v = "split_depth-r-w-split-lib-split-mem.v"
 
     val libMacro = SRAMMacro(
-      macroType=SRAM,
       name="awesome_lib_mem",
       width=width,
       depth=libDepth,
@@ -349,7 +348,6 @@ class SplitDepth_SplitPortsNonMasked extends MacroCompilerSpec with HasSRAMGener
     )
 
     val memMacro = SRAMMacro(
-      macroType=SRAM,
       name="target_memory",
       width=width,
       depth=memDepth,
@@ -426,7 +424,6 @@ circuit target_memory :
     val v = "split_depth-r-w-regular-lib-split-mem.v"
 
     val memMacro = SRAMMacro(
-      macroType=SRAM,
       name="target_memory",
       width=width,
       depth=memDepth,
@@ -460,7 +457,6 @@ TODO
     val v = "split_depth-r-w-split-lib-regular-mem.v"
 
     val libMacro = SRAMMacro(
-      macroType=SRAM,
       name="awesome_lib_mem",
       width=width,
       depth=libDepth,
@@ -502,7 +498,6 @@ class SplitDepth_SplitPortsMasked extends MacroCompilerSpec with HasSRAMGenerato
     val v = "split_depth-r-mw-split-lib-split-mem.v"
 
     val libMacro = SRAMMacro(
-      macroType=SRAM,
       name="awesome_lib_mem",
       width=width,
       depth=libDepth,
@@ -514,7 +509,6 @@ class SplitDepth_SplitPortsMasked extends MacroCompilerSpec with HasSRAMGenerato
     )
 
     val memMacro = SRAMMacro(
-      macroType=SRAM,
       name="target_memory",
       width=width,
       depth=memDepth,
@@ -595,7 +589,6 @@ circuit target_memory :
     val v = "split_depth-r-mw-regular-lib-split-mem.v"
 
     val memMacro = SRAMMacro(
-      macroType=SRAM,
       name="target_memory",
       width=width,
       depth=memDepth,
@@ -629,7 +622,6 @@ TODO
     val v = "split_depth-r-mw-split-lib-regular-mem.v"
 
     val libMacro = SRAMMacro(
-      macroType=SRAM,
       name="awesome_lib_mem",
       width=width,
       depth=libDepth,

macros/src/test/scala/SimpleSplitWidth.scala

@@ -407,7 +407,6 @@ class SplitWidth1024x32_readEnable_Lib extends MacroCompilerSpec with HasSRAMGen
 
   override def generateLibSRAM() = {
     SRAMMacro(
-      macroType=SRAM,
       name=lib_name,
       width=libWidth,
       depth=libDepth,
@@ -466,7 +465,6 @@ class SplitWidth1024x32_readEnable_Mem extends MacroCompilerSpec with HasSRAMGen
 
   override def generateMemSRAM() = {
     SRAMMacro(
-      macroType=SRAM,
       name=mem_name,
       width=memWidth,
       depth=memDepth,
@@ -493,7 +491,6 @@ class SplitWidth1024x32_readEnable_LibMem extends MacroCompilerSpec with HasSRAM
 
   override def generateLibSRAM() = {
     SRAMMacro(
-      macroType=SRAM,
       name=lib_name,
       width=libWidth,
       depth=libDepth,
@@ -508,7 +505,6 @@ class SplitWidth1024x32_readEnable_LibMem extends MacroCompilerSpec with HasSRAM
 
   override def generateMemSRAM() = {
     SRAMMacro(
-      macroType=SRAM,
       name=mem_name,
       width=memWidth,
       depth=memDepth,

macros/src/test/scala/SpecificExamples.scala

@@ -11,7 +11,6 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
 
   val libSRAMs = Seq(
     SRAMMacro(
-      macroType=SRAM,
       name="SRAM1RW1024x8",
       depth=1024,
       width=8,
@@ -21,7 +20,6 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
       )
     ),
     SRAMMacro(
-      macroType=SRAM,
       name="SRAM1RW512x32",
       depth=512,
       width=32,
@@ -31,7 +29,6 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
       )
     ),
     SRAMMacro(
-      macroType=SRAM,
       name="SRAM1RW64x128",
       depth=64,
       width=128,
@@ -41,7 +38,6 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
       )
     ),
     SRAMMacro(
-      macroType=SRAM,
       name="SRAM1RW64x32",
       depth=64,
       width=32,
@@ -51,7 +47,6 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
       )
     ),
     SRAMMacro(
-      macroType=SRAM,
       name="SRAM1RW64x8",
       depth=64,
       width=8,
@@ -61,7 +56,6 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
       )
     ),
     SRAMMacro(
-      macroType=SRAM,
       name="SRAM1RW512x8",
       depth=512,
       width=8,
@@ -71,7 +65,6 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
       )
     ),
     SRAMMacro(
-      macroType=SRAM,
       name="SRAM2RW64x32",
       depth=64,
       width=32,

macros/src/test/scala/SynFlops.scala

@@ -87,7 +87,6 @@ class Synflops_SplitPorts_Read_Write extends MacroCompilerSpec with HasSRAMGener
   override lazy val width = 8
 
   override def generateLibSRAM = SRAMMacro(
-    macroType=SRAM,
     name=lib_name,
     width=width,
     depth=libDepth,
@@ -99,7 +98,6 @@ class Synflops_SplitPorts_Read_Write extends MacroCompilerSpec with HasSRAMGener
   )
 
   override def generateMemSRAM = SRAMMacro(
-    macroType=SRAM,
     name=mem_name,
     width=width,
     depth=memDepth,
@@ -198,7 +196,6 @@ class Synflops_SplitPorts_MaskedMem_Read_MaskedWrite extends MacroCompilerSpec w
   override lazy val libMaskGran = Some(1)
 
   override def generateLibSRAM = SRAMMacro(
-    macroType=SRAM,
     name=lib_name,
     width=width,
     depth=libDepth,
@@ -210,7 +207,6 @@ class Synflops_SplitPorts_MaskedMem_Read_MaskedWrite extends MacroCompilerSpec w
   )
 
   override def generateMemSRAM = SRAMMacro(
-    macroType=SRAM,
     name=mem_name,
     width=width,
     depth=memDepth,