Trim redundant MDF field

2017-08-01 19:50:17 -07:00
parent 4013b1924f
commit df8b5815c6
8 changed files with 2 additions and 29 deletions
--- a/macros/src/test/scala/SpecificExamples.scala
+++ b/macros/src/test/scala/SpecificExamples.scala
@@ -11,7 +11,6 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {

  val libSRAMs = Seq(
    SRAMMacro(
-      macroType=SRAM,
      name="SRAM1RW1024x8",
      depth=1024,
      width=8,
@@ -21,7 +20,6 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
      )
    ),
    SRAMMacro(
-      macroType=SRAM,
      name="SRAM1RW512x32",
      depth=512,
      width=32,
@@ -31,7 +29,6 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
      )
    ),
    SRAMMacro(
-      macroType=SRAM,
      name="SRAM1RW64x128",
      depth=64,
      width=128,
@@ -41,7 +38,6 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
      )
    ),
    SRAMMacro(
-      macroType=SRAM,
      name="SRAM1RW64x32",
      depth=64,
      width=32,
@@ -51,7 +47,6 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
      )
    ),
    SRAMMacro(
-      macroType=SRAM,
      name="SRAM1RW64x8",
      depth=64,
      width=8,
@@ -61,7 +56,6 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
      )
    ),
    SRAMMacro(
-      macroType=SRAM,
      name="SRAM1RW512x8",
      depth=512,
      width=8,
@@ -71,7 +65,6 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
      )
    ),
    SRAMMacro(
-      macroType=SRAM,
      name="SRAM2RW64x32",
      depth=64,
      width=32,