diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh
index a4a95611..8043c12f 100755
--- a/.github/scripts/check-commit.sh
+++ b/.github/scripts/check-commit.sh
@@ -45,7 +45,7 @@ search () {
     done
 }
 
-submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils")
+submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy")
 dir="generators"
 branches=("master" "main" "dev")
 search
diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh
index 43151415..4eb7546f 100755
--- a/.github/scripts/defaults.sh
+++ b/.github/scripts/defaults.sh
@@ -28,12 +28,12 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
 
 # key value store to get the build groups
 declare -A grouping
-grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
-grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric"
+grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
+grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet"
 grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
 grouping["group-constellation"]="chipyard-constellation"
 grouping["group-gpu"]="chipyard-radiance chipyard-radiance-fuzzer chipyard-coalescer coalescer"
-grouping["group-tracegen"]="tracegen tracegen-boom"
+grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4"
 grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters"
 grouping["group-fpga"]="arty35t arty100t nexysvideo vc707 vcu118"
 
@@ -48,8 +48,10 @@ mapping["chipyard-digitaltop"]=" TOP=DigitalTop"
 mapping["chipyard-manymmioaccels"]=" CONFIG=ManyMMIOAcceleratorRocketConfig"
 mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig verilog"
 mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig"
-mapping["chipyard-boom"]=" CONFIG=MediumBoomCosimConfig"
-mapping["chipyard-dmiboom"]=" CONFIG=dmiMediumBoomCosimConfig"
+mapping["chipyard-boomv3"]=" CONFIG=MediumBoomV3CosimConfig"
+mapping["chipyard-dmiboomv3"]=" CONFIG=dmiMediumBoomV3CosimConfig"
+mapping["chipyard-boomv4"]=" CONFIG=MediumBoomV4CosimConfig"
+mapping["chipyard-dmiboomv4"]=" CONFIG=dmiMediumBoomV4CosimConfig"
 mapping["chipyard-spike"]=" CONFIG=SpikeConfig EXTRA_SIM_FLAGS='+spike-ipc=10'"
 mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
 mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
@@ -60,10 +62,12 @@ mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_S
 mapping["chipyard-chiplike"]=" CONFIG=ChipLikeRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog"
 mapping["chipyard-tethered"]=" CONFIG=VerilatorCITetheredChipLikeRocketConfig"
 mapping["chipyard-symmetric"]=" CONFIG=MultiSimSymmetricChipletRocketConfig"
-mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog"
+mapping["chipyard-llcchiplet"]=" CONFIG=MultiSimLLCChipletRocketConfig"
+mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomV3Config verilog"
 mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"
 mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"
-mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig"
+mapping["tracegen-boomv3"]=" CONFIG=BoomV3TraceGenConfig"
+mapping["tracegen-boomv4"]=" CONFIG=BoomV4TraceGenConfig"
 mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig"
 mapping["chipyard-shuttle"]=" CONFIG=ShuttleConfig"
 mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig"
diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh
index 22a699a5..2a4ad42f 100755
--- a/.github/scripts/run-tests.sh
+++ b/.github/scripts/run-tests.sh
@@ -46,13 +46,21 @@ case $1 in
         $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
         run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch
         ;;
-    chipyard-boom)
+    chipyard-boomv3)
+        run_bmark
+        ;;
+    chipyard-boomv4)
         run_bmark
         ;;
     chipyard-shuttle)
         run_bmark ${mapping[$1]}
         ;;
-    chipyard-dmiboom)
+    chipyard-dmiboomv3)
+        # Test checkpoint-restore
+        $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
+        run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch
+        ;;
+    chipyard-dmiboomv4)
         # Test checkpoint-restore
         $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
         run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch
@@ -122,10 +130,17 @@ case $1 in
         make -C $LOCAL_CHIPYARD_DIR/tests
         run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/symmetric.riscv LOADMEM=1
         ;;
+    chipyard-llcchiplet)
+        make -C $LOCAL_CHIPYARD_DIR/tests
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv LOADMEM=1
+        ;;
     tracegen)
         run_tracegen
         ;;
-    tracegen-boom)
+    tracegen-boomv3)
+        run_tracegen
+        ;;
+    tracegen-boomv4)
         run_tracegen
         ;;
     chipyard-cva6)
diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml
index f56f279d..dd91f4de 100644
--- a/.github/workflows/chipyard-run-tests.yml
+++ b/.github/workflows/chipyard-run-tests.yml
@@ -455,8 +455,8 @@ jobs:
           group-key: "group-cores"
           project-key: "chipyard-hetero"
 
-  chipyard-boom-run-tests:
-    name: chipyard-boom-run-tests
+  chipyard-boomv3-run-tests:
+    name: chipyard-boomv3-run-tests
     needs: prepare-chipyard-cores
     runs-on: as4
     steps:
@@ -476,7 +476,30 @@ jobs:
         uses: ./.github/actions/run-tests
         with:
           group-key: "group-cores"
-          project-key: "chipyard-boom"
+          project-key: "chipyard-boomv3"
+
+  chipyard-boomv4-run-tests:
+    name: chipyard-boomv4-run-tests
+    needs: prepare-chipyard-cores
+    runs-on: as4
+    steps:
+      - name: Delete old checkout
+        run: |
+            ls -alh .
+            rm -rf ${{ github.workspace }}/* || true
+            rm -rf ${{ github.workspace }}/.* || true
+            ls -alh .
+      - name: Checkout
+        uses: actions/checkout@v4
+      - name: Git workaround
+        uses: ./.github/actions/git-workaround
+      - name: Create conda env
+        uses: ./.github/actions/create-conda-env
+      - name: Run tests
+        uses: ./.github/actions/run-tests
+        with:
+          group-key: "group-cores"
+          project-key: "chipyard-boomv4"
 
   chipyard-shuttle-run-tests:
     name: chipyard-shuttle-run-tests
@@ -616,8 +639,8 @@ jobs:
           group-key: "group-peripherals"
           project-key: "chipyard-dmirocket"
 
-  chipyard-dmiboom-run-tests:
-    name: chipyard-dmiboom-run-tests
+  chipyard-dmiboomv3-run-tests:
+    name: chipyard-dmiboomv3-run-tests
     needs: prepare-chipyard-peripherals
     runs-on: as4
     steps:
@@ -637,7 +660,30 @@ jobs:
         uses: ./.github/actions/run-tests
         with:
           group-key: "group-peripherals"
-          project-key: "chipyard-dmiboom"
+          project-key: "chipyard-dmiboomv3"
+
+  chipyard-dmiboomv4-run-tests:
+    name: chipyard-dmiboomv4-run-tests
+    needs: prepare-chipyard-peripherals
+    runs-on: as4
+    steps:
+      - name: Delete old checkout
+        run: |
+            ls -alh .
+            rm -rf ${{ github.workspace }}/* || true
+            rm -rf ${{ github.workspace }}/.* || true
+            ls -alh .
+      - name: Checkout
+        uses: actions/checkout@v4
+      - name: Git workaround
+        uses: ./.github/actions/git-workaround
+      - name: Create conda env
+        uses: ./.github/actions/create-conda-env
+      - name: Run tests
+        uses: ./.github/actions/run-tests
+        with:
+          group-key: "group-peripherals"
+          project-key: "chipyard-dmiboomv4"
 
   chipyard-spiflashwrite-run-tests:
     name: chipyard-spiflashwrite-run-tests
@@ -731,6 +777,29 @@ jobs:
           group-key: "group-peripherals"
           project-key: "chipyard-symmetric"
 
+  chipyard-llcchiplet-run-tests:
+    name: chipyard-llcchiplet-run-tests
+    needs: prepare-chipyard-peripherals
+    runs-on: as4
+    steps:
+      - name: Delete old checkout
+        run: |
+            ls -alh .
+            rm -rf ${{ github.workspace }}/* || true
+            rm -rf ${{ github.workspace }}/.* || true
+            ls -alh .
+      - name: Checkout
+        uses: actions/checkout@v3
+      - name: Git workaround
+        uses: ./.github/actions/git-workaround
+      - name: Create conda env
+        uses: ./.github/actions/create-conda-env
+      - name: Run tests
+        uses: ./.github/actions/run-tests
+        with:
+          group-key: "group-peripherals"
+          project-key: "chipyard-llcchiplet"
+
   chipyard-sha3-run-tests:
     name: chipyard-sha3-run-tests
     needs: prepare-chipyard-accels
@@ -847,8 +916,8 @@ jobs:
           project-key: "chipyard-mempress"
 
 
-  tracegen-boom-run-tests:
-    name: tracegen-boom-run-tests
+  tracegen-boomv3-run-tests:
+    name: tracegen-boomv3-run-tests
     needs: prepare-chipyard-tracegen
     runs-on: as4
     steps:
@@ -868,7 +937,30 @@ jobs:
         uses: ./.github/actions/run-tests
         with:
           group-key: "group-tracegen"
-          project-key: "tracegen-boom"
+          project-key: "tracegen-boomv3"
+
+  tracegen-boomv4-run-tests:
+    name: tracegen-boomv4-run-tests
+    needs: prepare-chipyard-tracegen
+    runs-on: as4
+    steps:
+      - name: Delete old checkout
+        run: |
+            ls -alh .
+            rm -rf ${{ github.workspace }}/* || true
+            rm -rf ${{ github.workspace }}/.* || true
+            ls -alh .
+      - name: Checkout
+        uses: actions/checkout@v4
+      - name: Git workaround
+        uses: ./.github/actions/git-workaround
+      - name: Create conda env
+        uses: ./.github/actions/create-conda-env
+      - name: Run tests
+        uses: ./.github/actions/run-tests
+        with:
+          group-key: "group-tracegen"
+          project-key: "tracegen-boomv4"
 
   tracegen-run-tests:
     name: tracegen-run-tests
@@ -1084,24 +1176,28 @@ jobs:
             documentation-check,
             chipyard-rocket-run-tests,
             chipyard-hetero-run-tests,
-            chipyard-boom-run-tests,
+            chipyard-boomv3-run-tests,
+            chipyard-boomv4-run-tests,
             chipyard-shuttle-run-tests,
             chipyard-cva6-run-tests,
             chipyard-ibex-run-tests,
             chipyard-sodor-run-tests,
-            chipyard-dmiboom-run-tests,
+            chipyard-dmiboomv3-run-tests,
+            chipyard-dmiboomv4-run-tests,
             chipyard-dmirocket-run-tests,
             chipyard-spiflashwrite-run-tests,
             chipyard-manyperipherals-run-tests,
             chipyard-tethered-run-tests,
             chipyard-symmetric-run-tests,
+            chipyard-llcchiplet-run-tests,
             chipyard-sha3-run-tests,
             chipyard-gemmini-run-tests,
             chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests,
             chipyard-prefetchers-run-tests,
             chipyard-mempress-run-tests,
             chipyard-constellation-run-tests,
-            tracegen-boom-run-tests,
+            tracegen-boomv3-run-tests,
+            tracegen-boomv4-run-tests,
             tracegen-run-tests,
             icenet-run-tests,
             testchipip-run-tests,
diff --git a/.github/workflows/update-circt.yml b/.github/workflows/update-circt.yml
index 2d52a155..f0c3158b 100644
--- a/.github/workflows/update-circt.yml
+++ b/.github/workflows/update-circt.yml
@@ -16,7 +16,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - name: Update CIRCT
-        uses: circt/update-circt@v1.0.0
+        uses: circt/update-circt@v1
         with:
           user: 'bartender'
           email: 'firesimchipyard@gmail.com'
diff --git a/.gitmodules b/.gitmodules
index 2442d989..c708169b 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -49,6 +49,9 @@
 [submodule "generators/cva6"]
 	path = generators/cva6
 	url = https://github.com/ucb-bar/cva6-wrapper.git
+[submodule "generators/diplomacy"]
+	path = generators/diplomacy
+	url = https://github.com/chipsalliance/diplomacy.git
 [submodule "tools/DRAMSim2"]
 	path = tools/DRAMSim2
 	url = https://github.com/firesim/DRAMSim2.git
diff --git a/build.sbt b/build.sbt
index 642c4af9..ea1637cd 100644
--- a/build.sbt
+++ b/build.sbt
@@ -113,8 +113,19 @@ lazy val rocketMacros  = (project in rocketChipDir / "macros")
     )
   )
 
+lazy val diplomacy = freshProject("diplomacy", file("generators/diplomacy/diplomacy"))
+  .dependsOn(cde)
+  .settings(commonSettings)
+  .settings(chiselSettings)
+  .settings(Compile / scalaSource := baseDirectory.value / "diplomacy")
+  .settings(
+    libraryDependencies ++= Seq(
+      "com.lihaoyi" %% "sourcecode" % "0.3.1"
+    )
+  )
+
 lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
-  .dependsOn(hardfloat, rocketMacros, cde)
+  .dependsOn(hardfloat, rocketMacros, diplomacy, cde)
   .settings(commonSettings)
   .settings(chiselSettings)
   .settings(
@@ -123,7 +134,8 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
       "org.scala-lang" % "scala-reflect" % scalaVersion.value,
       "org.json4s" %% "json4s-jackson" % "4.0.5",
       "org.scalatest" %% "scalatest" % "3.2.0" % "test",
-      "org.scala-graph" %% "graph-core" % "1.13.5"
+      "org.scala-graph" %% "graph-core" % "1.13.5",
+      "com.lihaoyi" %% "sourcecode" % "0.3.1"
     )
   )
   .settings( // Settings for scalafix
diff --git a/common.mk b/common.mk
index b31ddafc..dff235a9 100644
--- a/common.mk
+++ b/common.mk
@@ -194,7 +194,7 @@ SFC_MFC_TARGETS = \
 	$(GEN_COLLATERAL_DIR)
 
 SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
-MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket
+MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,disallowPortDeclSharing,locationInfoStyle=wrapInAtSquareBracket
 
 # DOC include start: FirrtlCompiler
 # There are two possible cases for this step. In the first case, SFC
@@ -311,8 +311,13 @@ $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_S
 # note: {MODEL,TOP}_BB_MODS_FILELIST is added as a req. so that the files get generated,
 #       however it is really unneeded since ALL_MODS_FILELIST includes all BB files
 ########################################################################################
-$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE) $(BB_MODS_FILELIST)
-	sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' > $@
+$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE) $(BB_MODS_FILELIST) $(EXT_FILELISTS)
+ifneq (,$(EXT_FILELISTS))
+	cat $(EXT_FILELISTS) > $@
+else
+	rm -f $@
+endif
+	sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' >> $@
 	echo "$(TOP_SMEMS_FILE)" >> $@
 	echo "$(MODEL_SMEMS_FILE)" >> $@
 
@@ -372,14 +377,27 @@ run-binary: check-binary $(BINARY).run
 run-binaries: check-binaries $(addsuffix .run,$(BINARIES))
 
 %.run: %.check-exists $(SIM_PREREQ) | $(output_dir)
-	(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $* </dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
+	(set -o pipefail && $(NUMA_PREFIX) $(sim) \
+		$(PERMISSIVE_ON) \
+		$(call get_common_sim_flags,$*) \
+		$(VERBOSE_FLAGS) \
+		$(PERMISSIVE_OFF) \
+		$* \
+		$(BINARY_ARGS) \
+		</dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
 
 # run simulator as fast as possible (no insn disassembly)
 run-binary-fast: check-binary $(BINARY).run.fast
 run-binaries-fast: check-binaries $(addsuffix .run.fast,$(BINARIES))
 
 %.run.fast: %.check-exists $(SIM_PREREQ) | $(output_dir)
-	(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(PERMISSIVE_OFF) $* </dev/null | tee $(call get_sim_out_name,$*).log)
+	(set -o pipefail && $(NUMA_PREFIX) $(sim) \
+		$(PERMISSIVE_ON) \
+		$(call get_common_sim_flags,$*) \
+		$(PERMISSIVE_OFF) \
+		$* \
+		$(BINARY_ARGS) \
+		</dev/null | tee $(call get_sim_out_name,$*).log)
 
 # run simulator with as much debug info as possible
 run-binary-debug: check-binary $(BINARY).run.debug
@@ -387,7 +405,15 @@ run-binaries-debug: check-binaries $(addsuffix .run.debug,$(BINARIES))
 
 %.run.debug: %.check-exists $(SIM_DEBUG_PREREQ) | $(output_dir)
 	if [ "$*" != "none" ]; then riscv64-unknown-elf-objdump -D -S $* > $(call get_sim_out_name,$*).dump ; fi
-	(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(VERBOSE_FLAGS) $(call get_waveform_flag,$(call get_sim_out_name,$*)) $(PERMISSIVE_OFF) $* </dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
+	(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) \
+		$(PERMISSIVE_ON) \
+		$(call get_common_sim_flags,$*) \
+		$(VERBOSE_FLAGS) \
+		$(call get_waveform_flag,$(call get_sim_out_name,$*)) \
+		$(PERMISSIVE_OFF) \
+		$* \
+		$(BINARY_ARGS) \
+		</dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
 
 run-fast: run-asm-tests-fast run-bmark-tests-fast
 
diff --git a/conda-reqs/chipyard-base.yaml b/conda-reqs/chipyard-base.yaml
index 59b02ef8..f1ab3a26 100644
--- a/conda-reqs/chipyard-base.yaml
+++ b/conda-reqs/chipyard-base.yaml
@@ -14,8 +14,8 @@ dependencies:
     #   instructions on adding a recipe
     # https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications
     #   documentation on package_spec syntax for constraining versions
-    - gcc<12
-    - gxx<12
+    - gcc=13.2
+    - gxx=13.2
     - sysroot_linux-64=2.17 # needed to match pre-built CI XRT glibc version
     - conda-gcc-specs
     - binutils
@@ -31,5 +31,5 @@ dependencies:
     - sbt
     - openjdk=20
     - dtc
-    - verilator==5.020
+    - verilator==5.022
     - conda-lock=1.4
diff --git a/conda-reqs/circt.json b/conda-reqs/circt.json
index 3b5ca63a..1eb54a43 100644
--- a/conda-reqs/circt.json
+++ b/conda-reqs/circt.json
@@ -1,3 +1,3 @@
 {
-  "version": "firtool-1.61.0"
+  "version": "firtool-1.66.0"
 }
diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64-lean.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64-lean.conda-lock.yml
index 41b9d9a9..9a4aabe8 100644
--- a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64-lean.conda-lock.yml
+++ b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64-lean.conda-lock.yml
@@ -9,7 +9,7 @@
 # To update a single package to the latest version compatible with the version constraints in the source:
 #     conda-lock lock  --lockfile conda-requirements-esp-tools-linux-64-lean.conda-lock.yml --update PACKAGE
 # To re-solve the entire environment, e.g. after changing a version constraint in the source file:
-#     conda-lock -f /scratch/hansung/chipyard-gpu/conda-reqs/chipyard-base.yaml -f /scratch/hansung/chipyard-gpu/conda-reqs/docs.yaml -f /scratch/hansung/chipyard-gpu/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64-lean.conda-lock.yml
+#     conda-lock -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/chipyard-base.yaml -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/docs.yaml -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64-lean.conda-lock.yml
 metadata:
   channels:
   - url: ucb-bar
@@ -21,13 +21,13 @@ metadata:
   - url: nodefaults
     used_env_vars: []
   content_hash:
-    linux-64: b3d6181ced7140e828bceb01703958b116fa5c544d3f5a8ce512f808f5ed3c35
+    linux-64: 82a67811dd17c821d0f6126f25e6fc23833d67f6b990ee3139ff0bea2b0ddf59
   platforms:
   - linux-64
   sources:
-  - /scratch/hansung/chipyard-gpu/conda-reqs/chipyard-base.yaml
-  - /scratch/hansung/chipyard-gpu/conda-reqs/docs.yaml
-  - /scratch/hansung/chipyard-gpu/conda-reqs/esp-tools.yaml
+  - /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/chipyard-base.yaml
+  - /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/docs.yaml
+  - /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/esp-tools.yaml
 package:
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   dependencies: {}
@@ -43,13 +43,13 @@ package:
 - category: main
   dependencies: {}
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   manager: conda
   name: _sysroot_linux-64_curr_repodata_hack
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h69a702a_13.conda
+  url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h69a702a_14.conda
   version: '3'
 - category: main
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@@ -120,25 +120,25 @@ package:
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   manager: conda
   name: libgcc-devel_linux-64
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/libgcc-devel_linux-64-11.4.0-h922705a_105.conda
-  version: 11.4.0
+  url: https://conda.anaconda.org/conda-forge/noarch/libgcc-devel_linux-64-13.2.0-ha9c7c90_105.conda
+  version: 13.2.0
 - category: main
   dependencies: {}
   hash:
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-    sha256: 20c4f2b96b8fb57a3cad0bb8f1ce407ee7bc935cb0ce68b430b10b77616c0b16
+    md5: 66383205c2e1bdf013df52fa9e3e6763
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   manager: conda
   name: libstdcxx-devel_linux-64
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/libstdcxx-devel_linux-64-11.4.0-h922705a_105.conda
-  version: 11.4.0
+  url: https://conda.anaconda.org/conda-forge/noarch/libstdcxx-devel_linux-64-13.2.0-ha9c7c90_105.conda
+  version: 13.2.0
 - category: main
   dependencies: {}
   hash:
@@ -191,13 +191,13 @@ package:
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     _sysroot_linux-64_curr_repodata_hack: 3.*
   hash:
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-    sha256: 67a3caa56e2a59f407f3d290437b865aaf996873006e2fcfca6295d0f0be8db9
+    md5: f6c14886b1695a2462d296176e831080
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   manager: conda
   name: kernel-headers_linux-64
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/kernel-headers_linux-64-3.10.0-h4a8ded7_13.tar.bz2
+  url: https://conda.anaconda.org/conda-forge/noarch/kernel-headers_linux-64-3.10.0-h4a8ded7_14.conda
   version: 3.10.0
 - category: main
   dependencies:
@@ -239,15 +239,15 @@ package:
 - category: main
   dependencies:
     _sysroot_linux-64_curr_repodata_hack: 3.*
-    kernel-headers_linux-64: 3.10.0 h4a8ded7_13
+    kernel-headers_linux-64: 3.10.0 h4a8ded7_14
   hash:
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-    sha256: f09f2fea4b571dcd225f1e35bd3c851e809cd4c2f5f151438133969ab28478e5
+    md5: d5f7a1cca06f56e6ac2b525f199f9b9e
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   manager: conda
   name: sysroot_linux-64
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/sysroot_linux-64-2.17-h4a8ded7_13.tar.bz2
+  url: https://conda.anaconda.org/conda-forge/noarch/sysroot_linux-64-2.17-h4a8ded7_14.conda
   version: '2.17'
 - category: main
   dependencies:
@@ -279,14 +279,14 @@ package:
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   hash:
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-    sha256: 51147922bad9d3176e780eb26f748f380cd3184896a9f9125d8ac64fe330158b
+    md5: 0bb492cca54017ea314b809b1ee3a176
+    sha256: 0e2b75b9834a6e520b13db516f7cf5c9cea8f0bbc9157c978444173dacb98fec
   manager: conda
   name: alsa-lib
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/alsa-lib-1.2.10-hd590300_0.conda
-  version: 1.2.10
+  url: https://conda.anaconda.org/conda-forge/linux-64/alsa-lib-1.2.11-hd590300_1.conda
+  version: 1.2.11
 - category: main
   dependencies:
     binutils_impl_linux-64: '>=2.40,<2.41.0a0'
@@ -315,14 +315,14 @@ package:
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   hash:
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-    sha256: 3771589a91303710a59d1d40bbcdca43743969fe993ea576538ba375ac8ab0fa
+    md5: f6afff0e9ee08d2f1b897881a4f38cdb
+    sha256: 2a5866b19d28cb963fab291a62ff1c884291b9d6f59de14643e52f103e255749
   manager: conda
   name: c-ares
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/c-ares-1.26.0-hd590300_0.conda
-  version: 1.26.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/c-ares-1.27.0-hd590300_0.conda
+  version: 1.27.0
 - category: main
   dependencies:
     libgcc-ng: '>=12'
@@ -364,13 +364,13 @@ package:
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     libstdcxx-ng: '>=12'
   hash:
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-    sha256: 2a50495b6bbbacb03107ea0b752d8358d4a40b572d124a8cade068c147f344f5
+    md5: e358c7c5f6824c272b5034b3816438a7
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   manager: conda
   name: gmp
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/gmp-6.3.0-h59595ed_0.conda
+  url: https://conda.anaconda.org/conda-forge/linux-64/gmp-6.3.0-h59595ed_1.conda
   version: 6.3.0
 - category: main
   dependencies:
@@ -451,14 +451,14 @@ package:
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   manager: conda
   name: libexpat
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/libexpat-2.5.0-hcb278e6_1.conda
-  version: 2.5.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/libexpat-2.6.1-h59595ed_0.conda
+  version: 2.6.1
 - category: main
   dependencies:
     libgcc-ng: '>=12'
@@ -521,16 +521,16 @@ package:
   version: 2.0.1
 - category: main
   dependencies:
-    libgcc-ng: '>=11.4.0'
+    libgcc-ng: '>=13.2.0'
   hash:
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-    sha256: fc00e9a71c07446cf1744bd1d5cd3efa6dfd3a7db6c2c8a82853f19b8b1416f8
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   manager: conda
   name: libsanitizer
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/libsanitizer-11.4.0-h4dcbe23_5.conda
-  version: 11.4.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/libsanitizer-13.2.0-h7e041cc_5.conda
+  version: 13.2.0
 - category: main
   dependencies:
     libgcc-ng: '>=12'
@@ -813,17 +813,17 @@ package:
   version: 1.6.1
 - category: main
   dependencies:
-    libexpat: 2.5.0 hcb278e6_1
+    libexpat: 2.6.1 h59595ed_0
     libgcc-ng: '>=12'
   hash:
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-    sha256: 36dfeb4375059b3bba75ce9b38c29c69fd257342a79e6cf20e9f25c1523f785f
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   manager: conda
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   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/expat-2.5.0-hcb278e6_1.conda
-  version: 2.5.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/expat-2.6.1-h59595ed_0.conda
+  version: 2.6.1
 - category: main
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@@ -841,21 +841,21 @@ package:
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-    libgcc-devel_linux-64: 11.4.0 h922705a_105
-    libgcc-ng: '>=11.4.0'
-    libgomp: '>=11.4.0'
-    libsanitizer: 11.4.0 h4dcbe23_5
-    libstdcxx-ng: '>=11.4.0'
+    libgcc-devel_linux-64: 13.2.0 ha9c7c90_105
+    libgcc-ng: '>=13.2.0'
+    libgomp: '>=13.2.0'
+    libsanitizer: 13.2.0 h7e041cc_5
+    libstdcxx-ng: '>=13.2.0'
     sysroot_linux-64: ''
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-  url: https://conda.anaconda.org/conda-forge/linux-64/gcc_impl_linux-64-11.4.0-h7aa1c59_5.conda
-  version: 11.4.0
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+  version: 13.2.0
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@@ -904,27 +904,27 @@ package:
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   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/libpng-1.6.42-h2797004_0.conda
-  version: 1.6.42
+  url: https://conda.anaconda.org/conda-forge/linux-64/libpng-1.6.43-h2797004_0.conda
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-  url: https://conda.anaconda.org/conda-forge/linux-64/libsqlite-3.44.2-h2797004_0.conda
-  version: 3.44.2
+  url: https://conda.anaconda.org/conda-forge/linux-64/libsqlite-3.45.2-h2797004_0.conda
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   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/pcre2-10.42-hcad00b1_0.conda
-  version: '10.42'
+  url: https://conda.anaconda.org/conda-forge/linux-64/pcre2-10.43-hcad00b1_0.conda
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@@ -1090,16 +1090,16 @@ package:
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+    gcc_impl_linux-64: '>=13.2.0,<13.2.1.0a0'
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-  version: 11.4.0
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@@ -1116,30 +1116,30 @@ package:
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+    gcc_impl_linux-64: 13.2.0 h338b0a0_5
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@@ -1158,22 +1158,19 @@ package:
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-  version: 2.78.3
+  url: https://conda.anaconda.org/conda-forge/linux-64/libglib-2.80.0-hf2295e7_0.conda
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@@ -1448,17 +1445,17 @@ package:
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 - category: main
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+    gcc: 13.2.0.*
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-    sha256: e07c2da262b374fc9aad422a4927660ef96aec6d1445c7673a6ba58a445523a5
+    md5: 8988c1eaea17d0cec6af9da7b6241e3b
+    sha256: 433ea239bca69f64c4262d4d660f7511a925b7a2819d096554c9788e35d46371
   manager: conda
   name: gxx
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/gxx-11.4.0-h7baecda_2.conda
-  version: 11.4.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/gxx-13.2.0-hd6cf55c_3.conda
+  version: 13.2.0
 - category: main
   dependencies:
     python: '>=3.6'
@@ -1585,16 +1582,16 @@ package:
   version: 1.0.7
 - category: main
   dependencies:
-    python: '>=3.7'
+    python: '>=3.8'
   hash:
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-    sha256: 69b3ace6cca2dab9047b2c24926077d81d236bef45329d264b394001e3c3e52f
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   manager: conda
   name: packaging
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/packaging-23.2-pyhd8ed1ab_0.conda
-  version: '23.2'
+  url: https://conda.anaconda.org/conda-forge/noarch/packaging-24.0-pyhd8ed1ab_0.conda
+  version: '24.0'
 - category: main
   dependencies:
     python: '>=2.7'
@@ -1609,16 +1606,16 @@ package:
   version: 0.2.1
 - category: main
   dependencies:
-    python: '>=3.6'
+    python: '>=3.7'
   hash:
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-    sha256: 7ea5a5af62a15376d9f4f9f3c134874d0b0710f39be719e849b7fa9ca8870502
+    md5: 8c6a4a704308f5d91f3a974a72db1096
+    sha256: 3e833f907039646e34d23203cd5c9cc487a451d955d8c8d6581e18a8ccef4cee
   manager: conda
   name: pkginfo
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/pkginfo-1.9.6-pyhd8ed1ab_0.conda
-  version: 1.9.6
+  url: https://conda.anaconda.org/conda-forge/noarch/pkginfo-1.10.0-pyhd8ed1ab_0.conda
+  version: 1.10.0
 - category: main
   dependencies:
     python: '>=3.8'
@@ -1713,26 +1710,26 @@ package:
     python: '>=3.9,<3.10.0a0'
     python_abi: 3.9.* *_cp39
   hash:
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-    sha256: 06b089d59ffebef9c9171a8a3480adcb6e7f112caef9f8b87591207427cb1cf1
+    md5: b1961e70cfe8e1eac243faf933d1813f
+    sha256: 32b7b4f13493eeff0d18de85d58d7b8c2b04234ea737b8769871067189c70d69
   manager: conda
   name: ruamel.yaml.clib
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml.clib-0.2.7-py39hd1e30aa_2.conda
-  version: 0.2.7
+  url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml.clib-0.2.8-py39hd1e30aa_0.conda
+  version: 0.2.8
 - category: main
   dependencies:
-    python: '>=3.7'
+    python: '>=3.8'
   hash:
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-    sha256: 0fe2a0473ad03dac6c7f5c42ef36a8e90673c88a0350dfefdea4b08d43803db2
+    md5: da214ecd521a720a9d521c68047682dc
+    sha256: 78a75c75a5dacda6de5f4056c9c990141bdaf4f64245673a590594d00bc63713
   manager: conda
   name: setuptools
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/setuptools-69.0.3-pyhd8ed1ab_0.conda
-  version: 69.0.3
+  url: https://conda.anaconda.org/conda-forge/noarch/setuptools-69.2.0-pyhd8ed1ab_0.conda
+  version: 69.2.0
 - category: main
   dependencies:
     python: ''
@@ -1785,14 +1782,14 @@ package:
   dependencies:
     python: '>=3.7'
   hash:
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-    sha256: 53cc436ab92d38683df1320e4468a8b978428e800195bf1c8c2460e90b0bc117
+    md5: 37c47ea93ef00dd80d880fc4ba21256a
+    sha256: 8d45c266bf919788abacd9828f4a2101d7216f6d4fc7c8d3417034fe0d795a18
   manager: conda
   name: tomlkit
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/tomlkit-0.12.3-pyha770c72_0.conda
-  version: 0.12.3
+  url: https://conda.anaconda.org/conda-forge/noarch/tomlkit-0.12.4-pyha770c72_0.conda
+  version: 0.12.4
 - category: main
   dependencies:
     python: '>=3.7'
@@ -1811,26 +1808,26 @@ package:
     python: '>=3.9,<3.10.0a0'
     python_abi: 3.9.* *_cp39
   hash:
-    md5: cbe186eefb0bcd91e8f47c3908489874
-    sha256: dc0df742be0e83a4286137d21f60ca829632c2ffd66d3bebb603afe5ce74cc68
+    md5: 1e865e9188204cdfb1fd2531780add88
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   manager: conda
   name: tornado
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/tornado-6.3.3-py39hd1e30aa_1.conda
-  version: 6.3.3
+  url: https://conda.anaconda.org/conda-forge/linux-64/tornado-6.4-py39hd1e30aa_0.conda
+  version: '6.4'
 - category: main
   dependencies:
     python: '>=3.8'
   hash:
-    md5: a92a6440c3fe7052d63244f3aba2a4a7
-    sha256: f3c5be8673bfd905c4665efcb27fa50192f24f84fa8eff2f19cba5d09753d905
+    md5: 16ae769069b380646c47142d719ef466
+    sha256: 4be24d557897b2f6609f5d5f7c437833c62f4d4a96581e39530067e96a2d0451
   manager: conda
   name: typing_extensions
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/typing_extensions-4.9.0-pyha770c72_0.conda
-  version: 4.9.0
+  url: https://conda.anaconda.org/conda-forge/noarch/typing_extensions-4.10.0-pyha770c72_0.conda
+  version: 4.10.0
 - category: main
   dependencies:
     flex: '>=2.6.4,<3.0a0'
@@ -1842,14 +1839,14 @@ package:
     perl: ''
     python: ''
   hash:
-    md5: 0b2929f84fe7d3a6117439507d5d50d9
-    sha256: 1d6af07d2d19be7adc296e8b6c43bd3eb12b48d8ab8e0cec566e8f9872661813
+    md5: d628a7f32222786b70ad81e56dd4a61a
+    sha256: 1648f885c97e5189adb12a70eef72699885a4e9e882ea385c3cd904baed251ce
   manager: conda
   name: verilator
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/verilator-5.020-h7cd9344_0.conda
-  version: '5.020'
+  url: https://conda.anaconda.org/conda-forge/linux-64/verilator-5.022-h7cd9344_0.conda
+  version: '5.022'
 - category: main
   dependencies:
     python: '>=2.6'
@@ -2067,27 +2064,27 @@ package:
     python: '>=3.8'
     zipp: '>=0.5'
   hash:
-    md5: 746623a787e06191d80a2133e5daff17
-    sha256: e72d05f171f4567004c9360a838e9d5df21e23dcfeb945066b53a6e5f754b861
+    md5: b050a4bb0e90ebd6e7fa4093d6346867
+    sha256: 9a26136d2cc81ccac209d6ae24281ceba3365fe34e34b2c45570f2a96e9d9c1b
   manager: conda
   name: importlib-metadata
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-7.0.1-pyha770c72_0.conda
-  version: 7.0.1
+  url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-7.0.2-pyha770c72_0.conda
+  version: 7.0.2
 - category: main
   dependencies:
     more-itertools: ''
     python: '>=3.7'
   hash:
-    md5: e9f79248d30e942f7c358ff21a1790f5
-    sha256: 14f5240c3834e1b784dd41a5a14392d9150dff62a74ae851f73e65d2e2bbd891
+    md5: c541ae264c9f1f21d83fc30dffb908ee
+    sha256: 232b40de8176fa7fb66a893653f8ae03c29616e04a83dae5a47df94b74e256ca
   manager: conda
   name: jaraco.classes
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/jaraco.classes-3.3.0-pyhd8ed1ab_0.conda
-  version: 3.3.0
+  url: https://conda.anaconda.org/conda-forge/noarch/jaraco.classes-3.3.1-pyhd8ed1ab_0.conda
+  version: 3.3.1
 - category: main
   dependencies:
     markupsafe: '>=2.0'
@@ -2136,28 +2133,27 @@ package:
     python: '>=3.9,<3.10.0a0'
     python_abi: 3.9.* *_cp39
     ruamel.yaml.clib: '>=0.1.2'
-    setuptools: ''
   hash:
-    md5: 2b447c949fba3e4c95e7f7dae77f5ebd
-    sha256: 78638b0ef756443722f91a3bc0225b1ac79757be3d1f313a754c49cd3a3e2227
+    md5: 2289054e90cf07e35280bbe798811dc8
+    sha256: 9cfb534d18a1c060d876762806752d6a3d253727f255c65e5473810dd1dd4231
   manager: conda
   name: ruamel.yaml
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml-0.18.5-py39hd1e30aa_0.conda
-  version: 0.18.5
+  url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml-0.18.6-py39hd1e30aa_0.conda
+  version: 0.18.6
 - category: main
   dependencies:
-    typing_extensions: 4.9.0 pyha770c72_0
+    typing_extensions: 4.10.0 pyha770c72_0
   hash:
-    md5: c16524c1b7227dc80b36b4fa6f77cc86
-    sha256: d795c1eb1db4ea147f01ece74e5a504d7c2e8d5ee8c11ec987884967dd938f9c
+    md5: 091683b9150d2ebaa62fd7e2c86433da
+    sha256: 0698fe2c4e555fb44c27c60f7a21fa0eea7f5bf8186ad109543c5b056e27f96a
   manager: conda
   name: typing-extensions
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/typing-extensions-4.9.0-hd8ed1ab_0.conda
-  version: 4.9.0
+  url: https://conda.anaconda.org/conda-forge/noarch/typing-extensions-4.10.0-hd8ed1ab_0.conda
+  version: 4.10.0
 - category: main
   dependencies:
     brotli-python: '>=1.0.9'
@@ -2179,14 +2175,14 @@ package:
     platformdirs: <5,>=3.9.1
     python: '>=3.8'
   hash:
-    md5: c119653cba436d8183c27bf6d190e587
-    sha256: 50827c3721a9dbf973b568709d4381add2a6552fa562f26a385c5edc16a534af
+    md5: 8797a4e26be36880a603aba29c785352
+    sha256: 1ced4445cf72cd9dc344ad04bdaf703a08cc428c8c46e4bda928ad79786ee153
   manager: conda
   name: virtualenv
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.25.0-pyhd8ed1ab_0.conda
-  version: 20.25.0
+  url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.25.1-pyhd8ed1ab_0.conda
+  version: 20.25.1
 - category: main
   dependencies:
     libgcc-ng: '>=9.3.0'
@@ -2220,18 +2216,18 @@ package:
   dependencies:
     cffi: '>=1.12'
     libgcc-ng: '>=12'
-    openssl: '>=3.1.5,<4.0a0'
+    openssl: '>=3.2.1,<4.0a0'
     python: '>=3.9,<3.10.0a0'
     python_abi: 3.9.* *_cp39
   hash:
-    md5: fee371764cdabeffc4f89a06688deb08
-    sha256: 56b8d01515d58bf5e368f01286485f9f3095bbede487ffa9f9367f6978eba07f
+    md5: 74adeac31d6368a9dcf1a867a052cffa
+    sha256: dbde9bd3cc0400cdefbdfe7a41ddb7cb33efc472dbd291485308eb5f5830f1a9
   manager: conda
   name: cryptography
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/cryptography-42.0.2-py39he6105cc_0.conda
-  version: 42.0.2
+  url: https://conda.anaconda.org/conda-forge/linux-64/cryptography-42.0.5-py39hd4f0224_0.conda
+  version: 42.0.5
 - category: main
   dependencies:
     curl: ''
@@ -2240,18 +2236,18 @@ package:
     libgcc-ng: '>=12'
     libiconv: '>=1.17,<2.0a0'
     libzlib: '>=1.2.13,<1.3.0a0'
-    openssl: '>=3.2.0,<4.0a0'
-    pcre2: '>=10.42,<10.43.0a0'
+    openssl: '>=3.2.1,<4.0a0'
+    pcre2: '>=10.43,<10.44.0a0'
     perl: 5.*
   hash:
-    md5: 851970792301b407ba4c35e75e796791
-    sha256: 73a065e160d759e8fb0b169e615955a8fe0c148ed00c7f6ddf076f2e4adfd765
+    md5: 6817894081347566c0f097216bb36faa
+    sha256: 3ca58462b1c79a288587f8bdb82aa55829586e3f1635650988ab95d845b1b68e
   manager: conda
   name: git
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/git-2.43.0-pl5321h7bc287a_0.conda
-  version: 2.43.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/git-2.44.0-pl5321h709897a_0.conda
+  version: 2.44.0
 - category: main
   dependencies:
     cairo: '>=1.18.0,<2.0a0'
@@ -2272,16 +2268,16 @@ package:
   version: 8.3.0
 - category: main
   dependencies:
-    importlib-metadata: '>=7.0.1,<7.0.2.0a0'
+    importlib-metadata: '>=7.0.2,<7.0.3.0a0'
   hash:
-    md5: 4a2f43a20fa404b998859c6a470ba316
-    sha256: bc362df1d4f5a04c38dff29cd9c2d0ac584f9c4b45d3e4683ee090944a38fba4
+    md5: d11132727a247f2c1998779a2af743a1
+    sha256: b250e6a3e741b762bb2caf05119feb6245cb41b468542e5a9263cd01671098f7
   manager: conda
   name: importlib_metadata
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/importlib_metadata-7.0.1-hd8ed1ab_0.conda
-  version: 7.0.1
+  url: https://conda.anaconda.org/conda-forge/noarch/importlib_metadata-7.0.2-hd8ed1ab_0.conda
+  version: 7.0.2
 - category: main
   dependencies:
     libgcc-ng: '>=12'
@@ -2289,14 +2285,14 @@ package:
     python_abi: 3.9.* *_cp39
     typing-extensions: '>=4.6.0,!=4.7.0'
   hash:
-    md5: bf093850e0507bfaf8c1cabfd277d06b
-    sha256: 8896019379cab43cff61c8f16166db9f328317590fe61d897bb9ce8df2b7e900
+    md5: 35fef239167838ec05bc714a70fbd6d9
+    sha256: c0c9ebdcd812ac6c35e85a37bae966b461b5d390aeecf168611c4abd43c947a8
   manager: conda
   name: pydantic-core
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/pydantic-core-2.16.2-py39h9fdd4d6_0.conda
-  version: 2.16.2
+  url: https://conda.anaconda.org/conda-forge/linux-64/pydantic-core-2.16.3-py39h9fdd4d6_0.conda
+  version: 2.16.3
 - category: main
   dependencies:
     certifi: '>=2017.4.17'
@@ -2363,7 +2359,7 @@ package:
   version: 1.4.4
 - category: main
   dependencies:
-    alsa-lib: '>=1.2.10,<1.2.11.0a0'
+    alsa-lib: '>=1.2.10,<1.3.0.0a0'
     fontconfig: '>=2.14.2,<3.0a0'
     fonts-conda-ecosystem: ''
     freetype: '>=2.12.1,<3.0a0'
@@ -2394,18 +2390,18 @@ package:
 - category: main
   dependencies:
     annotated-types: '>=0.4.0'
-    pydantic-core: 2.16.2
+    pydantic-core: 2.16.3
     python: '>=3.7'
     typing-extensions: '>=4.6.1'
   hash:
-    md5: 3b1698c91820d852d802fc21471f52d8
-    sha256: 27083637287bb08a93e28616b5030f5eab31deb83d16fc132901ada987a62cfa
+    md5: 4f4e78b41c489b89d98719fcbde09361
+    sha256: 7367461b8f9e309f20f129605daa78635a1daa2538fe0b40d7f7238f8d430a29
   manager: conda
   name: pydantic
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/pydantic-2.6.1-pyhd8ed1ab_0.conda
-  version: 2.6.1
+  url: https://conda.anaconda.org/conda-forge/noarch/pydantic-2.6.3-pyhd8ed1ab_0.conda
+  version: 2.6.3
 - category: main
   dependencies:
     cryptography: ''
@@ -2445,14 +2441,14 @@ package:
     python_abi: 3.9.* *_cp39
     secretstorage: '>=3.2'
   hash:
-    md5: 1426c4f9994cb7e55859b44b98bc7b3e
-    sha256: a7538a914feb54dc3e7ee46431af5f0a40e668b29224998e6d3be044a1a7606e
+    md5: 2482396e5d629d60526bce6268cfde6a
+    sha256: 8d231971f2ab5a9ab17d0b792021e287b982cb28c5258a93076a7fb937fa40c5
   manager: conda
   name: keyring
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/keyring-24.3.0-py39hf3d152e_0.conda
-  version: 24.3.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/keyring-24.3.1-py39hf3d152e_0.conda
+  version: 24.3.1
 - category: main
   dependencies:
     __unix: ''
diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
index c5ec730b..12cca34f 100644
--- a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
+++ b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
@@ -9,7 +9,7 @@
 # To update a single package to the latest version compatible with the version constraints in the source:
 #     conda-lock lock  --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml --update PACKAGE
 # To re-solve the entire environment, e.g. after changing a version constraint in the source file:
-#     conda-lock -f /scratch/hansung/chipyard-gpu/conda-reqs/chipyard-base.yaml -f /scratch/hansung/chipyard-gpu/conda-reqs/chipyard-extended.yaml -f /scratch/hansung/chipyard-gpu/conda-reqs/docs.yaml -f /scratch/hansung/chipyard-gpu/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml
+#     conda-lock -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/chipyard-base.yaml -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/chipyard-extended.yaml -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/docs.yaml -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml
 metadata:
   channels:
   - url: ucb-bar
@@ -21,14 +21,14 @@ metadata:
   - url: nodefaults
     used_env_vars: []
   content_hash:
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-  - /scratch/hansung/chipyard-gpu/conda-reqs/docs.yaml
-  - /scratch/hansung/chipyard-gpu/conda-reqs/esp-tools.yaml
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+    md5: 2482396e5d629d60526bce6268cfde6a
+    sha256: 8d231971f2ab5a9ab17d0b792021e287b982cb28c5258a93076a7fb937fa40c5
   manager: conda
   name: keyring
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/keyring-24.3.0-py39hf3d152e_0.conda
-  version: 24.3.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/keyring-24.3.1-py39hf3d152e_0.conda
+  version: 24.3.1
 - category: main
   dependencies:
     cairo: '>=1.18.0,<2.0a0'
@@ -5465,14 +5451,14 @@ package:
     python_abi: 3.9.* *_cp39
     tk: '>=8.6.13,<8.7.0a0'
   hash:
-    md5: 6085411aa2f0b2b801d3b46e1d3b83c5
-    sha256: f5e1275e1e7f644d5c91780c08f9868153b8b1a00703e7b03f4b171be02879e1
+    md5: 5456bdfe5809ebf5689eda6c808b686e
+    sha256: 6a430a5816f189b7277182b6c251236c5af22e254b8253eeb6ffcb06a8ea7087
   manager: conda
   name: matplotlib-base
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/matplotlib-base-3.8.2-py39he9076e7_0.conda
-  version: 3.8.2
+  url: https://conda.anaconda.org/conda-forge/linux-64/matplotlib-base-3.8.3-py39he9076e7_0.conda
+  version: 3.8.3
 - category: main
   dependencies:
     libsecret: ''
@@ -5515,14 +5501,14 @@ package:
     pyyaml: '>=5.1'
     virtualenv: '>=20.10.0'
   hash:
-    md5: 473a7cfca197da0a10cff3f6dded7d4b
-    sha256: 7d1f4b4a2eb4946b5808769642c5f643788c3a9e090f1c02a6c63f8794fb3d54
+    md5: 61534ee57ffdf26d7b1b514d33daccc4
+    sha256: 8eb9f5965c37d2bbee9302e16cc7c5517ee06491986356112be13431a043681e
   manager: conda
   name: pre-commit
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.6.0-pyha770c72_0.conda
-  version: 3.6.0
+  url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.6.2-pyha770c72_0.conda
+  version: 3.6.2
 - category: main
   dependencies:
     __unix: ''
@@ -5544,14 +5530,14 @@ package:
     python: '>=3.7,<4.0'
     typing-extensions: '>=4.4'
   hash:
-    md5: 7e09df6905a73a73cb3a0681ac824bb1
-    sha256: 1cb6e0d220fd183e6e4701c6867c4dc53daef40e1acaedb5378fee97e7ac0e97
+    md5: 250e721935d1b8feb2a17f24120c5e06
+    sha256: f1205b9438e8947fc0a3b70eabe07e6ef25c2bc228edb2ca3a26010c5f0a2e71
   manager: conda
   name: aws-sam-translator
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/aws-sam-translator-1.84.0-pyhd8ed1ab_0.conda
-  version: 1.84.0
+  url: https://conda.anaconda.org/conda-forge/noarch/aws-sam-translator-1.86.0-pyhd8ed1ab_0.conda
+  version: 1.86.0
 - category: main
   dependencies:
     azure-core: <2.0.0,>=1.23.0
@@ -5574,14 +5560,14 @@ package:
     python: ''
     typing_extensions: ''
   hash:
-    md5: d3c13aa8a3841ba9e53527b07de04933
-    sha256: af230542beef11d7d5b5ee0e9a144272ab99c28477b3fbd6fc0e2f626fbc8849
+    md5: 53366303b332b3bd2570a2df27f0d78b
+    sha256: 4082c623a4913c8737302397419a382585ff2df14a7a8153e3696d7c9cee9e2b
   manager: conda
   name: boto3-stubs
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.34.35-pyhd8ed1ab_0.conda
-  version: 1.34.35
+  url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.34.61-pyhd8ed1ab_0.conda
+  version: 1.34.61
 - category: main
   dependencies:
     archspec: ''
@@ -5686,14 +5672,14 @@ package:
     python: '>=3.6'
     typing-extensions: ''
   hash:
-    md5: 41b56eb093c6e10e3fd211656ad4e74e
-    sha256: 758fd7af61990c9890c2895a71b9e2644d41296a8461bc4a5aa838486b664eaa
+    md5: c9f10150ad5f625b48294a07a1d54d40
+    sha256: 29b7a44c9a2bbe8ca088e8e96f59679aed392f35e135a579bd6c357208ef572d
   manager: conda
   name: mypy_boto3_ec2
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.34.30-pyhd8ed1ab_0.conda
-  version: 1.34.30
+  url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.34.61-pyhd8ed1ab_0.conda
+  version: 1.34.61
 - category: main
   dependencies:
     importlib_resources: '>=5.8,<7.0'
@@ -5727,7 +5713,7 @@ package:
   version: 0.4.2
 - category: main
   dependencies:
-    aws-sam-translator: '>=1.83.0'
+    aws-sam-translator: '>=1.85.0'
     jschema-to-python: '>=1.2.3,<1.3.dev0'
     jsonpatch: ''
     jsonschema: '>=3.0,<5'
@@ -5739,14 +5725,14 @@ package:
     sarif-om: '>=1.0.4,<1.1.dev0'
     sympy: '>=1.0.0'
   hash:
-    md5: 2b97c7ed3caa28a40105b787c2408a15
-    sha256: ec6912b46231c9f89bba709bc5bb32e5d9c3957a1821ec418c16415b4245360d
+    md5: d2b123d03e90c526da05a58d32c1ccc9
+    sha256: 18b972f8ed1ede9a6c8aade643180f4fceb45c2d4b24632bf1deb795cf07b732
   manager: conda
   name: cfn-lint
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.85.0-pyhd8ed1ab_0.conda
-  version: 0.85.0
+  url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.86.0-pyhd8ed1ab_0.conda
+  version: 0.86.0
 - category: main
   dependencies:
     colorama: ''
@@ -5772,14 +5758,14 @@ package:
     python: '>=3.8'
     ruamel.yaml: '>=0.11.14,<0.19'
   hash:
-    md5: d8cb2dfbc95cd06af84d11bf16572270
-    sha256: 78a2b1abf48bdb34a9902caa7bff273ed001758f0845ef0508b347d85c21ca2b
+    md5: a348959b6d5222c8b85a06e2a0c23cb8
+    sha256: 79e4ff87514ed6fb4b2c28edc73573b82837f3d032c6a1a65f4aaeec00f318d8
   manager: conda
   name: constructor
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/constructor-3.6.0-pyh55f8243_0.conda
-  version: 3.6.0
+  url: https://conda.anaconda.org/conda-forge/noarch/constructor-3.7.0-pyh55f8243_0.conda
+  version: 3.7.0
 - category: main
   dependencies:
     graphviz: '>=2.46.1'
@@ -5807,6 +5793,7 @@ package:
     idna: '>=2.5,<4'
     importlib_metadata: ''
     jinja2: '>=2.10.1'
+    joserfc: ''
     jsondiff: '>=1.1.2'
     openapi-spec-validator: '>=0.2.8'
     pyparsing: '>=3.0.7'
@@ -5822,14 +5809,14 @@ package:
     werkzeug: '>=0.5,!=2.2.0,!=2.2.1'
     xmltodict: ''
   hash:
-    md5: 0bab0cb52bb79f684915a650c5452b33
-    sha256: bb03fa39768749a64bcd4204546e3c9e348c7702bfa979ddfc73575a1b6a9ff4
+    md5: 31d81c30d7244228121e31a40c7dc612
+    sha256: 89edf678481fc620ce5bdb49b8d0f14cf43d3386ec7bd39a445b249762130241
   manager: conda
   name: moto
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/moto-5.0.1-pyhd8ed1ab_0.conda
-  version: 5.0.1
+  url: https://conda.anaconda.org/conda-forge/noarch/moto-5.0.3-pyhd8ed1ab_0.conda
+  version: 5.0.3
 - category: main
   dependencies:
     colorama: ''
diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64-lean.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64-lean.conda-lock.yml
index 6fb0aaa4..0b7f0352 100644
--- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64-lean.conda-lock.yml
+++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64-lean.conda-lock.yml
@@ -9,7 +9,7 @@
 # To update a single package to the latest version compatible with the version constraints in the source:
 #     conda-lock lock  --lockfile conda-requirements-riscv-tools-linux-64-lean.conda-lock.yml --update PACKAGE
 # To re-solve the entire environment, e.g. after changing a version constraint in the source file:
-#     conda-lock -f /scratch/hansung/chipyard-gpu/conda-reqs/chipyard-base.yaml -f /scratch/hansung/chipyard-gpu/conda-reqs/docs.yaml -f /scratch/hansung/chipyard-gpu/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64-lean.conda-lock.yml
+#     conda-lock -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/chipyard-base.yaml -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/docs.yaml -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64-lean.conda-lock.yml
 metadata:
   channels:
   - url: ucb-bar
@@ -21,13 +21,13 @@ metadata:
   - url: nodefaults
     used_env_vars: []
   content_hash:
-    linux-64: 992d6d7f85dd948e8f14b610157acfaad2453e8a2cd692e30ad1a3c340fdbd88
+    linux-64: b90f846250ea3712ec4443d75b88f209e3f4e6082da4c655963a79121db7ea28
   platforms:
   - linux-64
   sources:
-  - /scratch/hansung/chipyard-gpu/conda-reqs/chipyard-base.yaml
-  - /scratch/hansung/chipyard-gpu/conda-reqs/docs.yaml
-  - /scratch/hansung/chipyard-gpu/conda-reqs/riscv-tools.yaml
+  - /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/chipyard-base.yaml
+  - /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/docs.yaml
+  - /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/riscv-tools.yaml
 package:
 - category: main
   dependencies: {}
@@ -43,13 +43,13 @@ package:
 - category: main
   dependencies: {}
   hash:
-    md5: f6ce7955b53ae1ca83144adb3be9c600
-    sha256: 546e4eb1cbd822a66b363ec3fbdcc4fcc53853bcab57674cb46b8f3209b856f2
+    md5: 38d211c448a67f12fe693fe25df4da23
+    sha256: 0dbeaddc3d5134b5336c52ac05642533b8d1ba2e1316aa92981f4cf5b5388de0
   manager: conda
   name: _sysroot_linux-64_curr_repodata_hack
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h69a702a_13.conda
+  url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h69a702a_14.conda
   version: '3'
 - category: main
   dependencies: {}
@@ -120,25 +120,25 @@ package:
 - category: main
   dependencies: {}
   hash:
-    md5: fb94f6b17ef1a75faac2e06937dc4223
-    sha256: 86d1e11bf0b8dbc74fec07f3c71bb1b20f83e32b5b9f8625b3dc653ce00e40bd
+    md5: 3bc29a967fee57e193ce51f51c598bca
+    sha256: 858029ad4d66869c533bb5a22e95e7c044ca66c61d6f403f10d9ae074a0e360e
   manager: conda
   name: libgcc-devel_linux-64
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/libgcc-devel_linux-64-11.4.0-h922705a_105.conda
-  version: 11.4.0
+  url: https://conda.anaconda.org/conda-forge/noarch/libgcc-devel_linux-64-13.2.0-ha9c7c90_105.conda
+  version: 13.2.0
 - category: main
   dependencies: {}
   hash:
-    md5: a884fe2f11c6167f3dc62d4b1db20ced
-    sha256: 20c4f2b96b8fb57a3cad0bb8f1ce407ee7bc935cb0ce68b430b10b77616c0b16
+    md5: 66383205c2e1bdf013df52fa9e3e6763
+    sha256: 67e999ee56481844ca4ce2e61132c5c16f3f00a05daa1d0ea4b2c684eea5de5a
   manager: conda
   name: libstdcxx-devel_linux-64
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/libstdcxx-devel_linux-64-11.4.0-h922705a_105.conda
-  version: 11.4.0
+  url: https://conda.anaconda.org/conda-forge/noarch/libstdcxx-devel_linux-64-13.2.0-ha9c7c90_105.conda
+  version: 13.2.0
 - category: main
   dependencies: {}
   hash:
@@ -191,13 +191,13 @@ package:
   dependencies:
     _sysroot_linux-64_curr_repodata_hack: 3.*
   hash:
-    md5: 523bc836a954faf0cca94831971bb85a
-    sha256: 67a3caa56e2a59f407f3d290437b865aaf996873006e2fcfca6295d0f0be8db9
+    md5: f6c14886b1695a2462d296176e831080
+    sha256: 604b9345a7a1474b7eb33260e382446754d16eed754b853d7571d0e39bfc7737
   manager: conda
   name: kernel-headers_linux-64
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/kernel-headers_linux-64-3.10.0-h4a8ded7_13.tar.bz2
+  url: https://conda.anaconda.org/conda-forge/noarch/kernel-headers_linux-64-3.10.0-h4a8ded7_14.conda
   version: 3.10.0
 - category: main
   dependencies:
@@ -239,15 +239,15 @@ package:
 - category: main
   dependencies:
     _sysroot_linux-64_curr_repodata_hack: 3.*
-    kernel-headers_linux-64: 3.10.0 h4a8ded7_13
+    kernel-headers_linux-64: 3.10.0 h4a8ded7_14
   hash:
-    md5: 57e5a5191ffe999b9f4dfdbcd0ddcba4
-    sha256: f09f2fea4b571dcd225f1e35bd3c851e809cd4c2f5f151438133969ab28478e5
+    md5: d5f7a1cca06f56e6ac2b525f199f9b9e
+    sha256: af0f9ed466f97e3910c1d867ab44c974e01383cb408baa38606265964c7f0857
   manager: conda
   name: sysroot_linux-64
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/sysroot_linux-64-2.17-h4a8ded7_13.tar.bz2
+  url: https://conda.anaconda.org/conda-forge/noarch/sysroot_linux-64-2.17-h4a8ded7_14.conda
   version: '2.17'
 - category: main
   dependencies:
@@ -279,14 +279,14 @@ package:
   dependencies:
     libgcc-ng: '>=12'
   hash:
-    md5: 75dae9a4201732aa78a530b826ee5fe0
-    sha256: 51147922bad9d3176e780eb26f748f380cd3184896a9f9125d8ac64fe330158b
+    md5: 0bb492cca54017ea314b809b1ee3a176
+    sha256: 0e2b75b9834a6e520b13db516f7cf5c9cea8f0bbc9157c978444173dacb98fec
   manager: conda
   name: alsa-lib
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/alsa-lib-1.2.10-hd590300_0.conda
-  version: 1.2.10
+  url: https://conda.anaconda.org/conda-forge/linux-64/alsa-lib-1.2.11-hd590300_1.conda
+  version: 1.2.11
 - category: main
   dependencies:
     binutils_impl_linux-64: '>=2.40,<2.41.0a0'
@@ -315,14 +315,14 @@ package:
   dependencies:
     libgcc-ng: '>=12'
   hash:
-    md5: a86d90025198fd411845fc245ebc06c8
-    sha256: 3771589a91303710a59d1d40bbcdca43743969fe993ea576538ba375ac8ab0fa
+    md5: f6afff0e9ee08d2f1b897881a4f38cdb
+    sha256: 2a5866b19d28cb963fab291a62ff1c884291b9d6f59de14643e52f103e255749
   manager: conda
   name: c-ares
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/c-ares-1.26.0-hd590300_0.conda
-  version: 1.26.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/c-ares-1.27.0-hd590300_0.conda
+  version: 1.27.0
 - category: main
   dependencies:
     libgcc-ng: '>=12'
@@ -364,13 +364,13 @@ package:
     libgcc-ng: '>=12'
     libstdcxx-ng: '>=12'
   hash:
-    md5: 0e33ef437202db431aa5a928248cf2e8
-    sha256: 2a50495b6bbbacb03107ea0b752d8358d4a40b572d124a8cade068c147f344f5
+    md5: e358c7c5f6824c272b5034b3816438a7
+    sha256: cfc4202c23d6895d9c84042d08d5cda47d597772df870d4d2a10fc86dded5576
   manager: conda
   name: gmp
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/gmp-6.3.0-h59595ed_0.conda
+  url: https://conda.anaconda.org/conda-forge/linux-64/gmp-6.3.0-h59595ed_1.conda
   version: 6.3.0
 - category: main
   dependencies:
@@ -451,14 +451,14 @@ package:
   dependencies:
     libgcc-ng: '>=12'
   hash:
-    md5: 6305a3dd2752c76335295da4e581f2fd
-    sha256: 74c98a563777ae2ad71f1f74d458a8ab043cee4a513467c159ccf159d0e461f3
+    md5: 476fb82aba5358a08d52ec44e286ce33
+    sha256: 1c993845e8c25545565f50ab74511276a519e969acc406603e3f4539a14288b2
   manager: conda
   name: libexpat
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/libexpat-2.5.0-hcb278e6_1.conda
-  version: 2.5.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/libexpat-2.6.1-h59595ed_0.conda
+  version: 2.6.1
 - category: main
   dependencies:
     libgcc-ng: '>=12'
@@ -521,16 +521,16 @@ package:
   version: 2.0.1
 - category: main
   dependencies:
-    libgcc-ng: '>=11.4.0'
+    libgcc-ng: '>=13.2.0'
   hash:
-    md5: 47a9846c7679f8381b06fc5052ab4a4b
-    sha256: fc00e9a71c07446cf1744bd1d5cd3efa6dfd3a7db6c2c8a82853f19b8b1416f8
+    md5: 3f686300a92604d1bdff9a29dd4a6639
+    sha256: 97ecdab7e4e96400d712c2d6ba2b7c30a97278e9f4470ea0ff36bf4f1447b3b9
   manager: conda
   name: libsanitizer
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/libsanitizer-11.4.0-h4dcbe23_5.conda
-  version: 11.4.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/libsanitizer-13.2.0-h7e041cc_5.conda
+  version: 13.2.0
 - category: main
   dependencies:
     libgcc-ng: '>=12'
@@ -813,17 +813,17 @@ package:
   version: 1.6.1
 - category: main
   dependencies:
-    libexpat: 2.5.0 hcb278e6_1
+    libexpat: 2.6.1 h59595ed_0
     libgcc-ng: '>=12'
   hash:
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-    sha256: 36dfeb4375059b3bba75ce9b38c29c69fd257342a79e6cf20e9f25c1523f785f
+    md5: ee90e7ac57321f8782f8438bf647b75b
+    sha256: 8a5e6fe0b591b0dcd88967b86b94637b27d736364d8f4a6e771742fe30ca2078
   manager: conda
   name: expat
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@@ -2138,28 +2139,27 @@ package:
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     python_abi: 3.10.* *_cp310
     ruamel.yaml.clib: '>=0.1.2'
-    setuptools: ''
   hash:
-    md5: 14fd49048b91c96a8fbf1113a8cc4f49
-    sha256: b31d4eb844d1b667a9cddf63eafa2c303049ae559098f88e403c2ab5ebdd274e
+    md5: 50b7d9b39099cdbabf65bf27df73a793
+    sha256: 37581cbd99eb8855b6d268c85d189d723dd4fa1f9d115b8a633bed6dea4c370e
   manager: conda
   name: ruamel.yaml
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml-0.18.5-py310h2372a71_0.conda
-  version: 0.18.5
+  url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml-0.18.6-py310h2372a71_0.conda
+  version: 0.18.6
 - category: main
   dependencies:
-    typing_extensions: 4.9.0 pyha770c72_0
+    typing_extensions: 4.10.0 pyha770c72_0
   hash:
-    md5: c16524c1b7227dc80b36b4fa6f77cc86
-    sha256: d795c1eb1db4ea147f01ece74e5a504d7c2e8d5ee8c11ec987884967dd938f9c
+    md5: 091683b9150d2ebaa62fd7e2c86433da
+    sha256: 0698fe2c4e555fb44c27c60f7a21fa0eea7f5bf8186ad109543c5b056e27f96a
   manager: conda
   name: typing-extensions
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/typing-extensions-4.9.0-hd8ed1ab_0.conda
-  version: 4.9.0
+  url: https://conda.anaconda.org/conda-forge/noarch/typing-extensions-4.10.0-hd8ed1ab_0.conda
+  version: 4.10.0
 - category: main
   dependencies:
     brotli-python: '>=1.0.9'
@@ -2181,14 +2181,14 @@ package:
     platformdirs: <5,>=3.9.1
     python: '>=3.8'
   hash:
-    md5: c119653cba436d8183c27bf6d190e587
-    sha256: 50827c3721a9dbf973b568709d4381add2a6552fa562f26a385c5edc16a534af
+    md5: 8797a4e26be36880a603aba29c785352
+    sha256: 1ced4445cf72cd9dc344ad04bdaf703a08cc428c8c46e4bda928ad79786ee153
   manager: conda
   name: virtualenv
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.25.0-pyhd8ed1ab_0.conda
-  version: 20.25.0
+  url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.25.1-pyhd8ed1ab_0.conda
+  version: 20.25.1
 - category: main
   dependencies:
     libgcc-ng: '>=9.3.0'
@@ -2222,18 +2222,18 @@ package:
   dependencies:
     cffi: '>=1.12'
     libgcc-ng: '>=12'
-    openssl: '>=3.1.5,<4.0a0'
+    openssl: '>=3.2.1,<4.0a0'
     python: '>=3.10,<3.11.0a0'
     python_abi: 3.10.* *_cp310
   hash:
-    md5: a3618d82bb211dd03679a872cad533f2
-    sha256: 934249875c75779fd553aff568f25bdd625f5ba69cc8d60e78c847f35008e973
+    md5: 47e6ea7109182e9e48f8c5839f1bded7
+    sha256: eb514beb1c96969ebd299bb1979d6ccbf78087eb2a3772c364b94f778b8326ec
   manager: conda
   name: cryptography
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/cryptography-42.0.2-py310hb8475ec_0.conda
-  version: 42.0.2
+  url: https://conda.anaconda.org/conda-forge/linux-64/cryptography-42.0.5-py310h75e40e8_0.conda
+  version: 42.0.5
 - category: main
   dependencies:
     curl: ''
@@ -2242,18 +2242,18 @@ package:
     libgcc-ng: '>=12'
     libiconv: '>=1.17,<2.0a0'
     libzlib: '>=1.2.13,<1.3.0a0'
-    openssl: '>=3.2.0,<4.0a0'
-    pcre2: '>=10.42,<10.43.0a0'
+    openssl: '>=3.2.1,<4.0a0'
+    pcre2: '>=10.43,<10.44.0a0'
     perl: 5.*
   hash:
-    md5: 851970792301b407ba4c35e75e796791
-    sha256: 73a065e160d759e8fb0b169e615955a8fe0c148ed00c7f6ddf076f2e4adfd765
+    md5: 6817894081347566c0f097216bb36faa
+    sha256: 3ca58462b1c79a288587f8bdb82aa55829586e3f1635650988ab95d845b1b68e
   manager: conda
   name: git
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/git-2.43.0-pl5321h7bc287a_0.conda
-  version: 2.43.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/git-2.44.0-pl5321h709897a_0.conda
+  version: 2.44.0
 - category: main
   dependencies:
     cairo: '>=1.18.0,<2.0a0'
@@ -2274,16 +2274,16 @@ package:
   version: 8.3.0
 - category: main
   dependencies:
-    importlib-metadata: '>=7.0.1,<7.0.2.0a0'
+    importlib-metadata: '>=7.0.2,<7.0.3.0a0'
   hash:
-    md5: 4a2f43a20fa404b998859c6a470ba316
-    sha256: bc362df1d4f5a04c38dff29cd9c2d0ac584f9c4b45d3e4683ee090944a38fba4
+    md5: d11132727a247f2c1998779a2af743a1
+    sha256: b250e6a3e741b762bb2caf05119feb6245cb41b468542e5a9263cd01671098f7
   manager: conda
   name: importlib_metadata
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/importlib_metadata-7.0.1-hd8ed1ab_0.conda
-  version: 7.0.1
+  url: https://conda.anaconda.org/conda-forge/noarch/importlib_metadata-7.0.2-hd8ed1ab_0.conda
+  version: 7.0.2
 - category: main
   dependencies:
     libgcc-ng: '>=12'
@@ -2291,14 +2291,14 @@ package:
     python_abi: 3.10.* *_cp310
     typing-extensions: '>=4.6.0,!=4.7.0'
   hash:
-    md5: 1a6153b4a9a54c7250c163bcc0c1ac66
-    sha256: 1e491ddbfd53a67f0734fb3f4ccd8782c24935549c281cf5a9bcf9c5ce8b9ec4
+    md5: 3f7aa5bfda188d57c4741de6fcc15330
+    sha256: 0048a136343af983b6f6ee9fc6a65259d231eb3e90c57b2f9adaef725b64b17e
   manager: conda
   name: pydantic-core
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/pydantic-core-2.16.2-py310hcb5633a_0.conda
-  version: 2.16.2
+  url: https://conda.anaconda.org/conda-forge/linux-64/pydantic-core-2.16.3-py310hcb5633a_0.conda
+  version: 2.16.3
 - category: main
   dependencies:
     certifi: '>=2017.4.17'
@@ -2365,7 +2365,7 @@ package:
   version: 1.4.4
 - category: main
   dependencies:
-    alsa-lib: '>=1.2.10,<1.2.11.0a0'
+    alsa-lib: '>=1.2.10,<1.3.0.0a0'
     fontconfig: '>=2.14.2,<3.0a0'
     fonts-conda-ecosystem: ''
     freetype: '>=2.12.1,<3.0a0'
@@ -2396,18 +2396,18 @@ package:
 - category: main
   dependencies:
     annotated-types: '>=0.4.0'
-    pydantic-core: 2.16.2
+    pydantic-core: 2.16.3
     python: '>=3.7'
     typing-extensions: '>=4.6.1'
   hash:
-    md5: 3b1698c91820d852d802fc21471f52d8
-    sha256: 27083637287bb08a93e28616b5030f5eab31deb83d16fc132901ada987a62cfa
+    md5: 4f4e78b41c489b89d98719fcbde09361
+    sha256: 7367461b8f9e309f20f129605daa78635a1daa2538fe0b40d7f7238f8d430a29
   manager: conda
   name: pydantic
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/pydantic-2.6.1-pyhd8ed1ab_0.conda
-  version: 2.6.1
+  url: https://conda.anaconda.org/conda-forge/noarch/pydantic-2.6.3-pyhd8ed1ab_0.conda
+  version: 2.6.3
 - category: main
   dependencies:
     cryptography: ''
@@ -2447,14 +2447,14 @@ package:
     python_abi: 3.10.* *_cp310
     secretstorage: '>=3.2'
   hash:
-    md5: e710fd8e57356a64cace034413da9cb3
-    sha256: 886a764e4bc2cfaabf2ea0a98461fbd526affd99c984a2789770eca43dd17c9b
+    md5: 441009e6f4fa93552a32d2ed40d332b4
+    sha256: 8187362ec306c92e3d8ebb51677fffb2e44cd0a6e013ed1c4ef439f1d2e5e06b
   manager: conda
   name: keyring
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/keyring-24.3.0-py310hff52083_0.conda
-  version: 24.3.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/keyring-24.3.1-py310hff52083_0.conda
+  version: 24.3.1
 - category: main
   dependencies:
     __unix: ''
diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
index 44c1fe26..b31157e7 100644
--- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
+++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
@@ -9,7 +9,7 @@
 # To update a single package to the latest version compatible with the version constraints in the source:
 #     conda-lock lock  --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE
 # To re-solve the entire environment, e.g. after changing a version constraint in the source file:
-#     conda-lock -f /scratch/hansung/chipyard-gpu/conda-reqs/chipyard-base.yaml -f /scratch/hansung/chipyard-gpu/conda-reqs/chipyard-extended.yaml -f /scratch/hansung/chipyard-gpu/conda-reqs/docs.yaml -f /scratch/hansung/chipyard-gpu/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml
+#     conda-lock -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/chipyard-base.yaml -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/chipyard-extended.yaml -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/docs.yaml -f /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml
 metadata:
   channels:
   - url: ucb-bar
@@ -21,14 +21,14 @@ metadata:
   - url: nodefaults
     used_env_vars: []
   content_hash:
-    linux-64: a9cb69083a720c627608b7ed4f83a082677a26cc384fdbd207c5678111068c04
+    linux-64: 967532bafcd8d3c04dae411cd7253c49932c78f878e3fdd034b7d869cd3812a4
   platforms:
   - linux-64
   sources:
-  - /scratch/hansung/chipyard-gpu/conda-reqs/chipyard-base.yaml
-  - /scratch/hansung/chipyard-gpu/conda-reqs/chipyard-extended.yaml
-  - /scratch/hansung/chipyard-gpu/conda-reqs/docs.yaml
-  - /scratch/hansung/chipyard-gpu/conda-reqs/riscv-tools.yaml
+  - /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/chipyard-base.yaml
+  - /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/chipyard-extended.yaml
+  - /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/docs.yaml
+  - /scratch/vighneshiyer/chipyard-bump-gcc/conda-reqs/riscv-tools.yaml
 package:
 - category: main
   dependencies: {}
@@ -44,13 +44,13 @@ package:
 - category: main
   dependencies: {}
   hash:
-    md5: f6ce7955b53ae1ca83144adb3be9c600
-    sha256: 546e4eb1cbd822a66b363ec3fbdcc4fcc53853bcab57674cb46b8f3209b856f2
+    md5: 38d211c448a67f12fe693fe25df4da23
+    sha256: 0dbeaddc3d5134b5336c52ac05642533b8d1ba2e1316aa92981f4cf5b5388de0
   manager: conda
   name: _sysroot_linux-64_curr_repodata_hack
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h69a702a_13.conda
+  url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h69a702a_14.conda
   version: '3'
 - category: main
   dependencies: {}
@@ -77,14 +77,14 @@ package:
 - category: main
   dependencies: {}
   hash:
-    md5: fd2989188c0421b101b12c4ee91a8967
-    sha256: f0cb3d37b2642bf982d497d63f351dcdcd03cea1b0b175d4d3c9d13b3c022d80
+    md5: a5788fbb2081d5c3da68e94dda3199d9
+    sha256: 2536cf133f4f8afa0b66800168a8b25308096c355aa38ece865a268ee5a06104
   manager: conda
   name: conda-standalone
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/conda-standalone-23.11.0-ha770c72_1.conda
-  version: 23.11.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/conda-standalone-24.1.2-ha770c72_0.conda
+  version: 24.1.2
 - category: main
   dependencies: {}
   hash:
@@ -143,25 +143,25 @@ package:
 - category: main
   dependencies: {}
   hash:
-    md5: fb94f6b17ef1a75faac2e06937dc4223
-    sha256: 86d1e11bf0b8dbc74fec07f3c71bb1b20f83e32b5b9f8625b3dc653ce00e40bd
+    md5: 3bc29a967fee57e193ce51f51c598bca
+    sha256: 858029ad4d66869c533bb5a22e95e7c044ca66c61d6f403f10d9ae074a0e360e
   manager: conda
   name: libgcc-devel_linux-64
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/libgcc-devel_linux-64-11.4.0-h922705a_105.conda
-  version: 11.4.0
+  url: https://conda.anaconda.org/conda-forge/noarch/libgcc-devel_linux-64-13.2.0-ha9c7c90_105.conda
+  version: 13.2.0
 - category: main
   dependencies: {}
   hash:
-    md5: a884fe2f11c6167f3dc62d4b1db20ced
-    sha256: 20c4f2b96b8fb57a3cad0bb8f1ce407ee7bc935cb0ce68b430b10b77616c0b16
+    md5: 66383205c2e1bdf013df52fa9e3e6763
+    sha256: 67e999ee56481844ca4ce2e61132c5c16f3f00a05daa1d0ea4b2c684eea5de5a
   manager: conda
   name: libstdcxx-devel_linux-64
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/libstdcxx-devel_linux-64-11.4.0-h922705a_105.conda
-  version: 11.4.0
+  url: https://conda.anaconda.org/conda-forge/noarch/libstdcxx-devel_linux-64-13.2.0-ha9c7c90_105.conda
+  version: 13.2.0
 - category: main
   dependencies: {}
   hash:
@@ -176,14 +176,14 @@ package:
 - category: main
   dependencies: {}
   hash:
-    md5: ca8ce27415e2e304ec35b3de2af12364
-    sha256: b6f56d6c0a95dbd27bdcd5c666781c58c037850cebbaf62536a4fdf2bdcf2a2e
+    md5: 3f9dab167b1bac3a6636f3f4311eb17e
+    sha256: 37736ab56036733eaaff5f8f77a42c98caf75c82bc6b5dae59a727d24eabdd83
   manager: conda
   name: open_pdks.sky130a
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.460_0_gfdb1863-20231104_052339.tar.bz2
-  version: 1.0.460_0_gfdb1863
+  url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.471_0_g97d0844-20240223_100318.tar.bz2
+  version: 1.0.471_0_g97d0844
 - category: main
   dependencies: {}
   hash:
@@ -225,13 +225,13 @@ package:
   dependencies:
     _sysroot_linux-64_curr_repodata_hack: 3.*
   hash:
-    md5: 523bc836a954faf0cca94831971bb85a
-    sha256: 67a3caa56e2a59f407f3d290437b865aaf996873006e2fcfca6295d0f0be8db9
+    md5: f6c14886b1695a2462d296176e831080
+    sha256: 604b9345a7a1474b7eb33260e382446754d16eed754b853d7571d0e39bfc7737
   manager: conda
   name: kernel-headers_linux-64
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/kernel-headers_linux-64-3.10.0-h4a8ded7_13.tar.bz2
+  url: https://conda.anaconda.org/conda-forge/noarch/kernel-headers_linux-64-3.10.0-h4a8ded7_14.conda
   version: 3.10.0
 - category: main
   dependencies:
@@ -245,18 +245,6 @@ package:
   platform: linux-64
   url: https://conda.anaconda.org/conda-forge/linux-64/libgomp-13.2.0-h807b86a_5.conda
   version: 13.2.0
-- category: main
-  dependencies:
-    __unix: ''
-  hash:
-    md5: 46ab571e9b711ed713cd515395d187dd
-    sha256: 4ae02c3fadece8b4c0b0a214f21b4fd8e47ec81a332c503fdd21a659a472f108
-  manager: conda
-  name: rust-std-x86_64-unknown-linux-gnu
-  optional: false
-  platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/rust-std-x86_64-unknown-linux-gnu-1.75.0-h2c6d0dc_0.conda
-  version: 1.75.0
 - category: main
   dependencies:
     _libgcc_mutex: 0.1 conda_forge
@@ -285,15 +273,15 @@ package:
 - category: main
   dependencies:
     _sysroot_linux-64_curr_repodata_hack: 3.*
-    kernel-headers_linux-64: 3.10.0 h4a8ded7_13
+    kernel-headers_linux-64: 3.10.0 h4a8ded7_14
   hash:
-    md5: 57e5a5191ffe999b9f4dfdbcd0ddcba4
-    sha256: f09f2fea4b571dcd225f1e35bd3c851e809cd4c2f5f151438133969ab28478e5
+    md5: d5f7a1cca06f56e6ac2b525f199f9b9e
+    sha256: af0f9ed466f97e3910c1d867ab44c974e01383cb408baa38606265964c7f0857
   manager: conda
   name: sysroot_linux-64
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/sysroot_linux-64-2.17-h4a8ded7_13.tar.bz2
+  url: https://conda.anaconda.org/conda-forge/noarch/sysroot_linux-64-2.17-h4a8ded7_14.conda
   version: '2.17'
 - category: main
   dependencies:
@@ -325,14 +313,14 @@ package:
   dependencies:
     libgcc-ng: '>=12'
   hash:
-    md5: 75dae9a4201732aa78a530b826ee5fe0
-    sha256: 51147922bad9d3176e780eb26f748f380cd3184896a9f9125d8ac64fe330158b
+    md5: 0bb492cca54017ea314b809b1ee3a176
+    sha256: 0e2b75b9834a6e520b13db516f7cf5c9cea8f0bbc9157c978444173dacb98fec
   manager: conda
   name: alsa-lib
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/alsa-lib-1.2.10-hd590300_0.conda
-  version: 1.2.10
+  url: https://conda.anaconda.org/conda-forge/linux-64/alsa-lib-1.2.11-hd590300_1.conda
+  version: 1.2.11
 - category: main
   dependencies:
     libgcc-ng: '>=12'
@@ -385,14 +373,14 @@ package:
   dependencies:
     libgcc-ng: '>=12'
   hash:
-    md5: a86d90025198fd411845fc245ebc06c8
-    sha256: 3771589a91303710a59d1d40bbcdca43743969fe993ea576538ba375ac8ab0fa
+    md5: f6afff0e9ee08d2f1b897881a4f38cdb
+    sha256: 2a5866b19d28cb963fab291a62ff1c884291b9d6f59de14643e52f103e255749
   manager: conda
   name: c-ares
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/c-ares-1.26.0-hd590300_0.conda
-  version: 1.26.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/c-ares-1.27.0-hd590300_0.conda
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+  hash:
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+    sha256: a4283e21281679c54b8d4eb5b6992c22078fbbfced8250d629d1f76834778ae8
+  manager: conda
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+  optional: false
+  platform: linux-64
+  url: https://conda.anaconda.org/conda-forge/noarch/joserfc-0.9.0-pyhd8ed1ab_0.conda
+  version: 0.9.0
 - category: main
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     importlib_metadata: ''
@@ -5057,22 +5042,22 @@ package:
   version: 0.0.0.20190110_28_ga81397fc4
 - category: main
   dependencies:
-    cryptography: <44,>=0.6
+    cryptography: <45,>=0.6
     pyjwt: <3,>=1.0.0
     python: '>=3.6'
     requests: <3,>=2.0.0
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-    sha256: e0eb5606b4a164964d663d7a215ac9cd18db1ce1eca544aa61348e0a2bda94a9
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   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/msal-1.26.0-pyhd8ed1ab_0.conda
-  version: 1.26.0
+  url: https://conda.anaconda.org/conda-forge/noarch/msal-1.27.0-pyhd8ed1ab_0.conda
+  version: 1.27.0
 - category: main
   dependencies:
-    alsa-lib: '>=1.2.10,<1.2.11.0a0'
+    alsa-lib: '>=1.2.10,<1.3.0.0a0'
     fontconfig: '>=2.14.2,<3.0a0'
     fonts-conda-ecosystem: ''
     freetype: '>=2.12.1,<3.0a0'
@@ -5111,34 +5096,34 @@ package:
     python_abi: 3.10.* *_cp310
     pytz: '>=2020.1'
   hash:
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-    sha256: 540cb88ff475938dc8fd0b55a911db5daf509603eca385d2bad55013bf17e453
+    md5: cf5d315e3601a6a2931f63aa9a84dc40
+    sha256: 275bfe1485072153687b121b435864d97105928c674428348448d79ad85565aa
   manager: conda
   name: pandas
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/pandas-2.2.0-py310hcc13569_0.conda
-  version: 2.2.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/pandas-2.2.1-py310hcc13569_0.conda
+  version: 2.2.1
 - category: main
   dependencies:
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+    cairo: '>=1.18.0,<2.0a0'
     fontconfig: '>=2.14.2,<3.0a0'
     fonts-conda-ecosystem: ''
     freetype: '>=2.12.1,<3.0a0'
     fribidi: '>=1.0.10,<2.0a0'
-    harfbuzz: '>=8.1.1,<9.0a0'
+    harfbuzz: '>=8.3.0,<9.0a0'
     libgcc-ng: '>=12'
-    libglib: '>=2.76.4,<3.0a0'
-    libpng: '>=1.6.39,<1.7.0a0'
+    libglib: '>=2.78.4,<3.0a0'
+    libpng: '>=1.6.43,<1.7.0a0'
   hash:
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-    sha256: 6ecce306b7ac4acf1184eb5b045e57e613e19e99c27d57f33eb255f8a9120a93
+    md5: 5c0cc002bf4eaa56448b0729efd6e96c
+    sha256: 53d3442fb39eb9f0ac36646769469f2f825afaeda984719002460efd7c3d354f
   manager: conda
   name: pango
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/pango-1.50.14-ha41ecd1_2.conda
-  version: 1.50.14
+  url: https://conda.anaconda.org/conda-forge/linux-64/pango-1.52.1-ha41ecd1_0.conda
+  version: 1.52.1
 - category: main
   dependencies:
     bcrypt: '>=3.2'
@@ -5157,38 +5142,37 @@ package:
 - category: main
   dependencies:
     annotated-types: '>=0.4.0'
-    pydantic-core: 2.16.2
+    pydantic-core: 2.16.3
     python: '>=3.7'
     typing-extensions: '>=4.6.1'
   hash:
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-    sha256: 27083637287bb08a93e28616b5030f5eab31deb83d16fc132901ada987a62cfa
+    md5: 4f4e78b41c489b89d98719fcbde09361
+    sha256: 7367461b8f9e309f20f129605daa78635a1daa2538fe0b40d7f7238f8d430a29
   manager: conda
   name: pydantic
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/pydantic-2.6.1-pyhd8ed1ab_0.conda
-  version: 2.6.1
+  url: https://conda.anaconda.org/conda-forge/noarch/pydantic-2.6.3-pyhd8ed1ab_0.conda
+  version: 2.6.3
 - category: main
   dependencies:
-    cairo: '>=1.16.0,<2.0a0'
+    cairo: '>=1.18.0,<2.0a0'
     libffi: '>=3.4,<4.0a0'
-    libgcc-ng: '>=12'
     libgirepository: ''
-    libglib: '>=2.78.0,<3.0a0'
+    libglib: '>=2.78.4,<3.0a0'
     libiconv: ''
     pycairo: ''
     python: '>=3.10,<3.11.0a0'
     python_abi: 3.10.* *_cp310
   hash:
-    md5: d510c2f08eac618f03010d150e57dce6
-    sha256: d57070667fd3473ae37a6a7ad864a243ff0e6c8eef7969a92958f117d5495d75
+    md5: 6b137e8307102d90ef885382b57d672a
+    sha256: dff3e2ebae309d74a35eefeb4e3b5dbcd87c3bd7ebe2d1935376dea396c67866
   manager: conda
   name: pygobject
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/pygobject-3.46.0-py310h30b043a_1.conda
-  version: 3.46.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/pygobject-3.48.1-py310h30b043a_0.conda
+  version: 3.48.1
 - category: main
   dependencies:
     cryptography: '>=38.0.0,<41'
@@ -5227,14 +5211,14 @@ package:
     typing_extensions: ''
     urllib3: '>=1.25.10,<3.0'
   hash:
-    md5: b1b80aaa77d5e83183cd0c9e9025b1fa
-    sha256: 35a1cc20beca329bfa2b17feeb5ca66a2741bdccf39621dfe386f48206e73d67
+    md5: 3a3a9d37b275336a17386f80bfcca835
+    sha256: ffda7ac561d4b946dd8e2be9126a0418933340d345f3b96e3c9c4a1968bf3c3f
   manager: conda
   name: responses
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/responses-0.24.1-pyhd8ed1ab_0.conda
-  version: 0.24.1
+  url: https://conda.anaconda.org/conda-forge/noarch/responses-0.25.0-pyhd8ed1ab_0.conda
+  version: 0.25.0
 - category: main
   dependencies:
     botocore: '>=1.33.2,<2.0a.0'
@@ -5303,35 +5287,35 @@ package:
     prompt_toolkit: '>=3.0.24,<3.0.39'
     pyopenssl: <23.2
     python: '>=3.10,<3.11.0a0'
-    python-dateutil: '>=2.1,<3.0.0'
+    python-dateutil: '>=2.1,<=2.8.2'
     python_abi: 3.10.* *_cp310
     ruamel.yaml: '>=0.15.0,<=0.17.21'
     ruamel.yaml.clib: '>=0.2.0,<=0.2.7'
     urllib3: '>=1.25.4,<1.27'
   hash:
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-    sha256: b82590eecf39bc4621cf819ef604004ca8fba5610e5ac1b52fb0ca32cc3cc024
+    md5: d3b2de1d4c99c0b662b2b6f80568222b
+    sha256: e5422b4123263a09b8661fcfa7064426b68d7b7724650b156a06624bfe7b6334
   manager: conda
   name: awscli
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/awscli-2.15.17-py310hff52083_0.conda
-  version: 2.15.17
+  url: https://conda.anaconda.org/conda-forge/linux-64/awscli-2.15.28-py310hff52083_0.conda
+  version: 2.15.28
 - category: main
   dependencies:
-    botocore: '>=1.34.35,<1.35.0'
+    botocore: '>=1.34.61,<1.35.0'
     jmespath: '>=0.7.1,<2.0.0'
     python: '>=3.8'
     s3transfer: '>=0.10.0,<0.11.0'
   hash:
-    md5: 28bcab08664657284e9ea8673f1094ab
-    sha256: 55c967ae70c523077b1a6ed804acc340df2990860407e08af16ce1a75dcadd98
+    md5: 0e2e76e883b22b5688f2538f49f415c4
+    sha256: a5460fbc566bc50d421f8fd2cd3b4467785eb604d57e30e5271bd6d00e58edad
   manager: conda
   name: boto3
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.34.35-pyhd8ed1ab_0.conda
-  version: 1.34.35
+  url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.34.61-pyhd8ed1ab_1.conda
+  version: 1.34.61
 - category: main
   dependencies:
     cachecontrol: 0.14.0 pyhd8ed1ab_0
@@ -5382,19 +5366,25 @@ package:
   dependencies:
     atk-1.0: '>=2.38.0'
     cairo: '>=1.18.0,<2.0a0'
+    fontconfig: '>=2.14.2,<3.0a0'
+    fonts-conda-ecosystem: ''
+    freetype: '>=2.12.1,<3.0a0'
     gdk-pixbuf: '>=2.42.10,<3.0a0'
-    gettext: '>=0.21.1,<1.0a0'
+    harfbuzz: '>=8.3.0,<9.0a0'
     libgcc-ng: '>=12'
-    libglib: '>=2.78.3,<3.0a0'
+    libglib: '>=2.78.4,<3.0a0'
     pango: '>=1.50.14,<2.0a0'
+    xorg-libx11: '>=1.8.7,<2.0a0'
+    xorg-libxext: '>=1.3.4,<2.0a0'
+    xorg-libxrender: '>=0.9.11,<0.10.0a0'
   hash:
-    md5: 0abfa7f9241a0f4fd732bc15773cfb0c
-    sha256: e659f5eca2a5f21d5fe859d8d1dae132a284800eb017b8b4e2286b252a230527
+    md5: 410f86e58e880dcc7b0e910a8e89c05c
+    sha256: b946ba60d177d72157cad8af51723f1d081a4794741d35debe53f8b2c807f3af
   manager: conda
   name: gtk2
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/gtk2-2.24.33-h7f000aa_3.conda
+  url: https://conda.anaconda.org/conda-forge/linux-64/gtk2-2.24.33-h280cfa0_4.conda
   version: 2.24.33
 - category: main
   dependencies:
@@ -5420,14 +5410,14 @@ package:
     python_abi: 3.10.* *_cp310
     secretstorage: '>=3.2'
   hash:
-    md5: e710fd8e57356a64cace034413da9cb3
-    sha256: 886a764e4bc2cfaabf2ea0a98461fbd526affd99c984a2789770eca43dd17c9b
+    md5: 441009e6f4fa93552a32d2ed40d332b4
+    sha256: 8187362ec306c92e3d8ebb51677fffb2e44cd0a6e013ed1c4ef439f1d2e5e06b
   manager: conda
   name: keyring
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/keyring-24.3.0-py310hff52083_0.conda
-  version: 24.3.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/keyring-24.3.1-py310hff52083_0.conda
+  version: 24.3.1
 - category: main
   dependencies:
     cairo: '>=1.18.0,<2.0a0'
@@ -5465,14 +5455,14 @@ package:
     python_abi: 3.10.* *_cp310
     tk: '>=8.6.13,<8.7.0a0'
   hash:
-    md5: 3cbbc7d0b54df02c9a006d3de14911d9
-    sha256: 078f5f1ece533a03710dd6d644555f1f2f4cbe18f1412d695ffb304e3d8c9381
+    md5: 4a7296c0273eb01dfbed728dd6a6725a
+    sha256: f3179a086a10a0d7561b5935cfa5986ed9d1fd15b86f5a68de813455cd58f98f
   manager: conda
   name: matplotlib-base
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/matplotlib-base-3.8.2-py310h62c0568_0.conda
-  version: 3.8.2
+  url: https://conda.anaconda.org/conda-forge/linux-64/matplotlib-base-3.8.3-py310h62c0568_0.conda
+  version: 3.8.3
 - category: main
   dependencies:
     libsecret: ''
@@ -5515,14 +5505,14 @@ package:
     pyyaml: '>=5.1'
     virtualenv: '>=20.10.0'
   hash:
-    md5: 473a7cfca197da0a10cff3f6dded7d4b
-    sha256: 7d1f4b4a2eb4946b5808769642c5f643788c3a9e090f1c02a6c63f8794fb3d54
+    md5: 61534ee57ffdf26d7b1b514d33daccc4
+    sha256: 8eb9f5965c37d2bbee9302e16cc7c5517ee06491986356112be13431a043681e
   manager: conda
   name: pre-commit
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.6.0-pyha770c72_0.conda
-  version: 3.6.0
+  url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.6.2-pyha770c72_0.conda
+  version: 3.6.2
 - category: main
   dependencies:
     __unix: ''
@@ -5544,14 +5534,14 @@ package:
     python: '>=3.7,<4.0'
     typing-extensions: '>=4.4'
   hash:
-    md5: 7e09df6905a73a73cb3a0681ac824bb1
-    sha256: 1cb6e0d220fd183e6e4701c6867c4dc53daef40e1acaedb5378fee97e7ac0e97
+    md5: 250e721935d1b8feb2a17f24120c5e06
+    sha256: f1205b9438e8947fc0a3b70eabe07e6ef25c2bc228edb2ca3a26010c5f0a2e71
   manager: conda
   name: aws-sam-translator
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/aws-sam-translator-1.84.0-pyhd8ed1ab_0.conda
-  version: 1.84.0
+  url: https://conda.anaconda.org/conda-forge/noarch/aws-sam-translator-1.86.0-pyhd8ed1ab_0.conda
+  version: 1.86.0
 - category: main
   dependencies:
     azure-core: <2.0.0,>=1.23.0
@@ -5574,14 +5564,14 @@ package:
     python: ''
     typing_extensions: ''
   hash:
-    md5: d3c13aa8a3841ba9e53527b07de04933
-    sha256: af230542beef11d7d5b5ee0e9a144272ab99c28477b3fbd6fc0e2f626fbc8849
+    md5: 53366303b332b3bd2570a2df27f0d78b
+    sha256: 4082c623a4913c8737302397419a382585ff2df14a7a8153e3696d7c9cee9e2b
   manager: conda
   name: boto3-stubs
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.34.35-pyhd8ed1ab_0.conda
-  version: 1.34.35
+  url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.34.61-pyhd8ed1ab_0.conda
+  version: 1.34.61
 - category: main
   dependencies:
     archspec: ''
@@ -5687,14 +5677,14 @@ package:
     python: '>=3.6'
     typing-extensions: ''
   hash:
-    md5: 41b56eb093c6e10e3fd211656ad4e74e
-    sha256: 758fd7af61990c9890c2895a71b9e2644d41296a8461bc4a5aa838486b664eaa
+    md5: c9f10150ad5f625b48294a07a1d54d40
+    sha256: 29b7a44c9a2bbe8ca088e8e96f59679aed392f35e135a579bd6c357208ef572d
   manager: conda
   name: mypy_boto3_ec2
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.34.30-pyhd8ed1ab_0.conda
-  version: 1.34.30
+  url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.34.61-pyhd8ed1ab_0.conda
+  version: 1.34.61
 - category: main
   dependencies:
     importlib_resources: '>=5.8,<7.0'
@@ -5728,7 +5718,7 @@ package:
   version: 0.4.2
 - category: main
   dependencies:
-    aws-sam-translator: '>=1.83.0'
+    aws-sam-translator: '>=1.85.0'
     jschema-to-python: '>=1.2.3,<1.3.dev0'
     jsonpatch: ''
     jsonschema: '>=3.0,<5'
@@ -5740,14 +5730,14 @@ package:
     sarif-om: '>=1.0.4,<1.1.dev0'
     sympy: '>=1.0.0'
   hash:
-    md5: 2b97c7ed3caa28a40105b787c2408a15
-    sha256: ec6912b46231c9f89bba709bc5bb32e5d9c3957a1821ec418c16415b4245360d
+    md5: d2b123d03e90c526da05a58d32c1ccc9
+    sha256: 18b972f8ed1ede9a6c8aade643180f4fceb45c2d4b24632bf1deb795cf07b732
   manager: conda
   name: cfn-lint
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.85.0-pyhd8ed1ab_0.conda
-  version: 0.85.0
+  url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.86.0-pyhd8ed1ab_0.conda
+  version: 0.86.0
 - category: main
   dependencies:
     colorama: ''
@@ -5773,14 +5763,14 @@ package:
     python: '>=3.8'
     ruamel.yaml: '>=0.11.14,<0.19'
   hash:
-    md5: d8cb2dfbc95cd06af84d11bf16572270
-    sha256: 78a2b1abf48bdb34a9902caa7bff273ed001758f0845ef0508b347d85c21ca2b
+    md5: a348959b6d5222c8b85a06e2a0c23cb8
+    sha256: 79e4ff87514ed6fb4b2c28edc73573b82837f3d032c6a1a65f4aaeec00f318d8
   manager: conda
   name: constructor
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/constructor-3.6.0-pyh55f8243_0.conda
-  version: 3.6.0
+  url: https://conda.anaconda.org/conda-forge/noarch/constructor-3.7.0-pyh55f8243_0.conda
+  version: 3.7.0
 - category: main
   dependencies:
     graphviz: '>=2.46.1'
@@ -5808,6 +5798,7 @@ package:
     idna: '>=2.5,<4'
     importlib_metadata: ''
     jinja2: '>=2.10.1'
+    joserfc: ''
     jsondiff: '>=1.1.2'
     openapi-spec-validator: '>=0.2.8'
     pyparsing: '>=3.0.7'
@@ -5823,14 +5814,14 @@ package:
     werkzeug: '>=0.5,!=2.2.0,!=2.2.1'
     xmltodict: ''
   hash:
-    md5: 0bab0cb52bb79f684915a650c5452b33
-    sha256: bb03fa39768749a64bcd4204546e3c9e348c7702bfa979ddfc73575a1b6a9ff4
+    md5: 31d81c30d7244228121e31a40c7dc612
+    sha256: 89edf678481fc620ce5bdb49b8d0f14cf43d3386ec7bd39a445b249762130241
   manager: conda
   name: moto
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/moto-5.0.1-pyhd8ed1ab_0.conda
-  version: 5.0.1
+  url: https://conda.anaconda.org/conda-forge/noarch/moto-5.0.3-pyhd8ed1ab_0.conda
+  version: 5.0.3
 - category: main
   dependencies:
     colorama: ''
diff --git a/conda-reqs/riscv-tools.yaml b/conda-reqs/riscv-tools.yaml
index 0249f153..b1e52555 100644
--- a/conda-reqs/riscv-tools.yaml
+++ b/conda-reqs/riscv-tools.yaml
@@ -15,4 +15,4 @@ dependencies:
     # https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications
     #   documentation on package_spec syntax for constraining versions
 
-    - riscv-tools==1.0.3 # from ucb-bar channel - https://github.com/ucb-bar/riscv-tools-feedstock
+    - riscv-tools==1.0.6 # from ucb-bar channel - https://github.com/ucb-bar/riscv-tools-feedstock
diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst
index 948b7e2e..5ee4702b 100644
--- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst
+++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst
@@ -15,8 +15,8 @@ Running on AWS EC2 with FireSim
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 If you plan on using Chipyard alongside FireSim on AWS EC2 instances, you should refer to the :fsim_doc:`FireSim documentation <>`.
-Specifically, you should follow the :fsim_doc:`Initial Setup/Installation <Initial-Setup/index.html>`
-section of the docs up until :fsim_doc:`Setting up the FireSim Repo <Initial-Setup/Setting-up-your-Manager-Instance.html#setting-up-the-firesim-repo>`.
+Specifically, you should follow the :fsim_doc:`Initial Setup/Installation <Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Initial-Setup/index.html>`
+section of the docs up until :fsim_doc:`Setting up the FireSim Repo <Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Initial-Setup/Setting-up-your-Manager-Instance.html#setting-up-the-firesim-repo>`.
 At that point, instead of cloning FireSim you can clone Chipyard by following :ref:`Chipyard-Basics/Initial-Repo-Setup:Setting up the Chipyard Repo`.
 
 Default Requirements Installation
@@ -90,7 +90,9 @@ Run the following script based off which compiler you would like to use.
 
     ``-s 9`` skips pre-compiling FireMarshal default buildroot Linux sources
 
-    ``-s 10`` skips running repository clean-up
+    ``-s 10`` skips installing CIRCT
+
+    ``-s 11`` skips running repository clean-up
 
 .. code-block:: shell
 
diff --git a/docs/Simulation/FPGA-Accelerated-Simulation.rst b/docs/Simulation/FPGA-Accelerated-Simulation.rst
index 0e126252..1aa4ad74 100644
--- a/docs/Simulation/FPGA-Accelerated-Simulation.rst
+++ b/docs/Simulation/FPGA-Accelerated-Simulation.rst
@@ -26,12 +26,14 @@ Finally, source the following environment at the root of the FireSim directory:
 
     cd sims/firesim
     # (Recommended) The default manager environment (includes env.sh)
-    source sourceme-manager.sh
+    source sourceme-manager.sh`
+    # Completing setup using the manager
+    firesim managerinit --platform f1
 
 .. Note:: Every time you want to use FireSim with a fresh shell, you must source ``sourceme-manager.sh``
 
 At this point you're ready to use FireSim with Chipyard. If you're not already
-familiar with FireSim, please return to the :fsim_doc:`FireSim Docs <Initial-Setup/Setting-up-your-Manager-Instance.html#completing-setup-using-the-manager>`,
+familiar with FireSim, please return to the :fsim_doc:`FireSim Docs <Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Initial-Setup/Setting-up-your-Manager-Instance.html#completing-setup-using-the-manager>`,
 and proceed with the rest of the tutorial.
 
 Running your Design in FireSim
@@ -47,7 +49,7 @@ A FireSim simulation requires 3 additional config fragments:
 
 
 The simplest method to add this config fragments to your custom Chipyard config is through FireSim's build recipe scheme.
-After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/deploy/config_build_recipes.ini``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to your custom configuration as if they were listed in a custom Chisel config class definition. For example, if you would like to convert the Chipyard ``LargeBoomConfig`` to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig``. Note that the FireSim config fragments are part of the ``firesim.firesim`` scala package and therefore there do not need to be prefixed with the full package name as opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name.
+After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/config_build_recipes.yaml``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to your custom configuration as if they were listed in a custom Chisel config class definition. For example, if you would like to convert the Chipyard ``LargeBoomV3Config`` to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomV3Config``. Note that the FireSim config fragments are part of the ``firesim.firesim`` scala package and therefore there do not need to be prefixed with the full package name as opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name.
 
 An alternative method to prepending the FireSim config fragments in the FireSim build recipe is to create a new "permanent" FireChip custom configuration, which includes the FireSim config fragments.
 We are using the same target (top) RTL, and only need to specify a new set of connection behaviors for the IOs of that module. Simply create a matching config within ``generators/firechip/src/main/scala/TargetConfigs`` that inherits your config defined in ``chipyard``.
@@ -59,3 +61,5 @@ We are using the same target (top) RTL, and only need to specify a new set of co
     :end-before: DOC include end: firesimconfig
 
 While this option seems to require the maintenance of additional configuration code, it has the benefit of allowing for the inclusion of more complex config fragments which also accept custom arguments (for example, ``WithDefaultMemModel`` can take an optional argument``)
+
+For more information on how to build your own hardware design on FireSim, please refer to :fsim_doc:`FireSim Docs <Getting-Started-Guides/AWS-EC2-F1-Getting-Started/Building-a-FireSim-AFI.html#building-your-own-hardware-designs-firesim-amazon-fpga-images>`.
diff --git a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst
index 0c138d66..7387fde2 100644
--- a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst
+++ b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst
@@ -282,7 +282,7 @@ SRAM macros by default, but this feature does not exist yet.
 
 VLSI Flow Control
 ^^^^^^^^^^^^^^^^^
-Firt, refer to the :ref:`VLSI/Hammer:VLSI Flow Control` documentation. The below examples use the ``redo-par`` Make target to re-run only place-and-route. ``redo-`` may be prepended to any of the VLSI flow actions to re-run only that action.
+First, refer to the :ref:`VLSI/Hammer:VLSI Flow Control` documentation. The below examples use the ``redo-par`` Make target to re-run only place-and-route. ``redo-`` may be prepended to any of the VLSI flow actions to re-run only that action.
 
 .. code-block:: shell
 
diff --git a/fpga/fpga-shells b/fpga/fpga-shells
index 93004b7b..6019bb35 160000
--- a/fpga/fpga-shells
+++ b/fpga/fpga-shells
@@ -1 +1 @@
-Subproject commit 93004b7bd02eb7cc32a25cc1bc40595b93add118
+Subproject commit 6019bb3508d12887b01765f3cad512c3282aeb70
diff --git a/fpga/src/main/resources/vcu118/sdboot/Makefile b/fpga/src/main/resources/vcu118/sdboot/Makefile
index e4636129..46078b69 100644
--- a/fpga/src/main/resources/vcu118/sdboot/Makefile
+++ b/fpga/src/main/resources/vcu118/sdboot/Makefile
@@ -5,12 +5,13 @@ BUILD_DIR := $(ROOT_DIR)/build
 CC=$(RISCV)/bin/riscv64-unknown-elf-gcc
 OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy
 OBJDUMP=$(RISCV)/bin/riscv64-unknown-elf-objdump
-CFLAGS=-march=rv64ima -mcmodel=medany -O2 -std=gnu11 -Wall -nostartfiles
+CFLAGS=-march=rv64ima_zicsr_zifencei -mcmodel=medany -O2 -std=gnu11 -Wall -nostartfiles
 CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0
 CFLAGS+= -I $(ROOT_DIR)/include -I.
 LFLAGS=-static -nostdlib -L $(ROOT_DIR)/linker -T sdboot.elf.lds
 
-PBUS_CLK ?= 1000000 # default to 1MHz but really should be overridden
+# default to 1MHz but really should be overridden
+PBUS_CLK ?= 1000000
 
 default: elf bin dump
 
diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala
index 39ddd204..fcc07758 100644
--- a/fpga/src/main/scala/arty/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty/HarnessBinders.scala
@@ -5,7 +5,7 @@ import chisel3._
 import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
 import freechips.rocketchip.jtag.{JTAGIO}
 
-import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp}
+import sifive.blocks.devices.uart.{UARTPortIO}
 import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
 import sifive.blocks.devices.pinctrl.{BasePin}
 
diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala
index bb4b8e22..9d945824 100644
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -5,7 +5,8 @@ import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy._
+import org.chipsalliance.diplomacy.lazymodule._
 import freechips.rocketchip.system._
 import freechips.rocketchip.tile._
 
@@ -58,5 +59,5 @@ class NoCoresArty100TConfig extends Config(
 class BringupArty100TConfig extends Config(
   new WithArty100TSerialTLToGPIO ++
   new WithArty100TTweaks(freqMHz = 50) ++
-  new testchipip.serdes.WithSerialTLPHYParams(testchipip.serdes.InternalSyncSerialParams(freqMHz=50)) ++
+  new testchipip.serdes.WithSerialTLPHYParams(testchipip.serdes.InternalSyncSerialPhyParams(freqMHz=50)) ++
   new chipyard.ChipBringupHostConfig)
diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala
index 11a99421..35b3c3b1 100644
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -5,10 +5,9 @@ import chisel3._
 import freechips.rocketchip.jtag.{JTAGIO}
 import freechips.rocketchip.subsystem.{PeripheryBusKey}
 import freechips.rocketchip.tilelink.{TLBundle}
-import freechips.rocketchip.util.{HeterogeneousBag}
 import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
-
-import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp, UARTParams}
+import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
+import sifive.blocks.devices.uart.{UARTPortIO, UARTParams}
 import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
 import sifive.blocks.devices.pinctrl.{BasePin}
 import sifive.fpgashells.shell._
@@ -61,10 +60,10 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
     harnessIO <> port.io
 
     harnessIO match {
-      case io: DecoupledSerialIO => {
+      case io: DecoupledPhitIO => {
         val clkIO = io match {
-          case io: InternalSyncSerialIO => IOPin(io.clock_out)
-          case io: ExternalSyncSerialIO => IOPin(io.clock_in)
+          case io: InternalSyncPhitIO => IOPin(io.clock_out)
+          case io: ExternalSyncPhitIO => IOPin(io.clock_in)
         }
         val packagePinsWithPackageIOs = Seq(
           ("G13", clkIO),
@@ -72,14 +71,14 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
           ("A11", IOPin(io.out.ready)),
           ("D12", IOPin(io.in.valid)),
           ("D13", IOPin(io.in.ready)),
-          ("B18", IOPin(io.out.bits, 0)),
-          ("A18", IOPin(io.out.bits, 1)),
-          ("K16", IOPin(io.out.bits, 2)),
-          ("E15", IOPin(io.out.bits, 3)),
-          ("E16", IOPin(io.in.bits, 0)),
-          ("D15", IOPin(io.in.bits, 1)),
-          ("C15", IOPin(io.in.bits, 2)),
-          ("J17", IOPin(io.in.bits, 3))
+          ("B18", IOPin(io.out.bits.phit, 0)),
+          ("A18", IOPin(io.out.bits.phit, 1)),
+          ("K16", IOPin(io.out.bits.phit, 2)),
+          ("E15", IOPin(io.out.bits.phit, 3)),
+          ("E16", IOPin(io.in.bits.phit, 0)),
+          ("D15", IOPin(io.in.bits.phit, 1)),
+          ("C15", IOPin(io.in.bits.phit, 2)),
+          ("J17", IOPin(io.in.bits.phit, 3))
         )
         packagePinsWithPackageIOs foreach { case (pin, io) => {
           artyTh.xdc.addPackagePin(io, pin)
@@ -88,10 +87,10 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
 
         // Don't add IOB to the clock, if its an input
         io match {
-          case io: InternalSyncSerialIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
+          case io: InternalSyncPhitIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
             artyTh.xdc.addIOB(io)
           }}
-          case io: ExternalSyncSerialIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
+          case io: ExternalSyncPhitIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
             artyTh.xdc.addIOB(io)
           }}
         }
diff --git a/fpga/src/main/scala/nexysvideo/Configs.scala b/fpga/src/main/scala/nexysvideo/Configs.scala
index ce8fbae8..2aa241c7 100644
--- a/fpga/src/main/scala/nexysvideo/Configs.scala
+++ b/fpga/src/main/scala/nexysvideo/Configs.scala
@@ -5,7 +5,7 @@ import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy.lazymodule._
 import freechips.rocketchip.system._
 import freechips.rocketchip.tile._
 
diff --git a/fpga/src/main/scala/nexysvideo/HarnessBinders.scala b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala
index 29deeadb..722971a1 100644
--- a/fpga/src/main/scala/nexysvideo/HarnessBinders.scala
+++ b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala
@@ -7,6 +7,7 @@ import freechips.rocketchip.subsystem.{PeripheryBusKey}
 import freechips.rocketchip.tilelink.{TLBundle}
 import freechips.rocketchip.util.{HeterogeneousBag}
 import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
+import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
 
 import sifive.blocks.devices.uart.{UARTParams}
 
diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala
index 4842434e..d9fc1322 100644
--- a/fpga/src/main/scala/vc707/Configs.scala
+++ b/fpga/src/main/scala/vc707/Configs.scala
@@ -72,7 +72,7 @@ class RocketVC707Config extends Config (
 class BoomVC707Config extends Config (
   new WithFPGAFrequency(50) ++
   new WithVC707Tweaks ++
-  new chipyard.MegaBoomConfig
+  new chipyard.MegaBoomV3Config
 )
 
 class WithFPGAFrequency(fMHz: Double) extends Config (
diff --git a/fpga/src/main/scala/vc707/HarnessBinders.scala b/fpga/src/main/scala/vc707/HarnessBinders.scala
index d08fba76..b872f08a 100644
--- a/fpga/src/main/scala/vc707/HarnessBinders.scala
+++ b/fpga/src/main/scala/vc707/HarnessBinders.scala
@@ -3,10 +3,10 @@ package chipyard.fpga.vc707
 import chisel3._
 import chisel3.experimental.{BaseModule}
 
-import freechips.rocketchip.util.{HeterogeneousBag}
+import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
 import freechips.rocketchip.tilelink.{TLBundle}
 
-import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
+import sifive.blocks.devices.uart.{UARTPortIO}
 import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
 import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{HasSystemXilinxVC707PCIeX1ModuleImp, XilinxVC707PCIeX1IO}
 
diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala
index ff46deee..d9caa81d 100644
--- a/fpga/src/main/scala/vcu118/Configs.scala
+++ b/fpga/src/main/scala/vcu118/Configs.scala
@@ -54,11 +54,11 @@ class WithVCU118Tweaks extends Config(
   new WithUART ++
   new WithSPISDCard ++
   new WithDDRMem ++
+  new WithJTAG ++
   // other configuration
   new WithDefaultPeripherals ++
   new chipyard.config.WithTLBackingMemory ++ // use TL backing memory
   new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
-  new chipyard.config.WithNoDebug ++ // remove debug module
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(1)
 )
@@ -72,7 +72,7 @@ class RocketVCU118Config extends Config(
 class BoomVCU118Config extends Config(
   new WithFPGAFrequency(50) ++
   new WithVCU118Tweaks ++
-  new chipyard.MegaBoomConfig
+  new chipyard.MegaBoomV3Config
 )
 
 class WithFPGAFrequency(fMHz: Double) extends Config(
diff --git a/fpga/src/main/scala/vcu118/HarnessBinders.scala b/fpga/src/main/scala/vcu118/HarnessBinders.scala
index c03f551f..6b977531 100644
--- a/fpga/src/main/scala/vcu118/HarnessBinders.scala
+++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala
@@ -3,10 +3,10 @@ package chipyard.fpga.vcu118
 import chisel3._
 import chisel3.experimental.{BaseModule}
 
-import freechips.rocketchip.util.{HeterogeneousBag}
+import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
 import freechips.rocketchip.tilelink.{TLBundle}
 
-import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
+import sifive.blocks.devices.uart.{UARTPortIO}
 import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
 
 import chipyard._
@@ -36,3 +36,17 @@ class WithDDRMem extends HarnessBinder({
     ddrClientBundle <> port.io
   }
 })
+
+class WithJTAG extends HarnessBinder({
+  case (th: VCU118FPGATestHarnessImp, port: JTAGPort, chipId: Int) => {
+    val jtag_io = th.vcu118Outer.jtagPlacedOverlay.overlayOutput.jtag.getWrappedValue
+    port.io.TCK := jtag_io.TCK
+    port.io.TMS := jtag_io.TMS
+    port.io.TDI := jtag_io.TDI
+    jtag_io.TDO.data := port.io.TDO
+    jtag_io.TDO.driven := true.B
+    // ignore srst_n
+    jtag_io.srst_n := DontCare
+
+  }
+})
diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala
index 78dee3e6..b707d144 100644
--- a/fpga/src/main/scala/vcu118/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/TestHarness.scala
@@ -85,6 +85,9 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
   )))))
   ddrNode := TLWidthWidget(dp(ExtTLMem).get.master.beatBytes) := ddrClient
 
+  /*** JTAG ***/
+  val jtagPlacedOverlay = dp(JTAGDebugOverlayKey).head.place(JTAGDebugDesignInput())
+
   // module implementation
   override lazy val module = new VCU118FPGATestHarnessImp(this)
 }
diff --git a/generators/boom b/generators/boom
index 9459af0c..506c11c9 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit 9459af0c1f6847f8411622dac770ac78fe10847c
+Subproject commit 506c11c99ca9f6015d14fdc02c45c1e22983d06f
diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala
index 0a34f599..7a216fa1 100644
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -19,9 +19,11 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO
   with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
   with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device
-  with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
+  with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the tl-serial interface
+  with testchipip.serdes.old.CanHavePeripheryTLSerial // Enables optionally adding the DEPRECATED tl-serial interface
   with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs
   with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C
+  with sifive.blocks.devices.timer.HasPeripheryTimer // Enables optionally adding the timer device
   with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM
   with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
   with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
@@ -43,12 +45,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   override lazy val module = new DigitalTopModule(this)
 }
 
-class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
-  with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
-  with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
-  with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
-  with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
-  with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
-  with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
+class DigitalTopModule(l: DigitalTop) extends ChipyardSystemModule(l)
   with freechips.rocketchip.util.DontTouch
 // DOC include end: DigitalTop
diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala
index 651a4000..c95f2516 100644
--- a/generators/chipyard/src/main/scala/Subsystem.scala
+++ b/generators/chipyard/src/main/scala/Subsystem.scala
@@ -20,9 +20,6 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.amba.axi4._
 
-import boom.common.{BoomTile}
-
-
 import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
 
 trait CanHaveHTIF { this: BaseSubsystem =>
@@ -92,7 +89,8 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
 {
   def coreMonitorBundles = totalTiles.values.map {
     case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle
-    case b: BoomTile => b.module.core.coreMonitorBundle
+    case b: boom.v3.common.BoomTile => b.module.core.coreMonitorBundle
+    case b: boom.v4.common.BoomTile => b.module.core.coreMonitorBundle
   }.toList
 
   // No-tile configs have to be handled specially.
@@ -132,6 +130,6 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
 }
 
 class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
-    with HasHierarchicalElementsRootContextModuleImp
-{
+    with HasHierarchicalElementsRootContextModuleImp {
+  override lazy val outer = _outer
 }
diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala
index b8a04eac..d67f99bd 100644
--- a/generators/chipyard/src/main/scala/System.scala
+++ b/generators/chipyard/src/main/scala/System.scala
@@ -38,7 +38,7 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
 /**
  * Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem
  */
-class ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer)
+class ChipyardSystemModule(_outer: ChipyardSystem) extends ChipyardSubsystemModuleImp(_outer)
   with HasRTCModuleImp
   with HasExtInterruptsModuleImp
   with DontTouch
@@ -60,6 +60,7 @@ trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
   private val portName = "tl_mem"
   private val device = new MemoryDevice
   private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1)
+  private val mbus = tlBusWrapperLocationMap.lift(MBUS).getOrElse(locateTLBusWrapper(SBUS))
 
   val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels, _) =>
     Seq.tabulate(nMemoryChannels) { channel =>
@@ -76,15 +77,15 @@ trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
          supportsPutFull    = TransferSizes(1, mbus.blockBytes),
          supportsPutPartial = TransferSizes(1, mbus.blockBytes))),
          beatBytes = memPortParams.beatBytes)
-   }
- }).toList.flatten)
+    }
+  }).toList.flatten)
 
- mbus.coupleTo(s"memory_controller_port_named_$portName") {
-   (memTLNode
-     :*= TLBuffer()
-     :*= TLSourceShrinker(1 << idBits)
-     :*= TLWidthWidget(mbus.beatBytes)
-     :*= _)
+  mbus.coupleTo(s"memory_controller_port_named_$portName") {
+    (memTLNode
+      :*= TLBuffer()
+      :*= TLSourceShrinker(1 << idBits)
+      :*= TLWidthWidget(mbus.beatBytes)
+      :*= _)
   }
 
   val mem_tl = InModuleBody { memTLNode.makeIOs() }
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
index 8a328daf..77a998e6 100644
--- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala
+++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -11,24 +11,32 @@ import org.chipsalliance.cde.config.{Config}
 // --------------
 
 class AbstractConfig extends Config(
+  // ================================================
+  //   Set up TestHarness
+  // ================================================
   // The HarnessBinders control generation of hardware in the TestHarness
-  new chipyard.harness.WithUARTAdapter ++                          // add UART adapter to display UART on stdout, if uart is present
-  new chipyard.harness.WithBlackBoxSimMem ++                       // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled
-  new chipyard.harness.WithSimTSIOverSerialTL ++                   // add external serial-adapter and RAM
-  new chipyard.harness.WithSimJTAGDebug ++                         // add SimJTAG if JTAG for debug exposed
-  new chipyard.harness.WithSimDMI ++                               // add SimJTAG if DMI exposed
-  new chipyard.harness.WithGPIOTiedOff ++                          // tie-off chiptop GPIOs, if GPIOs are present
-  new chipyard.harness.WithSimSPIFlashModel ++                     // add simulated SPI flash memory, if SPI is enabled
-  new chipyard.harness.WithSimAXIMMIO ++                           // add SimAXIMem for axi4 mmio port, if enabled
-  new chipyard.harness.WithTieOffInterrupts ++                     // tie-off interrupt ports, if present
-  new chipyard.harness.WithTieOffL2FBusAXI ++                      // tie-off external AXI4 master, if present
-  new chipyard.harness.WithCustomBootPinPlusArg ++                 // drive custom-boot pin with a plusarg, if custom-boot-pin is present
-  new chipyard.harness.WithDriveChipIdPin ++                       // drive chip id pin from harness binder, if chip id pin is present
-  new chipyard.harness.WithSimUARTToUARTTSI ++                     // connect a SimUART to the UART-TSI port
-  new chipyard.harness.WithClockFromHarness ++                     // all Clock I/O in ChipTop should be driven by harnessClockInstantiator
-  new chipyard.harness.WithResetFromHarness ++                     // reset controlled by harness
-  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz
+  new chipyard.harness.WithUARTAdapter ++                          /** add UART adapter to display UART on stdout, if uart is present */
+  new chipyard.harness.WithBlackBoxSimMem ++                       /** add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled */
+  new chipyard.harness.WithSimTSIOverSerialTL ++                   /** add external serial-adapter and RAM */
+  new chipyard.harness.WithSimJTAGDebug ++                         /** add SimJTAG if JTAG for debug exposed */
+  new chipyard.harness.WithSimDMI ++                               /** add SimJTAG if DMI exposed */
+  new chipyard.harness.WithGPIOPinsTiedOff ++                      /** tie-off chiptop GPIO-pins, if GPIO-punchthrough is used */
+  new chipyard.harness.WithGPIOTiedOff ++                          /** tie-off chiptop GPIOs, if GPIOs are present */
+  new chipyard.harness.WithSimSPIFlashModel ++                     /** add simulated SPI flash memory, if SPI is enabled */
+  new chipyard.harness.WithSimAXIMMIO ++                           /** add SimAXIMem for axi4 mmio port, if enabled */
+  new chipyard.harness.WithTieOffInterrupts ++                     /** tie-off interrupt ports, if present */
+  new chipyard.harness.WithTieOffL2FBusAXI ++                      /** tie-off external AXI4 master, if present */
+  new chipyard.harness.WithCustomBootPinPlusArg ++                 /** drive custom-boot pin with a plusarg, if custom-boot-pin is present */
+  new chipyard.harness.WithDriveChipIdPin ++                       /** drive chip id pin from harness binder, if chip id pin is present */
+  new chipyard.harness.WithSimUARTToUARTTSI ++                     /** connect a SimUART to the UART-TSI port */
+  new chipyard.harness.WithClockFromHarness ++                     /** all Clock I/O in ChipTop should be driven by harnessClockInstantiator */
+  new chipyard.harness.WithResetFromHarness ++                     /** reset controlled by harness */
+  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ /** generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz */
 
+
+  // ================================================
+  //   Set up I/O cells + punch I/Os in ChipTop
+  // ================================================
   // The IOBinders instantiate ChipTop IOs to match desired digital IOs
   // IOCells are generated for "Chip-like" IOs
   new chipyard.iobinders.WithSerialTLIOCells ++
@@ -53,42 +61,99 @@ class AbstractConfig extends Config(
   new chipyard.iobinders.WithUARTTSIPunchthrough ++
   new chipyard.iobinders.WithNMITiedOff ++
 
-  new chipyard.clocking.WithClockTapIOCells ++                      // Default generate a clock tapio
-  new chipyard.clocking.WithPassthroughClockGenerator ++            // Default punch out IOs to the Harness
-  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore",    // Default merge all the bus clocks
-    Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"), Seq("tile"))) ++
-  new chipyard.config.WithPeripheryBusFrequency(500.0) ++           // Default 500 MHz pbus
-  new chipyard.config.WithControlBusFrequency(500.0) ++             // Default 500 MHz cbus
-  new chipyard.config.WithMemoryBusFrequency(500.0) ++              // Default 500 MHz mbus
-  new chipyard.config.WithControlBusFrequency(500.0) ++             // Default 500 MHz cbus
-  new chipyard.config.WithSystemBusFrequency(500.0) ++              // Default 500 MHz sbus
-  new chipyard.config.WithFrontBusFrequency(500.0) ++               // Default 500 MHz fbus
-  new chipyard.config.WithOffchipBusFrequency(500.0) ++             // Default 500 MHz obus
 
-  new testchipip.boot.WithCustomBootPin ++                          // add a custom-boot-pin to support pin-driven boot address
-  new testchipip.boot.WithBootAddrReg ++                            // add a boot-addr-reg for configurable boot address
-  new testchipip.serdes.WithSerialTL(Seq(                           // add a serial-tilelink interface
+  // ================================================
+  //   Set up External Memory and IO Devices
+  // ================================================
+  // External memory section
+  new testchipip.serdes.WithSerialTL(Seq(                           /** add a serial-tilelink interface */
     testchipip.serdes.SerialTLParams(
-      client = Some(testchipip.serdes.SerialTLClientParams()),      // serial-tilelink interface will master the FBUS, and support 4 idBits
-      phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32) // serial-tilelink interface with 32 lanes
+      client = Some(testchipip.serdes.SerialTLClientParams(totalIdBits=4)), // serial-tilelink interface will master the FBUS, and support 4 idBits
+      phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=32, flitWidth=32) // serial-tilelink interface with 32 lanes
     )
   )) ++
-  new testchipip.soc.WithMbusScratchpad(base = 0x08000000,          // add 64 KiB on-chip scratchpad
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++         /** Default 1 AXI-4 memory channels */
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++                 /** no top-level MMIO master port (overrides default set in rocketchip) */
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++                /** no top-level MMIO slave port (overrides default set in rocketchip) */
+
+  // MMIO device section
+  new chipyard.config.WithUART ++                                  /** add a UART */
+
+
+  // ================================================
+  //   Set up Debug/Bringup/Testing Features
+  // ================================================
+  // JTAG
+  new freechips.rocketchip.subsystem.WithDebugSBA ++                /** enable the SBA (system-bus-access) feature of the debug module */
+  new chipyard.config.WithDebugModuleAbstractDataWords(8) ++        /** increase debug module data word capacity */
+  new freechips.rocketchip.subsystem.WithJtagDTM ++                 /** set the debug module to expose a JTAG port */
+
+  // Boot Select Pins
+  new testchipip.boot.WithCustomBootPin ++                          /** add a custom-boot-pin to support pin-driven boot address */
+  new testchipip.boot.WithBootAddrReg ++                            /** add a boot-addr-reg for configurable boot address */
+
+
+  // ================================================
+  //   Set up Interrupts
+  // ================================================
+  // CLINT and PLIC related settings goes here
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++    /** no external interrupts */
+
+
+  // ================================================
+  //   Set up Tiles
+  // ================================================
+  // tile-local settings goes here
+
+
+  // ================================================
+  //   Set up Memory system
+  // ================================================
+  // On-chip memory section
+  new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ /** custom device name for DTS (embedded in BootROM) */
+  new chipyard.config.WithBootROM ++                                     /** use default bootrom */
+  new testchipip.soc.WithMbusScratchpad(base = 0x08000000,               /** add 64 KiB on-chip scratchpad */
                                         size = 64 * 1024) ++
-  new chipyard.config.WithDebugModuleAbstractDataWords(8) ++        // increase debug module data capacity
-  new chipyard.config.WithBootROM ++                                // use default bootrom
-  new chipyard.config.WithUART ++                                   // add a UART
-  new chipyard.config.WithL2TLBs(1024) ++                           // use L2 TLBs
-  new chipyard.config.WithNoSubsystemClockIO ++                     // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
-  new chipyard.config.WithInheritBusFrequencyAssignments ++         // Unspecified clocks within a bus will receive the bus frequency if set
-  new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++      // Default 1 memory channels
-  new freechips.rocketchip.subsystem.WithClockGateModel ++          // add default EICG_wrapper clock gate model
-  new freechips.rocketchip.subsystem.WithJtagDTM ++                 // set the debug module to expose a JTAG port
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++              // no top-level MMIO master port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++             // no top-level MMIO slave port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++          // use Sifive L2 cache
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++    // no external interrupts
-  new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ // leave the bus clocks undriven by sbus
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++     // hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2
-  new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ // custom device name for DTS
-  new freechips.rocketchip.system.BaseConfig)                       // "base" rocketchip system
+
+  // Coherency settings
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++          /** use Sifive LLC cache as root of coherence */
+
+  // Bus/interconnect settings
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++     /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */
+  new chipyard.config.WithSV48IfPossible ++                         /** use sv48 if possible */
+
+
+  // ================================================
+  //   Set up power, reset and clocking
+  // ================================================
+
+  // ChipTop clock IO/PLL/Divider/Mux settings
+  new chipyard.clocking.WithClockTapIOCells ++                      /** Default generate a clock tapio */
+  new chipyard.clocking.WithPassthroughClockGenerator ++
+
+  // DigitalTop-internal clocking settings
+  new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++  /** leave the bus clocks undriven by sbus */
+  new freechips.rocketchip.subsystem.WithClockGateModel ++              /** add default EICG_wrapper clock gate model */
+  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore",        /** create a "uncore" clock group tieing all the bus clocks together */
+    Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"),
+    Seq("tile"))) ++
+
+  new chipyard.config.WithPeripheryBusFrequency(500.0) ++           /** Default 500 MHz pbus */
+  new chipyard.config.WithMemoryBusFrequency(500.0) ++              /** Default 500 MHz mbus */
+  new chipyard.config.WithControlBusFrequency(500.0) ++             /** Default 500 MHz cbus */
+  new chipyard.config.WithSystemBusFrequency(500.0) ++              /** Default 500 MHz sbus */
+  new chipyard.config.WithFrontBusFrequency(500.0) ++               /** Default 500 MHz fbus */
+  new chipyard.config.WithOffchipBusFrequency(500.0) ++             /** Default 500 MHz obus */
+  new chipyard.config.WithInheritBusFrequencyAssignments ++         /** Unspecified clocks within a bus will receive the bus frequency if set */
+  new chipyard.config.WithNoSubsystemClockIO ++                     /** drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks */
+
+  // reset
+
+  // power
+
+
+  // ==================================
+  //   Base Settings
+  // ==================================
+  new freechips.rocketchip.system.BaseConfig                        /** "base" rocketchip system */
+)
diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala
index 6b037ec9..dfd302c3 100644
--- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala
@@ -3,60 +3,116 @@ package chipyard
 import org.chipsalliance.cde.config.{Config}
 
 // ---------------------
-// BOOM Configs
+// BOOM V3 Configs
+// Performant, stable baseline
 // ---------------------
 
-class SmallBoomConfig extends Config(
-  new boom.common.WithNSmallBooms(1) ++                          // small boom config
+class SmallBoomV3Config extends Config(
+  new boom.v3.common.WithNSmallBooms(1) ++                          // small boom config
   new chipyard.config.AbstractConfig)
 
-class MediumBoomConfig extends Config(
-  new boom.common.WithNMediumBooms(1) ++                         // medium boom config
+class MediumBoomV3Config extends Config(
+  new boom.v3.common.WithNMediumBooms(1) ++                         // medium boom config
   new chipyard.config.AbstractConfig)
 
-class LargeBoomConfig extends Config(
-  new boom.common.WithNLargeBooms(1) ++                          // large boom config
+class LargeBoomV3Config extends Config(
+  new boom.v3.common.WithNLargeBooms(1) ++                          // large boom config
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
-class MegaBoomConfig extends Config(
-  new boom.common.WithNMegaBooms(1) ++                           // mega boom config
+class MegaBoomV3Config extends Config(
+  new boom.v3.common.WithNMegaBooms(1) ++                           // mega boom config
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
-class DualSmallBoomConfig extends Config(
-  new boom.common.WithNSmallBooms(2) ++                          // 2 boom cores
+class DualSmallBoomV3Config extends Config(
+  new boom.v3.common.WithNSmallBooms(2) ++                          // 2 boom cores
   new chipyard.config.AbstractConfig)
 
-class Cloned64MegaBoomConfig extends Config(
-  new boom.common.WithCloneBoomTiles(63, 0) ++
-  new boom.common.WithNMegaBooms(1) ++                           // mega boom config
+class Cloned64MegaBoomV3Config extends Config(
+  new boom.v3.common.WithCloneBoomTiles(63, 0) ++
+  new boom.v3.common.WithNMegaBooms(1) ++                           // mega boom config
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
-class LoopbackNICLargeBoomConfig extends Config(
+class LoopbackNICLargeBoomV3Config extends Config(
   new chipyard.harness.WithLoopbackNIC ++                        // drive NIC IOs with loopback
   new icenet.WithIceNIC ++                                       // build a NIC
-  new boom.common.WithNLargeBooms(1) ++
+  new boom.v3.common.WithNLargeBooms(1) ++
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
-class MediumBoomCosimConfig extends Config(
+class MediumBoomV3CosimConfig extends Config(
   new chipyard.harness.WithCospike ++                            // attach spike-cosim
   new chipyard.config.WithTraceIO ++                             // enable the traceio
-  new boom.common.WithNMediumBooms(1) ++
+  new boom.v3.common.WithNMediumBooms(1) ++
   new chipyard.config.AbstractConfig)
 
-class dmiMediumBoomConfig extends Config(
+class dmiMediumBoomV3Config extends Config(
   new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anything to serial-tl
   new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
-  new boom.common.WithNMediumBooms(1) ++
+  new boom.v3.common.WithNMediumBooms(1) ++
   new chipyard.config.AbstractConfig)
 
-class dmiMediumBoomCosimConfig extends Config(
+class dmiMediumBoomV3CosimConfig extends Config(
   new chipyard.harness.WithCospike ++                            // attach spike-cosim
   new chipyard.config.WithTraceIO ++                             // enable the traceio
   new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anythint to serial-tl
   new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
-  new boom.common.WithNMediumBooms(1) ++
+  new boom.v3.common.WithNMediumBooms(1) ++
+  new chipyard.config.AbstractConfig)
+
+
+// ---------------------
+// BOOM V4 Configs
+// Less stable and performant, but with more advanced micro-architecture
+// Use for PD exploration
+// ---------------------
+
+class SmallBoomV4Config extends Config(
+  new boom.v4.common.WithNSmallBooms(1) ++                          // small boom config
+  new chipyard.config.AbstractConfig)
+
+class MediumBoomV4Config extends Config(
+  new boom.v4.common.WithNMediumBooms(1) ++                         // medium boom config
+  new chipyard.config.AbstractConfig)
+
+class LargeBoomV4Config extends Config(
+  new boom.v4.common.WithNLargeBooms(1) ++                          // large boom config
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new chipyard.config.AbstractConfig)
+
+class MegaBoomV4Config extends Config(
+  new boom.v4.common.WithNMegaBooms(1) ++                           // mega boom config
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new chipyard.config.AbstractConfig)
+
+class DualSmallBoomV4Config extends Config(
+  new boom.v4.common.WithNSmallBooms(2) ++                          // 2 boom cores
+  new chipyard.config.AbstractConfig)
+
+class Cloned64MegaBoomV4Config extends Config(
+  new boom.v4.common.WithCloneBoomTiles(63, 0) ++
+  new boom.v4.common.WithNMegaBooms(1) ++                           // mega boom config
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new chipyard.config.AbstractConfig)
+
+class MediumBoomV4CosimConfig extends Config(
+  new chipyard.harness.WithCospike ++                            // attach spike-cosim
+  new chipyard.config.WithTraceIO ++                             // enable the traceio
+  new boom.v4.common.WithNMediumBooms(1) ++
+  new chipyard.config.AbstractConfig)
+
+class dmiMediumBoomV4Config extends Config(
+  new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anything to serial-tl
+  new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
+  new boom.v4.common.WithNMediumBooms(1) ++
+  new chipyard.config.AbstractConfig)
+
+class dmiMediumBoomV4CosimConfig extends Config(
+  new chipyard.harness.WithCospike ++                            // attach spike-cosim
+  new chipyard.config.WithTraceIO ++                             // enable the traceio
+  new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anythint to serial-tl
+  new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
+  new boom.v4.common.WithNMediumBooms(1) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
index 52f39a03..c34492a4 100644
--- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
@@ -31,7 +31,7 @@ class ChipLikeRocketConfig extends Config(
       isMemoryDevice = true
     )),
     client = Some(testchipip.serdes.SerialTLClientParams()),                            // Allow an external manager to probe this chip
-    phyParams = testchipip.serdes.ExternalSyncSerialParams(width=4)                     // 4-bit bidir interface, sync'd to an external clock
+    phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=4, flitWidth=16)   // 4-bit bidir interface, sync'd to an external clock
   ))) ++
 
   new freechips.rocketchip.subsystem.WithNoMemPort ++                                   // Remove axi4 mem port
@@ -77,8 +77,8 @@ class ChipBringupHostConfig extends Config(
         size    = BigInt("80000000", 16)
       ))
     )),
-    client = Some(testchipip.serdes.SerialTLClientParams()),                         // Allow chip to access this device's memory (DRAM)
-    phyParams = testchipip.serdes.InternalSyncSerialParams(width=4, freqMHz = 75)    // bringup platform provides the clock
+    client = Some(testchipip.serdes.SerialTLClientParams()),                                        // Allow chip to access this device's memory (DRAM)
+    phyParams = testchipip.serdes.InternalSyncSerialPhyParams(phitWidth=4, flitWidth=16, freqMHz = 75) // bringup platform provides the clock
   ))) ++
 
   //============================
diff --git a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
index a7d2113f..dbf3fa0a 100644
--- a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
@@ -16,7 +16,7 @@ class SymmetricChipletRocketConfig extends Config(
   new testchipip.serdes.WithSerialTL(Seq(
     testchipip.serdes.SerialTLParams(                               // 0th serial-tl is chip-to-bringup-fpga
       client = Some(testchipip.serdes.SerialTLClientParams()),      // bringup serial-tl acts only as a client
-      phyParams = testchipip.serdes.ExternalSyncSerialParams()      // bringup serial-tl is sync'd to external clock
+      phyParams = testchipip.serdes.ExternalSyncSerialPhyParams()   // bringup serial-tl is sync'd to external clock
     ),
     testchipip.serdes.SerialTLParams(                               // 1st serial-tl is chip-to-chip
       client = Some(testchipip.serdes.SerialTLClientParams()),      // chip-to-chip serial-tl acts as a client
@@ -27,7 +27,7 @@ class SymmetricChipletRocketConfig extends Config(
         )),
         slaveWhere = OBUS
       )),
-      phyParams = testchipip.serdes.SourceSyncSerialParams()        // chip-to-chip serial-tl is symmetric source-sync'd
+      phyParams = testchipip.serdes.SourceSyncSerialPhyParams()     // chip-to-chip serial-tl is symmetric source-sync'd
     ))
   ) ++
   new testchipip.soc.WithOffchipBusClient(SBUS,                     // obus provides path to other chip's memory
@@ -45,3 +45,49 @@ class MultiSimSymmetricChipletRocketConfig extends Config(
   new chipyard.harness.WithMultiChip(0, new SymmetricChipletRocketConfig) ++
   new chipyard.harness.WithMultiChip(1, new SymmetricChipletRocketConfig)
 )
+
+// Core-only chiplet config, where the coherent memory is located on the LLC-chiplet
+class RocketCoreChipletConfig extends Config(
+  new testchipip.serdes.WithSerialTL(Seq(
+    testchipip.serdes.SerialTLParams(
+      client = Some(testchipip.serdes.SerialTLClientParams()),
+      phyParams = testchipip.serdes.ExternalSyncSerialPhyParams()     // chip-to-chip serial-tl is symmetric source-sync'd
+    ),
+    testchipip.serdes.SerialTLParams(
+      manager = Some(testchipip.serdes.SerialTLManagerParams(
+        cohParams = Seq(testchipip.serdes.ManagerCOHParams(
+          address = BigInt("80000000", 16),
+          size    = BigInt("100000000", 16)
+        )),
+        slaveWhere = OBUS,
+        isMemoryDevice = true
+      )),
+      phyParams = testchipip.serdes.SourceSyncSerialPhyParams()
+    )
+  )) ++
+  new testchipip.soc.WithOffchipBusClient(SBUS) ++
+  new testchipip.soc.WithOffchipBus ++
+  new testchipip.soc.WithNoScratchpads ++
+  new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
+  new freechips.rocketchip.subsystem.WithNoMemPort ++
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+// LLC-only chiplet
+class LLCChipletConfig extends Config(
+  new chipyard.harness.WithSerialTLTiedOff ++
+  new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(                               // 1st serial-tl is chip-to-chip
+    client = Some(testchipip.serdes.SerialTLClientParams(supportsProbe=true)),
+    phyParams = testchipip.serdes.SourceSyncSerialPhyParams()     // chip-to-chip serial-tl is symmetric source-sync'd
+  ))) ++
+  new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++
+  new chipyard.NoCoresConfig
+)
+
+class MultiSimLLCChipletRocketConfig extends Config(
+  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++
+  new chipyard.harness.WithMultiChipSerialTL(chip0=0, chip1=1, chip0portId=1, chip1portId=0) ++
+  new chipyard.harness.WithMultiChip(0, new RocketCoreChipletConfig) ++
+  new chipyard.harness.WithMultiChip(1, new LLCChipletConfig)
+)
diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala
index 206b086b..f2e12ec0 100644
--- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala
@@ -7,7 +7,7 @@ import org.chipsalliance.cde.config.{Config}
 // ---------------------
 
 class LargeBoomAndRocketConfig extends Config(
-  new boom.common.WithNLargeBooms(1) ++                          // single-core boom
+  new boom.v3.common.WithNLargeBooms(1) ++                          // single-core boom
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
@@ -16,7 +16,7 @@ class LargeBoomAndRocketConfig extends Config(
 class HwachaLargeBoomAndHwachaRocketConfig extends Config(
   new chipyard.config.WithHwachaTest ++
   new hwacha.DefaultHwachaConfig ++                          // add hwacha to all harts
-  new boom.common.WithNLargeBooms(1) ++                      // add 1 boom core
+  new boom.v3.common.WithNLargeBooms(1) ++                      // add 1 boom core
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++     // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
@@ -26,7 +26,7 @@ class LargeBoomAndHwachaRocketConfig extends Config(
   new chipyard.config.WithMultiRoCC ++                                  // support heterogeneous rocc
   new chipyard.config.WithMultiRoCCHwacha(0) ++                         // put hwacha on hart-0 (rocket)
   new hwacha.DefaultHwachaConfig ++                                     // set default hwacha config keys
-  new boom.common.WithNLargeBooms(1) ++                                 // add 1 boom core
+  new boom.v3.common.WithNLargeBooms(1) ++                                 // add 1 boom core
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++                // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
@@ -36,21 +36,21 @@ class DualLargeBoomAndHwachaRocketConfig extends Config(
   new chipyard.config.WithMultiRoCC ++                                  // support heterogeneous rocc
   new chipyard.config.WithMultiRoCCHwacha(0) ++                         // put hwacha on hart-0 (rocket)
   new hwacha.DefaultHwachaConfig ++                                     // set default hwacha config keys
-  new boom.common.WithNLargeBooms(2) ++                                 // add 2 boom cores
+  new boom.v3.common.WithNLargeBooms(2) ++                                 // add 2 boom cores
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++                // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: DualBoomAndRocketOneHwacha
 
 class DualLargeBoomAndDualRocketConfig extends Config(
-  new boom.common.WithNLargeBooms(2) ++                   // add 2 boom cores
+  new boom.v3.common.WithNLargeBooms(2) ++                   // add 2 boom cores
   new freechips.rocketchip.subsystem.WithNBigCores(2) ++  // add 2 rocket cores
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: DualBoomAndSingleRocket
 class DualLargeBoomAndSingleRocketConfig extends Config(
-  new boom.common.WithNLargeBooms(2) ++                   // add 2 boom cores
+  new boom.v3.common.WithNLargeBooms(2) ++                   // add 2 boom cores
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++  // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
@@ -58,7 +58,7 @@ class DualLargeBoomAndSingleRocketConfig extends Config(
 
 class LargeBoomAndRocketWithControlCoreConfig extends Config(
   new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // Add a small "control" core
-  new boom.common.WithNLargeBooms(1) ++                    // Add 1 boom core
+  new boom.v3.common.WithNLargeBooms(1) ++                    // Add 1 boom core
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++   // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
index 8d6f1063..fc6466ce 100644
--- a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
@@ -59,6 +59,7 @@ class LargeNVDLARocketConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class ManyMMIOAcceleratorRocketConfig extends Config(
+  new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++   // add InitZero
   new chipyard.harness.WithDontTouchChipTopPorts(false) ++   // TODO: hack around dontTouch not working in SFC
   new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
   new chipyard.example.WithStreamingPassthrough ++          // use top with tilelink-controlled streaming passthrough
diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala
index 4288fa84..a5acc1e0 100644
--- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala
@@ -240,7 +240,7 @@ class SbusMeshNoCConfig extends Config(
         "Core 9 " -> 13,
         "Core 10 " -> 14,
         "Core 11 " -> 15,
-        "serial-tl" -> 0),
+        "serial_tl" -> 0),
       outNodeMapping = ListMap(
         "system[0]" -> 5,
         "system[1]" -> 6,
@@ -251,14 +251,16 @@ class SbusMeshNoCConfig extends Config(
       topology        = Mesh2D(4, 4),
       channelParamGen = (a, b) => UserChannelParams(Seq.fill(3) { UserVirtualChannelParams(3) }, unifiedBuffer = false),
       routerParams    = (i) => UserRouterParams(combineRCVA=true, combineSAST=true),
-      routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 3, 1)),
+      routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 3, 1),
+    ),
     beNoCParams = NoCParams(
       topology        = Mesh2D(4, 4),
       channelParamGen = (a, b) => UserChannelParams(Seq.fill(2) { UserVirtualChannelParams(3) }, unifiedBuffer = false),
       routerParams    = (i) => UserRouterParams(combineRCVA=true, combineSAST=true),
-      routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 2, 1)),
+      routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 2, 1),
+    ),
     beDivision = 4
-  )) ++
+  ), inlineNoC = true) ++
   new freechips.rocketchip.subsystem.WithNBigCores(12) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new chipyard.config.WithSystemBusWidth(128) ++
diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
index 99400743..fa74d9b8 100644
--- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
@@ -75,6 +75,7 @@ class ManyPeripheralsRocketConfig extends Config(
   new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
   new chipyard.harness.WithSimSPIFlashModel(true) ++         // add the SPI flash model in the harness (read-only)
   new chipyard.harness.WithSimBlockDevice ++                 // drive block-device IOs with SimBlockDevice
+  new chipyard.config.WithPeripheryTimer ++                  // add the pwm timer device
   new chipyard.config.WithSPIFlash ++                        // add the SPI flash controller
   new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++  // add default external master port
   new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
index 0796bade..32c5fe19 100644
--- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
@@ -50,10 +50,10 @@ class MempressRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
-class HwachaLargeBoomConfig extends Config(
+class HwachaLargeBoomV3Config extends Config(
   new chipyard.config.WithHwachaTest ++
   new hwacha.DefaultHwachaConfig ++                              // use Hwacha vector accelerator
-  new boom.common.WithNLargeBooms(1) ++
+  new boom.v3.common.WithNLargeBooms(1) ++
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
index 6f4c6ab7..b7b829dd 100644
--- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
@@ -18,7 +18,8 @@ class dmiSpikeConfig extends Config(
 // Avoids polling on the UART registers
 class SpikeFastUARTConfig extends Config(
   new chipyard.WithNSpikeCores(1) ++
-  new chipyard.config.WithUARTFIFOEntries(128, 128) ++
+  new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer, 
+  new chipyard.config.WithNoUART() ++                           // so we overwrite the default one
   new chipyard.config.WithMemoryBusFrequency(2) ++
   new chipyard.config.WithPeripheryBusFrequency(2) ++
   new chipyard.config.AbstractConfig)
@@ -27,7 +28,8 @@ class SpikeFastUARTConfig extends Config(
 class SpikeUltraFastConfig extends Config(
   new chipyard.WithSpikeTCM ++
   new chipyard.WithNSpikeCores(1) ++
-  new chipyard.config.WithUARTFIFOEntries(128, 128) ++
+  new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer, 
+  new chipyard.config.WithNoUART() ++                           // so we overwrite the default one
   new chipyard.config.WithMemoryBusFrequency(2) ++
   new chipyard.config.WithPeripheryBusFrequency(2) ++
   new chipyard.config.WithBroadcastManager ++
@@ -47,7 +49,8 @@ class SpikeUltraFastDevicesConfig extends Config(
 
   new chipyard.WithSpikeTCM ++
   new chipyard.WithNSpikeCores(1) ++
-  new chipyard.config.WithUARTFIFOEntries(128, 128) ++
+  new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer, 
+  new chipyard.config.WithNoUART() ++                           // so we overwrite the default one
   new chipyard.config.WithMemoryBusFrequency(2) ++
   new chipyard.config.WithPeripheryBusFrequency(2) ++
   new chipyard.config.WithBroadcastManager ++
diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
index c9db790d..7c6c43cb 100644
--- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
@@ -32,8 +32,13 @@ class NonBlockingTraceGenConfig extends Config(
   new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
   new AbstractTraceGenConfig)
 
-class BoomTraceGenConfig extends Config(
-  new tracegen.WithBoomTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
+class BoomV3TraceGenConfig extends Config(
+  new tracegen.WithBoomV3TraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new AbstractTraceGenConfig)
+
+class BoomV4TraceGenConfig extends Config(
+  new tracegen.WithBoomV4TraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
   new freechips.rocketchip.subsystem.WithInclusiveCache ++
   new AbstractTraceGenConfig)
 
diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
index cf93d0e4..7225c800 100644
--- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
@@ -32,7 +32,7 @@ class TutorialStarterConfig extends Config(
   // Uncomment out one (or multiple) of the lines below, and choose
   // how many cores you want.
   // new freechips.rocketchip.subsystem.WithNBigCores(1) ++    // Specify we want some number of Rocket cores
-  // new boom.common.WithNSmallBooms(1) ++                     // Specify we want some number of BOOM cores
+  // new boom.v3.common.WithNSmallBooms(1) ++                     // Specify we want some number of BOOM cores
 
   // CUSTOMIZE the L2
   // Uncomment this line, and specify a size if you want to have a L2
diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
index 51d31094..265be720 100644
--- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
@@ -16,6 +16,7 @@ import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.spi._
 import sifive.blocks.devices.i2c._
+import sifive.blocks.devices.timer._
 
 import testchipip._
 
@@ -65,11 +66,12 @@ class WithNoUART extends Config((site, here, up) => {
   * @param address the address of the UART device
   * @param baudrate the baudrate of the UART device
   */
-class WithUART(baudrate: BigInt = 115200, address: BigInt = 0x10020000) extends Config ((site, here, up) => {
+class WithUART(baudrate: BigInt = 115200, address: BigInt = 0x10020000, txEntries: Int = 8, rxEntries: Int = 8) extends Config ((site, here, up) => {
   case PeripheryUARTKey => up(PeripheryUARTKey) ++ Seq(
-    UARTParams(address = address, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate))
+    UARTParams(address = address, nTxEntries = txEntries, nRxEntries = rxEntries, initBaudRate = baudrate))
 })
 
+// @deprecated("Use WithUART instead of WithUARTFIFOEntries", "chipyard v1.10")
 class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, here, up) => {
   case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries))
 })
@@ -168,3 +170,7 @@ class WithNoBusErrorDevices extends Config((site, here, up) => {
   case MemoryBusKey => up(MemoryBusKey).copy(errorDevice = None)
   case FrontBusKey => up(FrontBusKey).copy(errorDevice = None)
 })
+
+class WithPeripheryTimer(timerParams: TimerParams = TimerParams(0x4000)) extends Config((site, here, up) => {
+  case PeripheryTimerKey => Seq(timerParams)
+})
diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
index 392f1508..c9493e78 100644
--- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
@@ -5,9 +5,8 @@ import chisel3._
 import org.chipsalliance.cde.config.{Field, Parameters, Config}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.subsystem._
-import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
+import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams, PgLevels}
 
-import boom.common.{BoomTileAttachParams}
 import cva6.{CVA6TileAttachParams}
 import sodor.common.{SodorTileAttachParams}
 import ibex.{IbexTileAttachParams}
@@ -18,7 +17,9 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
-    case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+    case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
+    case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
     case other => other
   }
@@ -26,7 +27,9 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
 
 class WithTraceIO extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+    case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(trace = true)))
+    case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       core = tp.tileParams.core.copy(trace = true)))
     case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       trace = true))
@@ -37,7 +40,9 @@ class WithTraceIO extends Config((site, here, up) => {
 
 class WithNoTraceIO extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+    case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(trace = false)))
+    case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       core = tp.tileParams.core.copy(trace = false)))
     case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       trace = false))
@@ -50,7 +55,9 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       core = tp.tileParams.core.copy(nPerfCounters = n)))
-    case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+    case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(nPerfCounters = n)))
+    case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       core = tp.tileParams.core.copy(nPerfCounters = n)))
     case other => other
   }
@@ -60,7 +67,9 @@ class WithNPMPs(n: Int = 8) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       core = tp.tileParams.core.copy(nPMPs = n)))
-    case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+    case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(nPMPs = n)))
+    case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       core = tp.tileParams.core.copy(nPMPs = n)))
     case other => other
   }
@@ -95,7 +104,9 @@ class WithTilePrefetchers extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
       master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
-    case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
+    case tp: boom.v3.common.BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
+      master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
+    case tp: boom.v4.common.BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
       master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
     case tp: SodorTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
       master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
@@ -108,10 +119,15 @@ class WithTilePrefetchers extends Config((site, here, up) => {
 
 // Adds boundary buffers to RocketTiles, which places buffers between the caches and the TileLink interface
 // This typically makes it easier to close timing
-class WithRocketBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams] = Some(RocketTileBoundaryBufferParams(true))) extends Config((site, here, up) => {                                                                                                                                                           
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) map {                                                                                                                                                                                                                                                      
-    case tp: RocketTileAttachParams => tp.copy(tileParams=tp.tileParams.copy(                                                                                                                                                                                                                                                
-      boundaryBuffers=buffers                                                                                                                                                                                                                                                                                                
-    ))                                                                                                                                                                                                                                                                                                                       
-  }                                                                                                                                                                                                                                                                                                                          
-})   
+class WithRocketBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams] = Some(RocketTileBoundaryBufferParams(true))) extends Config((site, here, up) => {
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) map {
+    case tp: RocketTileAttachParams => tp.copy(tileParams=tp.tileParams.copy(
+      boundaryBuffers=buffers
+    ))
+  }
+})
+
+// Uses SV48 if possible, otherwise default to the Rocket Chip core default
+class WithSV48IfPossible extends Config((site, here, up) => {
+  case PgLevels => if (site(XLen) == 64) 4 /* Sv48 */ else up(PgLevels)
+})
diff --git a/generators/chipyard/src/main/scala/example/CustomChipTop.scala b/generators/chipyard/src/main/scala/example/CustomChipTop.scala
index f710ccab..eb0565ce 100644
--- a/generators/chipyard/src/main/scala/example/CustomChipTop.scala
+++ b/generators/chipyard/src/main/scala/example/CustomChipTop.scala
@@ -67,13 +67,13 @@ class WithCustomChipTop extends Config((site, here, up) => {
 })
 
 class WithBrokenOutUARTIO extends OverrideIOBinder({
-  (system: HasPeripheryUARTModuleImp) => {
+  (system: HasPeripheryUART) => {
     val uart_txd = IO(Output(Bool()))
     val uart_rxd = IO(Input(Bool()))
     system.uart(0).rxd := uart_rxd
     uart_txd := system.uart(0).txd
     val where = PBUS // TODO fix
-    val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
+    val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
     val freqMHz = bus.dtsFrequency.get / 1000000
     (Seq(UARTPort(() => {
       val uart_wire = Wire(new UARTPortIO(system.uart(0).c))
diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala
index d4caa49b..6b249286 100644
--- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala
+++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala
@@ -145,7 +145,7 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor
     // UART
     //==========================
     require(system.uarts.size == 1)
-    val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.module.uart.head, "uart_0", p(IOCellKey))
+    val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.uart.head, "uart_0", p(IOCellKey))
     val where = PBUS // TODO fix
     val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
     val freqMHz = bus.dtsFrequency.get / 1000000
diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
index 8bbbb205..c97ff84c 100644
--- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
+++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
@@ -47,16 +47,16 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
 
   // Figure out which clock drives the harness TLSerdes, based on the port type
   val serial_ram_clock = dut.serial_tl_pad match {
-    case io: InternalSyncSerialIO => io.clock_out
-    case io: ExternalSyncSerialIO => clock
+    case io: InternalSyncPhitIO => io.clock_out
+    case io: ExternalSyncPhitIO => clock
   }
   dut.serial_tl_pad match {
-    case io: ExternalSyncSerialIO => io.clock_in := clock
-    case io: InternalSyncSerialIO =>
+    case io: ExternalSyncPhitIO => io.clock_in := clock
+    case io: InternalSyncPhitIO =>
   }
 
   dut.serial_tl_pad match {
-    case pad: DecoupledSerialIO => {
+    case pad: DecoupledPhitIO => {
       withClockAndReset(serial_ram_clock, reset) {
         // SerialRAM implements the memory regions the chip expects
         val ram = Module(LazyModule(new SerialRAM(lazyDut.system.serdessers(0), p(SerialTLKey)(0))).module)
diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala
index ef3edc1f..7fdb1714 100644
--- a/generators/chipyard/src/main/scala/example/GCD.scala
+++ b/generators/chipyard/src/main/scala/example/GCD.scala
@@ -5,7 +5,7 @@ import chisel3.util._
 import chisel3.experimental.{IntParam, BaseModule}
 import freechips.rocketchip.amba.axi4._
 import freechips.rocketchip.prci._
-import freechips.rocketchip.subsystem.BaseSubsystem
+import freechips.rocketchip.subsystem.{BaseSubsystem, PBUS}
 import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper.{HasRegMap, RegField}
@@ -194,6 +194,8 @@ class GCDAXI4(params: GCDParams, beatBytes: Int)(implicit p: Parameters) extends
 trait CanHavePeripheryGCD { this: BaseSubsystem =>
   private val portName = "gcd"
 
+  private val pbus = locateTLBusWrapper(PBUS)
+
   // Only build if we are using the TL (nonAXI4) version
   val gcd_busy = p(GCDKey) match {
     case Some(params) => {
diff --git a/generators/chipyard/src/main/scala/example/InitZero.scala b/generators/chipyard/src/main/scala/example/InitZero.scala
index 78237eca..f39661af 100644
--- a/generators/chipyard/src/main/scala/example/InitZero.scala
+++ b/generators/chipyard/src/main/scala/example/InitZero.scala
@@ -2,7 +2,7 @@ package chipyard.example
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
+import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes, FBUS}
 import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}
 import freechips.rocketchip.tilelink._
@@ -61,7 +61,8 @@ trait CanHavePeripheryInitZero { this: BaseSubsystem =>
   implicit val p: Parameters
 
   p(InitZeroKey) .map { k =>
-    val initZero = LazyModule(new InitZero()(p))
+    val fbus = locateTLBusWrapper(FBUS)
+    val initZero = fbus { LazyModule(new InitZero()(p)) }
     fbus.coupleFrom("init-zero") { _ := initZero.node }
   }
 }
diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
index df2ec35a..cefd1915 100644
--- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
+++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
@@ -199,6 +199,7 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: => Seq[T], p
 trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
   val streamingFIR = p(GenericFIRKey) match {
     case Some(params) => {
+      val pbus = locateTLBusWrapper(PBUS)
       val domain = pbus.generateSynchronousDomain.suggestName("fir_domain")
       val streamingFIR = domain { LazyModule(new TLGenericFIRChain(
         genIn = FixedPoint(8.W, 3.BP),
diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
index a2259ab1..154a3650 100644
--- a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
+++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
@@ -131,6 +131,7 @@ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughPara
 trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
   val passthrough = p(StreamingPassthroughKey) match {
     case Some(params) => {
+      val pbus = locateTLBusWrapper(PBUS)
       val domain = pbus.generateSynchronousDomain.suggestName("streaming_passthrough_domain")
       val streamingPassthroughChain = domain { LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) }
       pbus.coupleTo("streamingPassthrough") { domain { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes)} := _ }
diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
index e862d520..4cc1b2af 100644
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -44,6 +44,14 @@ class HarnessBinder[T <: HasHarnessInstantiators, S <: Port[_]](
 class WithGPIOTiedOff extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: GPIOPort, chipId: Int) => {
     port.io <> AnalogConst(0)
+
+  }
+})
+
+class WithGPIOPinsTiedOff extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: GPIOPinsPort, chipId: Int) => {
+    port.io := DontCare
+
   }
 })
 
@@ -209,17 +217,17 @@ class WithTiedOffDMI extends HarnessBinder({
 class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (tieoffs.map(_.contains(port.portId)).getOrElse(true)) => {
     port.io match {
-      case io: DecoupledSerialIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare;
-      case io: SourceSyncSerialIO => {
+      case io: DecoupledPhitIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare;
+      case io: SourceSyncPhitIO => {
         io.clock_in := false.B.asClock
         io.reset_in := false.B.asAsyncReset
         io.in := DontCare
-        io.credit_in := DontCare
       }
     }
     port.io match {
-      case io: InternalSyncSerialIO =>
-      case io: ExternalSyncSerialIO => io.clock_in := false.B.asClock
+      case io: InternalSyncPhitIO =>
+      case io: ExternalSyncPhitIO => io.clock_in := false.B.asClock
+      case io: SourceSyncPhitIO =>
       case _ =>
     }
   }
@@ -228,17 +236,18 @@ class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinde
 class WithSimTSIOverSerialTL extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (port.portId == 0) => {
     port.io match {
-      case io: InternalSyncSerialIO =>
-      case io: ExternalSyncSerialIO => io.clock_in := th.harnessBinderClock
+      case io: InternalSyncPhitIO =>
+      case io: ExternalSyncPhitIO => io.clock_in := th.harnessBinderClock
+      case io: SourceSyncPhitIO => io.clock_in := th.harnessBinderClock; io.reset_in := th.harnessBinderReset
     }
 
     port.io match {
-      case io: DecoupledSerialIO => {
+      case io: DecoupledPhitIO => {
         // If the port is locally synchronous (provides a clock), drive everything with that clock
         // Else, drive everything with the harnes clock
         val clock = port.io match {
-          case io: InternalSyncSerialIO => io.clock_out
-          case io: ExternalSyncSerialIO => th.harnessBinderClock
+          case io: InternalSyncPhitIO => io.clock_out
+          case io: ExternalSyncPhitIO => th.harnessBinderClock
         }
         withClock(clock) {
           val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module)
diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
index 5da69fc7..55ff4191 100644
--- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
@@ -59,25 +59,23 @@ class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1p
   (p0: SerialTLPort) => p0.portId == chip0portId,
   (p1: SerialTLPort) => p1.portId == chip1portId,
   (th: HasHarnessInstantiators, p0: SerialTLPort, p1: SerialTLPort) => {
-    def connectDecoupledSyncSerialIO(clkSource: InternalSyncSerialIO, clkSink: ExternalSyncSerialIO) = {
+    def connectDecoupledSyncPhitIO(clkSource: InternalSyncPhitIO, clkSink: ExternalSyncPhitIO) = {
       clkSink.clock_in := clkSource.clock_out
       clkSink.in <> clkSource.out
       clkSource.in <> clkSink.out
     }
-    def connectSourceSyncSerialIO(a: SourceSyncSerialIO, b: SourceSyncSerialIO) = {
+    def connectSourceSyncPhitIO(a: SourceSyncPhitIO, b: SourceSyncPhitIO) = {
       a.clock_in := b.clock_out
       b.clock_in := a.clock_out
       a.reset_in := b.reset_out
       b.reset_in := a.reset_out
       a.in := b.out
       b.in := a.out
-      a.credit_in := b.credit_out
-      b.credit_in := a.credit_out
     }
     (p0.io, p1.io) match {
-      case (io0: InternalSyncSerialIO, io1: ExternalSyncSerialIO) => connectDecoupledSyncSerialIO(io0, io1)
-      case (io0: ExternalSyncSerialIO, io1: InternalSyncSerialIO) => connectDecoupledSyncSerialIO(io1, io0)
-      case (io0: SourceSyncSerialIO  , io1: SourceSyncSerialIO  ) => connectSourceSyncSerialIO   (io0, io1)
+      case (io0: InternalSyncPhitIO, io1: ExternalSyncPhitIO) => connectDecoupledSyncPhitIO(io0, io1)
+      case (io0: ExternalSyncPhitIO, io1: InternalSyncPhitIO) => connectDecoupledSyncPhitIO(io1, io0)
+      case (io0: SourceSyncPhitIO  , io1: SourceSyncPhitIO  ) => connectSourceSyncPhitIO   (io0, io1)
     }
   }
 )
diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
index ae9f0cf2..4b1eb640 100644
--- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
@@ -5,7 +5,12 @@ import chisel3.reflect.DataMirror
 import chisel3.experimental.Analog
 
 import org.chipsalliance.cde.config._
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy._
+import org.chipsalliance.diplomacy.nodes._
+import org.chipsalliance.diplomacy.aop._
+import org.chipsalliance.diplomacy.lazymodule._
+import org.chipsalliance.diplomacy.bundlebridge._
+import freechips.rocketchip.diplomacy.{Resource, ResourceBinding, ResourceAddress}
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.jtag.{JTAGIO}
 import freechips.rocketchip.subsystem._
@@ -165,15 +170,17 @@ case object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams())
 
 
 class WithGPIOCells extends OverrideIOBinder({
-  (system: HasPeripheryGPIOModuleImp) => {
+  (system: HasPeripheryGPIO) => {
     val (ports2d, cells2d) = system.gpio.zipWithIndex.map({ case (gpio, i) =>
       gpio.pins.zipWithIndex.map({ case (pin, j) =>
+        val p = system.asInstanceOf[BaseSubsystem].p
         val g = IO(Analog(1.W)).suggestName(s"gpio_${i}_${j}")
-        val iocell = system.p(IOCellKey).gpio().suggestName(s"iocell_gpio_${i}_${j}")
+        val iocell = p(IOCellKey).gpio().suggestName(s"iocell_gpio_${i}_${j}")
         iocell.io.o := pin.o.oval
         iocell.io.oe := pin.o.oe
         iocell.io.ie := pin.o.ie
         pin.i.ival := iocell.io.i
+        pin.i.po.foreach(_ := DontCare)
         iocell.io.pad <> g
         (GPIOPort(() => g, i, j), iocell)
       }).unzip
@@ -183,7 +190,7 @@ class WithGPIOCells extends OverrideIOBinder({
 })
 
 class WithGPIOPunchthrough extends OverrideIOBinder({
-  (system: HasPeripheryGPIOModuleImp) => {
+  (system: HasPeripheryGPIO) => {
     val ports = system.gpio.zipWithIndex.map { case (gpio, i) =>
       val io_gpio = IO(gpio.cloneType).suggestName(s"gpio_$i")
       io_gpio <> gpio
@@ -194,7 +201,7 @@ class WithGPIOPunchthrough extends OverrideIOBinder({
 })
 
 class WithI2CPunchthrough extends OverrideIOBinder({
-  (system: HasPeripheryI2CModuleImp) => {
+  (system: HasPeripheryI2C) => {
     val ports = system.i2c.zipWithIndex.map { case (i2c, i) =>
       val io_i2c = IO(i2c.cloneType).suggestName(s"i2c_$i")
       io_i2c <> i2c
@@ -206,11 +213,12 @@ class WithI2CPunchthrough extends OverrideIOBinder({
 
 // DOC include start: WithUARTIOCells
 class WithUARTIOCells extends OverrideIOBinder({
-  (system: HasPeripheryUARTModuleImp) => {
+  (system: HasPeripheryUART) => {
     val (ports: Seq[UARTPort], cells2d) = system.uart.zipWithIndex.map({ case (u, i) =>
-      val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", system.p(IOCellKey), abstractResetAsAsync = true)
+      val p = system.asInstanceOf[BaseSubsystem].p
+      val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", p(IOCellKey), abstractResetAsAsync = true)
       val where = PBUS // TODO fix
-      val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
+      val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
       val freqMHz = bus.dtsFrequency.get / 1000000
       (UARTPort(() => port, i, freqMHz.toInt), ios)
     }).unzip
@@ -226,7 +234,7 @@ class WithSPIIOPunchthrough extends OverrideLazyIOBinder({
       Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0))
     }
     InModuleBody {
-      val spi = system.asInstanceOf[BaseSubsystem].module.asInstanceOf[HasPeripherySPIBundle].spi
+      val spi = system.spi
       val ports = spi.zipWithIndex.map({ case (s, i) =>
         val io_spi = IO(s.cloneType).suggestName(s"spi_$i")
         io_spi <> s
@@ -238,20 +246,20 @@ class WithSPIIOPunchthrough extends OverrideLazyIOBinder({
 })
 
 class WithSPIFlashIOCells extends OverrideIOBinder({
-  (system: HasPeripherySPIFlashModuleImp) => {
+  (system: HasPeripherySPIFlash) => {
     val (ports: Seq[SPIFlashPort], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) =>
-
+      val p = system.asInstanceOf[BaseSubsystem].p
       val name = s"spi_${i}"
       val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(name)
       val iocellBase = s"iocell_${name}"
 
       // SCK and CS are unidirectional outputs
-      val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), system.p(IOCellKey), IOCell.toAsyncReset)
-      val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), system.p(IOCellKey), IOCell.toAsyncReset)
+      val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), p(IOCellKey), IOCell.toAsyncReset)
+      val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), p(IOCellKey), IOCell.toAsyncReset)
 
       // DQ are bidirectional, so then need special treatment
       val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) =>
-        val iocell = system.p(IOCellKey).gpio().suggestName(s"${iocellBase}_dq_${j}")
+        val iocell = p(IOCellKey).gpio().suggestName(s"${iocellBase}_dq_${j}")
         iocell.io.o := pin.o
         iocell.io.oe := pin.oe
         iocell.io.ie := true.B
@@ -260,7 +268,7 @@ class WithSPIFlashIOCells extends OverrideIOBinder({
         iocell
       }
 
-      (SPIFlashPort(() => port, system.p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs)
+      (SPIFlashPort(() => port, p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs)
     }).unzip
     (ports, cells2d.flatten)
   }
@@ -418,7 +426,8 @@ class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({
   (system: CanHaveSlaveAXI4Port) => {
     implicit val p: Parameters = GetSystemParameters(system)
     val clockSinkNode = p(ExtIn).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
-    clockSinkNode.map(_ := system.asInstanceOf[BaseSubsystem].fbus.fixedClockNode)
+    val fbus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(FBUS)
+    clockSinkNode.map(_ := fbus.fixedClockNode)
     def clockBundle = clockSinkNode.get.in.head._1
 
     InModuleBody {
diff --git a/generators/chipyard/src/main/scala/iobinders/Ports.scala b/generators/chipyard/src/main/scala/iobinders/Ports.scala
index 6b327a18..a9ea0a2d 100644
--- a/generators/chipyard/src/main/scala/iobinders/Ports.scala
+++ b/generators/chipyard/src/main/scala/iobinders/Ports.scala
@@ -16,8 +16,8 @@ import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4EdgeParameters}
 import freechips.rocketchip.subsystem.{MemoryPortParams, MasterPortParams, SlavePortParams}
 import freechips.rocketchip.devices.debug.{ClockedDMIIO}
-import freechips.rocketchip.util.{HeterogeneousBag}
 import freechips.rocketchip.tilelink.{TLBundle}
+import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
 
 trait Port[T <: Data] {
   val getIO: () => T
diff --git a/generators/constellation b/generators/constellation
index 81f005ff..6664839b 160000
--- a/generators/constellation
+++ b/generators/constellation
@@ -1 +1 @@
-Subproject commit 81f005ffeac998ebf0619e0bd7f0d212d68a82c5
+Subproject commit 6664839b104a0d34adebfee13a0addc19efbde50
diff --git a/generators/diplomacy b/generators/diplomacy
new file mode 160000
index 00000000..edf37530
--- /dev/null
+++ b/generators/diplomacy
@@ -0,0 +1 @@
+Subproject commit edf375300d99a4c260a214d7c1553de0040771d7
diff --git a/generators/fft-generator b/generators/fft-generator
index 4e7e6cbb..490b975d 160000
--- a/generators/fft-generator
+++ b/generators/fft-generator
@@ -1 +1 @@
-Subproject commit 4e7e6cbbbc6ed96d27dbaeb2413764cd446c50b3
+Subproject commit 490b975d36f49632f05c29dd22bcd6e5f0e703ab
diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
index bd662a27..55089358 100644
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -15,7 +15,7 @@ import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import sifive.blocks.devices.uart._
 
-import testchipip.serdes.{ExternalSyncSerialIO}
+import testchipip.serdes.{ExternalSyncPhitIO}
 import testchipip.tsi.{SerialRAM}
 import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
 
@@ -69,7 +69,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
 class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
   case (th: FireSim, port: SerialTLPort, chipId: Int) => {
     port.io match {
-      case io: ExternalSyncSerialIO => {
+      case io: ExternalSyncPhitIO => {
         io.clock_in := th.harnessBinderClock
         val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module)
         ram.io.ser.in <> io.out
diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala
index 599788bc..aaee28a8 100644
--- a/generators/firechip/src/main/scala/FireSim.scala
+++ b/generators/firechip/src/main/scala/FireSim.scala
@@ -13,7 +13,7 @@ import org.chipsalliance.cde.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName}
 import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap}
 import freechips.rocketchip.tile.{RocketTile}
-import boom.common.{BoomTile}
+import boom.v3.common.{BoomTile}
 
 import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock, ResetPulseBridge, ResetPulseBridgeParameters}
 import midas.targetutils.{MemModelAnnotation, EnableModelMultiThreadingAnnotation}
@@ -112,10 +112,10 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta
           case b: BoomTile => {
             val core = b.module.core
             core.iregfile match {
-              case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
+              case irf: boom.v3.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
             }
             if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
-              case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
+              case frf: boom.v3.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
             }
           }
           case _ =>
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index 74d6c67e..3b116513 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -107,7 +107,10 @@ class WithFireSimDesignTweaks extends Config(
   // Optional: reduce the width of the Serial TL interface
   new testchipip.serdes.WithSerialTLWidth(4) ++
   // Required*: Scale default baud rate with periphery bus frequency
-  new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
+  new chipyard.config.WithUART(
+    baudrate=BigInt(3686400L), 
+    txEntries=256, rxEntries=256) ++        // FireSim requires a larger UART FIFO buffer, 
+  new chipyard.config.WithNoUART() ++       // so we overwrite the default one
   // Optional: Adds IO to attach tracerV bridges
   new chipyard.config.WithTraceIO ++
   // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 64 GiB on F1)
@@ -201,7 +204,7 @@ class WithFireSimTestChipConfigTweaks extends Config(
   new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
   new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
   new freechips.rocketchip.subsystem.WithRationalRocketTiles ++   // Add rational crossings between RocketTile and uncore
-  new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
+  new boom.v3.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
   new WithFireSimDesignTweaks
 )
 
@@ -264,8 +267,8 @@ class FireSimSmallSystemConfig extends Config(
   new WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
   new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(
-    client = Some(testchipip.serdes.SerialTLClientParams(idBits = 4)),
-    phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32)
+    client = Some(testchipip.serdes.SerialTLClientParams(totalIdBits = 4)),
+    phyParams = testchipip.serdes.ExternalSyncSerialPhyParams(phitWidth=32, flitWidth=32)
   ))) ++
   new testchipip.iceblk.WithBlockDevice ++
   new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
@@ -273,13 +276,13 @@ class FireSimSmallSystemConfig extends Config(
   new chipyard.RocketConfig)
 
 //*****************************************************************
-// Boom config, base off chipyard's LargeBoomConfig
+// Boom config, base off chipyard's LargeBoomV3Config
 //*****************************************************************
 class FireSimLargeBoomConfig extends Config(
   new WithDefaultFireSimBridges ++
   new WithDefaultMemModel ++
   new WithFireSimConfigTweaks ++
-  new chipyard.LargeBoomConfig)
+  new chipyard.LargeBoomV3Config)
 
 //********************************************************************
 // Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig
@@ -335,11 +338,11 @@ class FireSimCVA6Config extends Config(
 // - Requires MTModels and MCRams mixins as prefixes to the platform config
 // - May require larger build instances or JVM memory footprints
 //*********************************************************************************/
-class FireSim16LargeBoomConfig extends Config(
+class FireSim16LargeBoomV3Config extends Config(
   new WithDefaultFireSimBridges ++
   new WithDefaultMemModel ++
   new WithFireSimConfigTweaks ++
-  new boom.common.WithNLargeBooms(16) ++
+  new boom.v3.common.WithNLargeBooms(16) ++
   new chipyard.config.AbstractConfig)
 
 class FireSimNoMemPortConfig extends Config(
@@ -366,3 +369,10 @@ class FireSimRadianceClusterSynConfig extends Config(
     new WithDefaultMemModel ++
     new WithFireSimConfigTweaks ++
     new chipyard.RadianceClusterSynConfig)
+
+class FireSimLargeBoomCospikeConfig extends Config(
+  new firesim.firesim.WithCospikeBridge ++
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks++
+  new chipyard.LargeBoomV3Config)
diff --git a/generators/mempress b/generators/mempress
index c3d4901a..415f55b5 160000
--- a/generators/mempress
+++ b/generators/mempress
@@ -1 +1 @@
-Subproject commit c3d4901ab0f3c28bfd4101ffd62f707a86fc377e
+Subproject commit 415f55b583f3527500c5cf4e0a7b663982479098
diff --git a/generators/nvdla b/generators/nvdla
index 95697452..cfcb5faf 160000
--- a/generators/nvdla
+++ b/generators/nvdla
@@ -1 +1 @@
-Subproject commit 95697452e51ad56230a6e631bb02b3351c4293c6
+Subproject commit cfcb5fafcbf07035234a319622a0c4fa47ddef54
diff --git a/generators/radiance b/generators/radiance
index 3e0d87e1..e08bf2c2 160000
--- a/generators/radiance
+++ b/generators/radiance
@@ -1 +1 @@
-Subproject commit 3e0d87e1dd5eac5e3e101fc811d636801121bbde
+Subproject commit e08bf2c2c9a0294d1ccebc3dc867dd70d697b232
diff --git a/generators/rocc-acc-utils b/generators/rocc-acc-utils
index b001c888..9b8c5d37 160000
--- a/generators/rocc-acc-utils
+++ b/generators/rocc-acc-utils
@@ -1 +1 @@
-Subproject commit b001c888f9620189cd13d2c6ba19f1e28663a3cb
+Subproject commit 9b8c5d375fb89a3f4ff017e3b8933b63116382f6
diff --git a/generators/rocket-chip b/generators/rocket-chip
index 20ce83bf..8c8b3f5d 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit 20ce83bfc1e61ce25dada3e95ef20c8f2bb2a505
+Subproject commit 8c8b3f5dcf8cdc0166a030c75aa50c12578d5745
diff --git a/generators/rocket-chip-blocks b/generators/rocket-chip-blocks
index 3dddfe9f..2fc961f3 160000
--- a/generators/rocket-chip-blocks
+++ b/generators/rocket-chip-blocks
@@ -1 +1 @@
-Subproject commit 3dddfe9f5bcacf28aebcadb71d5b57f4f6df7e07
+Subproject commit 2fc961f356b1104a34567adeefa9e3666940643f
diff --git a/generators/sha3 b/generators/sha3
index 5e49347f..2d38585d 160000
--- a/generators/sha3
+++ b/generators/sha3
@@ -1 +1 @@
-Subproject commit 5e49347f069c72eeb3bf23f1a09170b3cfd3eb2e
+Subproject commit 2d38585d6410ca51ab19040fc23b1f6b3465270c
diff --git a/generators/shuttle b/generators/shuttle
index fd325d43..b75fada2 160000
--- a/generators/shuttle
+++ b/generators/shuttle
@@ -1 +1 @@
-Subproject commit fd325d43a162378dc1984e87297e6d710167db79
+Subproject commit b75fada257c576de5c9968dbbf5a09302b53b1de
diff --git a/generators/testchipip b/generators/testchipip
index d83fcccd..9b665a09 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit d83fcccda0a7c246a5adb76dfa7f738363d7fe5c
+Subproject commit 9b665a09da4bc5f1d30979b26968f82e4bbbc1c8
diff --git a/generators/tracegen/src/main/scala/Configs.scala b/generators/tracegen/src/main/scala/Configs.scala
index f51052c5..85fdf337 100644
--- a/generators/tracegen/src/main/scala/Configs.scala
+++ b/generators/tracegen/src/main/scala/Configs.scala
@@ -8,7 +8,6 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system.BaseConfig
 import freechips.rocketchip.rocket.DCacheParams
 import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
-import boom.lsu._
 import scala.math.{max, min}
 
 class WithTraceGen(
@@ -50,7 +49,7 @@ class WithTraceGen(
   case NumTiles => up(NumTiles) + n
 })
 
-class WithBoomTraceGen(
+class WithBoomV3TraceGen(
   n: Int = 2,
   overrideMemOffset: Option[BigInt] = None)(
   params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) },
@@ -61,8 +60,44 @@ class WithBoomTraceGen(
     val idOffset = up(NumTiles)
     val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
     params.zipWithIndex.map { case (dcp, i) =>
-      BoomTraceGenTileAttachParams(
-        tileParams = BoomTraceGenParams(
+      boom.v3.lsu.BoomTraceGenTileAttachParams(
+        tileParams = boom.v3.lsu.BoomTraceGenParams(
+          tileId = i + idOffset,
+          dcache = Some(dcp),
+          wordBits = site(XLen),
+          addrBits = 48,
+          addrBag = {
+            val nSets = dcp.nSets
+            val nWays = dcp.nWays
+            val blockOffset = site(SystemBusKey).blockOffset
+            val nBeats = site(SystemBusKey).blockBeats
+            List.tabulate(nWays) { i =>
+              Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) }
+            }.flatten
+          },
+          maxRequests = nReqs,
+          memStart = memOffset,
+          numGens = params.size),
+        crossingParams = RocketCrossingParams()
+      )
+    } ++ prev
+  }
+  case NumTiles => up(NumTiles) + n
+})
+
+class WithBoomV4TraceGen(
+  n: Int = 2,
+  overrideMemOffset: Option[BigInt] = None)(
+  params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) },
+  nReqs: Int = 8192
+) extends Config((site, here, up) => {
+  case TilesLocated(InSubsystem) => {
+    val prev = up(TilesLocated(InSubsystem), site)
+    val idOffset = up(NumTiles)
+    val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
+    params.zipWithIndex.map { case (dcp, i) =>
+      boom.v4.lsu.BoomTraceGenTileAttachParams(
+        tileParams = boom.v4.lsu.BoomTraceGenParams(
           tileId = i + idOffset,
           dcache = Some(dcp),
           wordBits = site(XLen),
diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala
index 488054d3..b1062cda 100644
--- a/generators/tracegen/src/main/scala/System.scala
+++ b/generators/tracegen/src/main/scala/System.scala
@@ -6,7 +6,6 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
 import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple, NullIntSyncSource, IntSyncXbar}
 import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile}
 import freechips.rocketchip.subsystem._
-import boom.lsu.BoomTraceGenTile
 
 class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
     with InstantiatesHierarchicalElements
@@ -20,10 +19,11 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
 
   val tileStatusNodes = totalTiles.values.toSeq.collect {
     case t: GroundTestTile => t.statusNode.makeSink()
-    case t: BoomTraceGenTile => t.statusNode.makeSink()
+    case t: boom.v3.lsu.BoomTraceGenTile => t.statusNode.makeSink()
+    case t: boom.v4.lsu.BoomTraceGenTile => t.statusNode.makeSink()
   }
 
-  lazy val fakeClockDomain = sbus.generateSynchronousDomain
+  lazy val fakeClockDomain = locateTLBusWrapper("sbus").generateSynchronousDomain
 
   lazy val clintOpt = None
   lazy val debugOpt = None
diff --git a/scripts/build-circt-from-source.sh b/scripts/build-circt-from-source.sh
new file mode 100755
index 00000000..d1afb6ab
--- /dev/null
+++ b/scripts/build-circt-from-source.sh
@@ -0,0 +1,104 @@
+#!/usr/bin/env bash
+
+# exit script if any command fails
+set -e
+set -o pipefail
+
+RDIR=$(git rev-parse --show-toplevel)
+
+# get helpful utilities
+source $RDIR/scripts/utils.sh
+
+common_setup
+
+# Allow user to override MAKE
+[ -n "${MAKE:+x}" ] || MAKE=$(command -v gnumake || command -v gmake || command -v make)
+readonly MAKE
+
+usage() {
+    echo "usage: ${0}"
+    echo ""
+    echo "Options"
+    echo "   --prefix -p PREFIX    : Install destination."
+    echo "   --help -h             : Display this message"
+    exit "$1"
+}
+
+PREFIX=""
+
+# getopts does not support long options, and is inflexible
+while [ "$1" != "" ];
+do
+    case $1 in
+        -h | -H | --help | help )
+            usage 3 ;;
+        -p | --prefix )
+            shift
+            PREFIX=$(realpath $1) ;;
+        * )
+            error "invalid option $1"
+            usage 1 ;;
+    esac
+    shift
+done
+
+if [ -z "$PREFIX" ] ; then
+    error "ERROR: Prefix not given."
+    exit 1
+fi
+
+
+
+echo "Cloning CIRCT"
+(
+    cd $RDIR/tools
+    git submodule update --init --progress circt
+)
+echo "Cloning CIRCT/LLVM"
+(
+    cd $RDIR/tools/circt
+    git submodule init
+    # The settings in circt/.gitmodules don't "stick", so force-set them here
+    git config submodule.llvm.shallow true
+    git config submodule.llvm.branch main
+    git submodule update --recommend-shallow --progress llvm
+)
+
+echo "Building CIRCT's LLVM/MLIR"
+(
+    cd $RDIR/tools/circt
+    rm -rf llvm/build
+    mkdir llvm/build
+    cd llvm/build
+    cmake -G Ninja ../llvm \
+	  -DLLVM_ENABLE_PROJECTS="mlir" \
+	  -DLLVM_TARGETS_TO_BUILD="host" \
+	  -DLLVM_ENABLE_ASSERTIONS=ON \
+	  -DCMAKE_BUILD_TYPE=RELEASE \
+	  -DCMAKE_EXPORT_COMPILE_COMMANDS=ON \
+	  -DCMAKE_EXE_LINKER_FLAGS="-L$RDIR/.conda-env/lib"
+    ninja
+)
+
+echo "Building CIRCT"
+(
+    cd $RDIR/tools/circt
+    rm -rf build
+    mkdir build
+    cd build
+    cmake -G Ninja .. \
+	  -DMLIR_DIR=$RDIR/tools/circt/llvm/build/lib/cmake/mlir \
+	  -DLLVM_DIR=$RDIR/tools/circt/llvm/build/lib/cmake/llvm \
+	  -DLLVM_ENABLE_ASSERTIONS=ON \
+	  -DCMAKE_BUILD_TYPE=RELEASE \
+	  -DCMAKE_INSTALL_PREFIX=$PREFIX \
+	  -DCMAKE_EXE_LINKER_FLAGS="-L$RDIR/.conda-env/lib"
+    ninja
+)
+
+echo "Installing CIRCT to $PREFIX"
+(
+    cd $RDIR/tools/circt/build
+    ninja install
+)
+
diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh
index ffcee96b..56f56506 100755
--- a/scripts/build-setup.sh
+++ b/scripts/build-setup.sh
@@ -39,6 +39,7 @@ usage() {
     echo "  --verbose -v            : Verbose printout"
     echo "  --use-unpinned-deps -ud : Use unpinned conda environment"
     echo "  --use-lean-conda        : Install a leaner version of the repository (Smaller conda env, no FireSim, no FireMarshal)"
+    echo "  --build-circt           : Builds CIRCT from source, instead of downloading the precompiled binary"
 
     echo "  --skip -s N             : Skip step N in the list above. Use multiple times to skip multiple steps ('-s N -s M ...')."
     echo "  --skip-conda            : Skip Conda initialization (step 1)"
@@ -60,6 +61,7 @@ VERBOSE_FLAG=""
 USE_UNPINNED_DEPS=false
 USE_LEAN_CONDA=false
 SKIP_LIST=()
+BUILD_CIRCT=false
 
 # getopts does not support long options, and is inflexible
 while [ "$1" != "" ];
@@ -75,6 +77,8 @@ do
         --use-lean-conda)
             USE_LEAN_CONDA=true
             SKIP_LIST+=(4 6 7 8 9) ;;
+        --build-circt)
+            BUILD_CIRCT=true ;;
         -ud | --use-unpinned-deps )
             USE_UNPINNED_DEPS=true ;;
         --skip | -s)
@@ -306,13 +310,20 @@ if run_step "10"; then
         PREFIX=$RISCV
     fi
 
-    git submodule update --init $CYDIR/tools/install-circt &&
-    $CYDIR/tools/install-circt/bin/download-release-or-nightly-circt.sh \
-        -f circt-full-shared-linux-x64.tar.gz \
-        -i $PREFIX \
-        -v version-file \
-        -x $CYDIR/conda-reqs/circt.json \
-        -g null
+    if [ "$BUILD_CIRCT" = true ] ; then
+	echo "Building CIRCT from source, and installing to $PREFIX"
+	$CYDIR/scripts/build-circt-from-source.sh --prefix $PREFIX
+    else
+	echo "Downloading CIRCT from nightly build"
+
+	git submodule update --init $CYDIR/tools/install-circt &&
+	    $CYDIR/tools/install-circt/bin/download-release-or-nightly-circt.sh \
+		-f circt-full-static-linux-x64.tar.gz \
+		-i $PREFIX \
+		-v version-file \
+		-x $CYDIR/conda-reqs/circt.json \
+		-g null
+    fi
     exit_if_last_command_failed
 fi
 
diff --git a/scripts/build-toolchain-extra.sh b/scripts/build-toolchain-extra.sh
index 28cc9dfa..4e7b29c6 100755
--- a/scripts/build-toolchain-extra.sh
+++ b/scripts/build-toolchain-extra.sh
@@ -84,7 +84,7 @@ cp -p "${SRCDIR}/riscv-isa-sim/build/libfesvr.a" "${RISCV}/lib/"
 CLEANAFTERINSTALL=$OLDCLEANAFTERINSTALL
 
 echo '==>  Installing Proxy Kernel'
-CC= CXX= module_all riscv-pk --prefix="${RISCV}" --host=riscv${XLEN}-unknown-elf
+CC= CXX= module_all riscv-pk --prefix="${RISCV}" --host=riscv${XLEN}-unknown-elf --with-arch=rv64gc_zifencei
 
 echo '==>  Installing RISC-V tests'
 module_all riscv-tests --prefix="${RISCV}/riscv${XLEN}-unknown-elf" --with-xlen=${XLEN}
@@ -115,6 +115,7 @@ echo '==>  Installing DRAMSim2 Shared Library'
 cd $RDIR
 git submodule update --init tools/DRAMSim2
 cd tools/DRAMSim2
+make clean
 make libdramsim.so
 cp libdramsim.so $RISCV/lib/
 
diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh
index 1779b8d8..e46af0ca 100755
--- a/scripts/init-submodules-no-riscv-tools-nolog.sh
+++ b/scripts/init-submodules-no-riscv-tools-nolog.sh
@@ -82,6 +82,7 @@ cd "$RDIR"
             software/spec2017 \
             tools/dsptools \
             tools/rocket-dsp-utils \
+            tools/circt \
             vlsi/hammer-mentor-plugins
         do
             "$1" "${name%/}"
diff --git a/scripts/insert-includes.py b/scripts/insert-includes.py
index 8262c251..b939878a 100755
--- a/scripts/insert-includes.py
+++ b/scripts/insert-includes.py
@@ -34,13 +34,15 @@ def process(inF, outF):
             # for each include found, search through all dirs and replace if found, error if not
             for num, line in enumerate(inFile, 1):
                 match = re.match(r"^ *`include +\"(.*)\"", line)
-                if match:
+                if match and match.group(1) != "uvm_macros.svh":
+                    print("[INFO] Replacing includes for {}".format(match.group(1)))
                     # search for include and replace
                     found = False
                     for d in incDirs:
                         potentialIncFileName = d + "/" + match.group(1)
                         if os.path.exists(potentialIncFileName):
                             found = True
+                            print("[INFO] Found missing include in {}".format(potentialIncFileName))
                             with open(potentialIncFileName, 'r') as incFile:
                                 for iline in incFile:
                                     outFile.write(iline)
diff --git a/scripts/uniquify-module-names.py b/scripts/uniquify-module-names.py
index 0ddea49f..d2131c33 100755
--- a/scripts/uniquify-module-names.py
+++ b/scripts/uniquify-module-names.py
@@ -110,7 +110,7 @@ def generate_copy(c, sfx):
   new_file = os.path.join(args.gcpath, new_file)
 
   shutil.copy(cur_file, new_file)
-  bash(f"{SED} -i 's/module\( \+\){cur_name}/module\\1{new_name}/' {new_file}")
+  bash(rf"{SED} -i 's/module\( \+\){cur_name}/module\1{new_name}/' {new_file}")
   return new_file
 
 def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename):
@@ -137,7 +137,7 @@ def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename):
         new_file = generate_copy(cur_file, MODEL_SFX)
         if parent is not None and ((parent, mod) not in updated_submodule):
           parent_file = os.path.join(args.gcpath, verilog_module_filename[parent])
-          bash(f"{SED} -i 's/\( \*\){mod}\( \+\)/\\1{mod}_{MODEL_SFX}\\2/' {parent_file}")
+          bash(rf"{SED} -i 's/\( \*\){mod}\( \+\)/\1{mod}_{MODEL_SFX}\2/' {parent_file}")
           updated_submodule.add((parent, mod))
 
         # add the uniquified module to the verilog_modul_filename dict
diff --git a/sims/firesim b/sims/firesim
index 535dcdc2..ac8bcd8b 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit 535dcdc29a930525e771f083f2b1c688884c6871
+Subproject commit ac8bcd8b349d89637750fb20e77545818df4ff2d
diff --git a/sims/vcs/vcs.mk b/sims/vcs/vcs.mk
index 68b9aa71..9913481c 100644
--- a/sims/vcs/vcs.mk
+++ b/sims/vcs/vcs.mk
@@ -54,7 +54,9 @@ VCS_NONCC_OPTS = \
 	-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
 	+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
 	-debug_pp \
-	+incdir+$(GEN_COLLATERAL_DIR)
+	-top $(TB) \
+	+incdir+$(GEN_COLLATERAL_DIR) \
+	$(addprefix +incdir+,$(EXT_INCDIRS))
 
 VCS_PREPROC_DEFINES = \
 	+define+VCS
diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile
index e1cf31ef..d90c4c38 100644
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -155,6 +155,7 @@ VERILATOR_NONCC_OPTS = \
 	-I$(GEN_COLLATERAL_DIR) \
 	--top-module $(TB) \
 	--vpi \
+	$(addprefix +incdir+,$(EXT_INCDIRS)) \
 	-f $(sim_common_files)
 
 #----------------------------------------------------------------------------------------
diff --git a/software/firemarshal b/software/firemarshal
index b014183a..a98f1faf 160000
--- a/software/firemarshal
+++ b/software/firemarshal
@@ -1 +1 @@
-Subproject commit b014183ac6afed7fe1aca89fa010be8d13ad4079
+Subproject commit a98f1faff6d11a0b4418d3a814cabd51c734c822
diff --git a/tests/hello.c b/tests/hello.c
index 626cd930..15398697 100644
--- a/tests/hello.c
+++ b/tests/hello.c
@@ -1,6 +1,7 @@
 #include <stdio.h>
 #include <riscv-pk/encoding.h>
 #include "marchid.h"
+#include <stdint.h>
 
 int main(void) {
   uint64_t marchid = read_csr(marchid);
diff --git a/tests/symmetric.c b/tests/symmetric.c
index a6d37627..d9f2917f 100644
--- a/tests/symmetric.c
+++ b/tests/symmetric.c
@@ -1,5 +1,6 @@
 #include <stdio.h>
 #include <string.h>
+#include <stdlib.h>
 #include <riscv-pk/encoding.h>
 #include "marchid.h"
 
@@ -20,10 +21,13 @@ int main(void) {
   memcpy(test, dest + OBUS_OFFSET, sizeof(src));
   size_t read_end = rdcycle();
 
-  if (memcmp(src, test, sizeof(src))) {
-    printf("Remote write/read failed\n");
-    exit(1);
+  for (int i = 0; i < sizeof(src); i++) {
+    if (src[i] != test[i]) {
+      printf("Remote write/read failed at %p %p %p %x %x\n", src+i, test+i, dest + OBUS_OFFSET + i, src[i], test[i]);
+      exit(1);
+    }
   }
+
   printf("Read %ld bytes in %ld cycles\n", sizeof(src), read_end - read_start);
 
   return 0;
diff --git a/toolchains/libgloss b/toolchains/libgloss
index 0ecdf7fa..39234a16 160000
--- a/toolchains/libgloss
+++ b/toolchains/libgloss
@@ -1 +1 @@
-Subproject commit 0ecdf7fa08c9e40f9d60903b8189511beb8555ab
+Subproject commit 39234a16247ab1fa234821b251f1f1870c3de343
diff --git a/toolchains/riscv-tools/riscv-spike-devices b/toolchains/riscv-tools/riscv-spike-devices
index 8b4836db..39a0993b 160000
--- a/toolchains/riscv-tools/riscv-spike-devices
+++ b/toolchains/riscv-tools/riscv-spike-devices
@@ -1 +1 @@
-Subproject commit 8b4836db0b5b4ed0a9bab34e7707fe40c7c014be
+Subproject commit 39a0993b20346215c8c672e083519f02d23af67c
diff --git a/toolchains/riscv-tools/riscv-tools-feedstock b/toolchains/riscv-tools/riscv-tools-feedstock
index 917b56ef..56c29e01 160000
--- a/toolchains/riscv-tools/riscv-tools-feedstock
+++ b/toolchains/riscv-tools/riscv-tools-feedstock
@@ -1 +1 @@
-Subproject commit 917b56ef1a78871be22283ecdb01658ac11cbe61
+Subproject commit 56c29e01ba3e705c563edd1271a387119bddb5a5
diff --git a/tools/circt b/tools/circt
new file mode 160000
index 00000000..9e0c1696
--- /dev/null
+++ b/tools/circt
@@ -0,0 +1 @@
+Subproject commit 9e0c1696f3caef4059c65774ad6b8efee91d9d9e
diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils
index 272cee3c..24bf9a27 160000
--- a/tools/rocket-dsp-utils
+++ b/tools/rocket-dsp-utils
@@ -1 +1 @@
-Subproject commit 272cee3c83a31a7496b8f2e933290798e2fb5cac
+Subproject commit 24bf9a27a8fe565392f1a6aa3e53fdbe92a64dbc
diff --git a/variables.mk b/variables.mk
index b4d70c1f..55dacd04 100644
--- a/variables.mk
+++ b/variables.mk
@@ -27,6 +27,7 @@ HELP_SIMULATION_VARIABLES = \
 "   BINARY                 = riscv elf binary that the simulator will run when using the run-binary* targets" \
 "   BINARIES               = list of riscv elf binary that the simulator will run when using the run-binaries* targets" \
 "   BINARIES_DIR           = directory of riscv elf binaries that the simulator will run when using the run-binaries* targets" \
+"   BINARY_ARGS            = arguments to pass to each binary in run-binary targets (primarily meant for pk arguments)" \
 "   LOADMEM                = riscv elf binary that should be loaded directly into simulated DRAM. LOADMEM=1 will load the BINARY elf" \
 "   LOADARCH               = path to a architectural checkpoint directory that should end in .loadarch/, for restoring from a checkpoint" \
 "   VERBOSE_FLAGS          = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" \
@@ -224,6 +225,12 @@ BB_MODS_FILELIST ?= $(build_dir)/$(long_name).bb.f
 # all module files to include (top, model, bb included)
 ALL_MODS_FILELIST ?= $(build_dir)/$(long_name).all.f
 
+# external filelists. Users, or project-supplied make fragments can append filelists
+# with absolute paths here
+EXT_FILELISTS ?=
+# external verilog incdirs. Users, or project-supplied make fragments can append to this
+EXT_INCDIRS ?=
+
 BOOTROM_FILES   ?= bootrom.rv64.img bootrom.rv32.img bootrom.radiance.rv32.img
 BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES))
 
@@ -291,6 +298,7 @@ PERMISSIVE_ON=+permissive
 PERMISSIVE_OFF=+permissive-off
 BINARY ?=
 BINARIES ?=
+BINARY_ARGS ?=
 override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(TIMEOUT_CYCLES)
 VERBOSE_FLAGS ?= +verbose
 # get_out_name is a function, 1st argument is the binary
diff --git a/vlsi/Makefile b/vlsi/Makefile
index 14feb6fb..ef9e2282 100644
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -72,7 +72,7 @@ VLSI_RTL = $(build_dir)/syn.f
 ifneq ($(CUSTOM_VLOG), )
 	RTL_DEPS = $(CUSTOM_VLOG)
 else
-	RTL_DEPS = $(TOP_MODS_FILELIST) $(TOP_SMEMS_FILE)
+	RTL_DEPS = $(TOP_MODS_FILELIST) $(TOP_SMEMS_FILE) $(EXT_FILELISTS)
 endif
 
 $(VLSI_RTL): $(RTL_DEPS)
@@ -82,6 +82,9 @@ ifneq ($(CUSTOM_VLOG), )
 else
 	cat $(TOP_MODS_FILELIST) | sort -u > $(VLSI_RTL)
 	echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL)
+ifneq ($(EXT_FILELISTS),)
+	cat $(EXT_FILELISTS) >> $(VLSI_RTL)
+endif
 endif
 
 #########################################################################################