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Bump to latest rocket-chip/chisel3.5.6

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This commit is contained in:
Jerry Zhao
2023-03-20 23:26:53 -07:00
parent 7475bfb1a0
commit df2e5ad9dc
93 changed files with 106 additions and 119 deletions
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4
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -6,9 +6,9 @@ import chisel3._
import chisel3.experimental.annotate
import chisel3.util.experimental.BoringUtils
import freechips.rocketchip.config.{Field, Config, Parameters}
import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebug}
import freechips.rocketchip.amba.axi4.{AXI4Bundle}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tile.{RocketTile}

2
generators/firechip/src/main/scala/FireSim.scala
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@@ -9,7 +9,7 @@ import chisel3.experimental.{IO}
import freechips.rocketchip.prci._
import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
import freechips.rocketchip.config.{Field, Config, Parameters}
import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName}
import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap}

2
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -4,7 +4,7 @@ import java.io.File
import chisel3._
import chisel3.util.{log2Up}
import freechips.rocketchip.config.{Parameters, Config}
import org.chipsalliance.cde.config.{Parameters, Config}
import freechips.rocketchip.groundtest.TraceGenParams
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._