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Bump to latest rocket-chip/chisel3.5.6

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This commit is contained in:
Jerry Zhao
2023-03-20 23:26:53 -07:00
parent 7475bfb1a0
commit df2e5ad9dc
93 changed files with 106 additions and 119 deletions
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2
generators/boom

Submodule generators/boom updated: deae9f7046...0101e2041d

2
generators/chipyard/src/main/scala/ChipTop.scala
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@@ -6,7 +6,7 @@ import scala.collection.mutable.{ArrayBuffer}
import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup}
import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
import freechips.rocketchip.config.{Parameters, Field}
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}
import freechips.rocketchip.util.{ResetCatchAndSync}
import chipyard.iobinders._

2
generators/chipyard/src/main/scala/Cospike.scala
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@@ -4,7 +4,7 @@ import chisel3._
import chisel3.experimental.{IntParam, StringParam, IO}
import chisel3.util._
import freechips.rocketchip.config.{Parameters, Field, Config}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.devices.tilelink._

2
generators/chipyard/src/main/scala/DigitalTop.scala
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@@ -4,7 +4,7 @@ import chisel3._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system._
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.devices.tilelink._
// ------------------------------------

2
generators/chipyard/src/main/scala/HarnessBinders.scala
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@@ -4,7 +4,7 @@ import chisel3._
import chisel3.util._
import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction}
import freechips.rocketchip.config.{Field, Config, Parameters}
import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
import freechips.rocketchip.devices.debug._

4
generators/chipyard/src/main/scala/IOBinders.scala
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@@ -3,7 +3,7 @@ package chipyard.iobinders
import chisel3._
import chisel3.experimental.{Analog, IO, DataMirror}
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.jtag.{JTAGIO}
@@ -219,7 +219,7 @@ class WithDebugIOCells extends OverrideLazyIOBinder({
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody { system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripheryDebugModuleImp => {
InModuleBody { system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripheryDebug => {
system.debug.map({ debug =>
// We never use the PSDIO, so tie it off on-chip
system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) }

2
generators/chipyard/src/main/scala/SpikeTile.scala
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@@ -4,7 +4,7 @@ import chisel3._
import chisel3.util._
import chisel3.experimental.{IntParam, StringParam, IO}
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._

5
generators/chipyard/src/main/scala/Subsystem.scala
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@@ -9,9 +9,9 @@ import chisel3._
import chisel3.internal.sourceinfo.{SourceInfo}
import freechips.rocketchip.prci._
import freechips.rocketchip.config.{Field, Parameters}
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey}
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, ExportDebug, DebugModuleKey}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
@@ -47,6 +47,7 @@ trait CanHaveHTIF { this: BaseSubsystem =>
class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
with HasTiles
with HasPeripheryDebug
with CanHaveHTIF
{
def coreMonitorBundles = tiles.map {

2
generators/chipyard/src/main/scala/System.scala
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@@ -7,7 +7,7 @@ package chipyard
import chisel3._
import freechips.rocketchip.config.{Parameters, Field}
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._

2
generators/chipyard/src/main/scala/TestHarness.scala
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@@ -4,7 +4,7 @@ import chisel3._
import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.config.{Field, Parameters}
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util.{ResetCatchAndSync}
import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters}

2
generators/chipyard/src/main/scala/TestSuites.scala
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@@ -4,7 +4,7 @@ import scala.collection.mutable.{LinkedHashSet}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tile.{XLen, TileParams}
import freechips.rocketchip.config.{Parameters, Field, Config}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
/**

2
generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
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@@ -4,7 +4,7 @@ import chisel3._
import chisel3.util._
import chisel3.experimental.{Analog, IO}
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._

2
generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala
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@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._
import freechips.rocketchip.config.{Parameters, Config, Field}
import org.chipsalliance.cde.config.{Parameters, Config, Field}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._

2
generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
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@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._
import freechips.rocketchip.config.{Parameters}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
import freechips.rocketchip.util.ElaborationArtefacts

2
generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
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@@ -4,7 +4,7 @@ import chisel3._
import scala.collection.mutable.{ArrayBuffer}
import freechips.rocketchip.config.{Parameters, Field, Config}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._

2
generators/chipyard/src/main/scala/clocking/TileClockGater.scala
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@@ -4,7 +4,7 @@ import chisel3._
import chisel3.util._
import chisel3.experimental.{Analog, IO}
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._

2
generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
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@@ -4,7 +4,7 @@ import chisel3._
import chisel3.util._
import chisel3.experimental.{Analog, IO}
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._

2
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -1,6 +1,6 @@
package chipyard.config
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
// --------------
// Chipyard abstract ("base") configuration

2
generators/chipyard/src/main/scala/config/BoomConfigs.scala
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@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
// ---------------------
// BOOM Configs

2
generators/chipyard/src/main/scala/config/CVA6Configs.scala
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@@ -2,7 +2,7 @@ package chipyard
import chisel3._
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
// ---------------------
// CVA6 Configs

2
generators/chipyard/src/main/scala/config/HeteroConfigs.scala
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@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
// ---------------------
// Heterogenous Configs

2
generators/chipyard/src/main/scala/config/IbexConfigs.scala
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@@ -2,7 +2,7 @@ package chipyard
import chisel3._
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
// ---------------------
// Ibex Configs

2
generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
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@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// ------------------------------

2
generators/chipyard/src/main/scala/config/NoCConfigs.scala
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@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
import freechips.rocketchip.subsystem.{SBUS, MBUS}

2
generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
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@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
// A empty config with no cores. Useful for testing
class NoCoresConfig extends Config(

2
generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
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@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// ---------------------------------------------------------

2
generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
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@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// ------------------------------

2
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// --------------

2
generators/chipyard/src/main/scala/config/RocketSha3Configs.scala
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@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// --------------

2
generators/chipyard/src/main/scala/config/SodorConfigs.scala
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@@ -2,7 +2,7 @@ package chipyard
import chisel3._
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
class Sodor1StageConfig extends Config(
// Create a Sodor 1-stage core

2
generators/chipyard/src/main/scala/config/SpikeConfigs.scala
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@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
// Configs which instantiate a Spike-simulated
// tile that interacts with the Chipyard SoC

2
generators/chipyard/src/main/scala/config/TracegenConfigs.scala
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@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.rocket.{DCacheParams}
class AbstractTraceGenConfig extends Config(

2
generators/chipyard/src/main/scala/config/TutorialConfigs.scala
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@@ -1,6 +1,6 @@
package chipyard
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import constellation.channel._
import constellation.routing._
import constellation.topology._

2
generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
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@@ -4,7 +4,7 @@ import scala.util.matching.Regex
import chisel3._
import chisel3.util.{log2Up}
import freechips.rocketchip.config.{Field, Parameters, Config}
import org.chipsalliance.cde.config.{Field, Parameters, Config}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.prci._
import freechips.rocketchip.diplomacy._

2
generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
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@@ -4,7 +4,7 @@ import scala.util.matching.Regex
import chisel3._
import chisel3.util.{log2Up}
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey}
import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI}
import freechips.rocketchip.stage.phases.TargetDirKey

2
generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
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@@ -2,7 +2,7 @@ package chipyard.config
import chisel3._
import freechips.rocketchip.config.{Field, Parameters, Config}
import org.chipsalliance.cde.config.{Field, Parameters, Config}
import freechips.rocketchip.tile._
import freechips.rocketchip.diplomacy._

2
generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
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@@ -1,6 +1,6 @@
package chipyard.config
import freechips.rocketchip.config.{Config}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper}
import freechips.rocketchip.diplomacy.{DTSTimebase}

2
generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
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@@ -2,7 +2,7 @@ package chipyard.config
import chisel3._
import freechips.rocketchip.config.{Field, Parameters, Config}
import org.chipsalliance.cde.config.{Field, Parameters, Config}
import freechips.rocketchip.tile._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}

2
generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala
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@@ -1,6 +1,6 @@
package chipyard.config
import freechips.rocketchip.config.{Config, Field, Parameters}
import org.chipsalliance.cde.config.{Config, Field, Parameters}
import tracegen.{TraceGenSystem}
import chipyard.{BuildSystem}
import chipyard.clocking.{HasChipyardPRCI}

2
generators/chipyard/src/main/scala/example/GCD.scala
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@@ -5,7 +5,7 @@ import chisel3.util._
import chisel3.experimental.{IntParam, BaseModule}
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.config.{Parameters, Field, Config}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper.{HasRegMap, RegField}
import freechips.rocketchip.tilelink._

2
generators/chipyard/src/main/scala/example/InitZero.scala
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@@ -3,7 +3,7 @@ package chipyard.example
import chisel3._
import chisel3.util._
import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
import freechips.rocketchip.config.{Parameters, Field, Config}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}
import freechips.rocketchip.tilelink._

2
generators/chipyard/src/main/scala/example/NodeTypes.scala
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@@ -1,6 +1,6 @@
package chipyard.example
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._

2
generators/chipyard/src/main/scala/example/RegisterNodeExample.scala
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@@ -2,7 +2,7 @@
import chisel3._
import chisel3.util._
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink.TLRegisterNode

2
generators/chipyard/src/main/scala/example/TutorialTile.scala
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@@ -3,7 +3,7 @@ package chipyard.example
import chisel3._
import chisel3.util._
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._

2
generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala
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@@ -5,7 +5,7 @@ import chisel3.util._
import dspblocks._
import dsptools.numbers._
import freechips.rocketchip.amba.axi4stream._
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._

2
generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
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@@ -8,7 +8,7 @@ import chisel3.util._
import dspblocks._
import dsptools.numbers._
import freechips.rocketchip.amba.axi4stream._
import freechips.rocketchip.config.{Parameters, Field, Config}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.subsystem._

2
generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
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@@ -8,7 +8,7 @@ import chisel3.util._
import dspblocks._
import dsptools.numbers._
import freechips.rocketchip.amba.axi4stream._
import freechips.rocketchip.config.{Parameters, Field, Config}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.subsystem._

2
generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala
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@@ -6,7 +6,7 @@ package chipyard.stage.phases
import scala.util.Try
import scala.collection.mutable
import chipsalliance.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import chisel3.stage.phases.Elaborate
import firrtl.AnnotationSeq
import firrtl.annotations.{Annotation, NoTargetAnnotation}

2
generators/chipyard/src/main/scala/unittest/TestHarness.scala
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@@ -1,7 +1,7 @@
package chipyard.unittest
import chisel3._
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
class TestHarness(implicit val p: Parameters) extends Module {
val io = IO(new Bundle { val success = Output(Bool()) })

2
generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala
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@@ -1,6 +1,6 @@
package chipyard.unittest
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.{ElaborationArtefacts, PlusArgArtefacts}
class UnitTestSuite(implicit p: Parameters) extends freechips.rocketchip.unittest.UnitTestSuite {

2
generators/constellation

Submodule generators/constellation updated: 4606ee19b7...e9f1c828ca

2
generators/cva6

Submodule generators/cva6 updated: 737fd83b82...0011494bb7

2
generators/fft-generator

Submodule generators/fft-generator updated: a31bd038dd...be8ab768bd

4
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -6,9 +6,9 @@ import chisel3._
import chisel3.experimental.annotate
import chisel3.util.experimental.BoringUtils
import freechips.rocketchip.config.{Field, Config, Parameters}
import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebug}
import freechips.rocketchip.amba.axi4.{AXI4Bundle}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tile.{RocketTile}

2
generators/firechip/src/main/scala/FireSim.scala
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@@ -9,7 +9,7 @@ import chisel3.experimental.{IO}
import freechips.rocketchip.prci._
import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
import freechips.rocketchip.config.{Field, Config, Parameters}
import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName}
import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap}

2
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -4,7 +4,7 @@ import java.io.File
import chisel3._
import chisel3.util.{log2Up}
import freechips.rocketchip.config.{Parameters, Config}
import org.chipsalliance.cde.config.{Parameters, Config}
import freechips.rocketchip.groundtest.TraceGenParams
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._

2
generators/gemmini

Submodule generators/gemmini updated: 686cb15dad...11e15ab1c5

2
generators/hwacha

Submodule generators/hwacha updated: e1be8e2a41...d01ca1e7f8

2
generators/ibex

Submodule generators/ibex updated: 626127f229...916fb7a6ff

2
generators/icenet

Submodule generators/icenet updated: 90d52a6a84...ce1ec55c1f

2
generators/mempress

Submodule generators/mempress updated: b9eaedc061...295ae0854a

2
generators/nvdla

Submodule generators/nvdla updated: 2b17011b26...7130a5c0f7

2
generators/riscv-sodor

Submodule generators/riscv-sodor updated: d6ccc5de5c...c051956d3b

2
generators/rocket-chip

Submodule generators/rocket-chip updated: f5ebf26b36...4fbd2f238d

2
generators/sha3

Submodule generators/sha3 updated: 8c5d244303...1fa5ef8ae5

2
generators/sifive-blocks

Submodule generators/sifive-blocks updated: 4273925fdd...19d42938f2

2
generators/sifive-cache

Submodule generators/sifive-cache updated: 850e12154c...65f8bc26b2

2
generators/testchipip

Submodule generators/testchipip updated: dead693f8f...ee47d2ea20

2
generators/tracegen/src/main/scala/Configs.scala
View File

@@ -2,7 +2,7 @@ package tracegen
import chisel3._
import chisel3.util.log2Ceil
import freechips.rocketchip.config.{Config, Parameters}
import org.chipsalliance.cde.config.{Config, Parameters}
import freechips.rocketchip.groundtest.{TraceGenParams, TraceGenTileAttachParams}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system.BaseConfig

5
generators/tracegen/src/main/scala/System.scala
View File

@@ -1,9 +1,9 @@
package tracegen
import chisel3._
import freechips.rocketchip.config.{Field, Parameters}
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple}
import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple, NullIntSyncSource}
import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile}
import freechips.rocketchip.subsystem._
import boom.lsu.BoomTraceGenTile
@@ -17,6 +17,7 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
case t: GroundTestTile => t.statusNode.makeSink()
case t: BoomTraceGenTile => t.statusNode.makeSink()
}
val debugNode = NullIntSyncSource()
override lazy val module = new TraceGenSystemModuleImp(this)
}