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Bump to latest rocket-chip/chisel3.5.6

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This commit is contained in:
Jerry Zhao
2023-03-20 23:26:53 -07:00
parent 7475bfb1a0
commit df2e5ad9dc
93 changed files with 106 additions and 119 deletions
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2
fpga/src/main/scala/arty100t/Configs.scala
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@@ -1,7 +1,7 @@
// See LICENSE for license details.
package chipyard.fpga.arty100t
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._

2
fpga/src/main/scala/arty100t/Harness.scala
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@@ -3,7 +3,7 @@ package chipyard.fpga.arty100t
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.config.{Parameters}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tilelink.{TLClientNode, TLBlockDuringReset}
import sifive.fpgashells.shell.xilinx._

1
fpga/src/main/scala/arty100t/HarnessBinders.scala
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@@ -2,7 +2,6 @@ package chipyard.fpga.arty100t
import chisel3._
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem.{PeripheryBusKey}
import freechips.rocketchip.tilelink.{TLBundle}