Bump to latest rocket-chip/chisel3.5.6

2023-03-20 23:26:53 -07:00
parent 7475bfb1a0
commit df2e5ad9dc
93 changed files with 106 additions and 119 deletions
--- a/fpga/src/main/scala/arty/TestHarness.scala
+++ b/fpga/src/main/scala/arty/TestHarness.scala
@@ -3,7 +3,7 @@ package chipyard.fpga.arty
 import chisel3._

 import freechips.rocketchip.diplomacy.{LazyModule}
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}

 import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}