wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Bump to latest rocket-chip/chisel3.5.6

Browse Source
This commit is contained in:
Jerry Zhao
2023-03-20 23:26:53 -07:00
parent 7475bfb1a0
commit df2e5ad9dc
93 changed files with 106 additions and 119 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
fpga/src/main/scala/arty/HarnessBinders.scala
View File

@@ -2,7 +2,7 @@ package chipyard.fpga.arty
import chisel3._
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
import freechips.rocketchip.jtag.{JTAGIO}
import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp}
@@ -15,7 +15,7 @@ import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
import chipyard.iobinders.JTAGChipIO
class WithArtyResetHarnessBinder extends ComposeHarnessBinder({
(system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => {
(system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Bool]) => {
require(ports.size == 2)
withClockAndReset(th.clock_32MHz, th.ck_rst) {