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Bump to latest rocket-chip/chisel3.5.6

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This commit is contained in:
Jerry Zhao
2023-03-20 23:26:53 -07:00
parent 7475bfb1a0
commit df2e5ad9dc
93 changed files with 106 additions and 119 deletions
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2
fpga/src/main/scala/arty/Configs.scala
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@@ -1,7 +1,7 @@
// See LICENSE for license details.
package chipyard.fpga.arty
import freechips.rocketchip.config._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._

4
fpga/src/main/scala/arty/HarnessBinders.scala
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@@ -2,7 +2,7 @@ package chipyard.fpga.arty
import chisel3._
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
import freechips.rocketchip.jtag.{JTAGIO}
import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp}
@@ -15,7 +15,7 @@ import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
import chipyard.iobinders.JTAGChipIO
class WithArtyResetHarnessBinder extends ComposeHarnessBinder({
(system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => {
(system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Bool]) => {
require(ports.size == 2)
withClockAndReset(th.clock_32MHz, th.ck_rst) {

4
fpga/src/main/scala/arty/IOBinders.scala
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@@ -3,12 +3,12 @@ package chipyard.fpga.arty
import chisel3._
import chisel3.experimental.{IO}
import freechips.rocketchip.devices.debug.{HasPeripheryDebugModuleImp}
import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
import chipyard.iobinders.{ComposeIOBinder}
class WithDebugResetPassthrough extends ComposeIOBinder({
(system: HasPeripheryDebugModuleImp) => {
(system: HasPeripheryDebug) => {
// Debug module reset
val io_ndreset: Bool = IO(Output(Bool())).suggestName("ndreset")
io_ndreset := system.debug.get.ndreset

2
fpga/src/main/scala/arty/TestHarness.scala
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@@ -3,7 +3,7 @@ package chipyard.fpga.arty
import chisel3._
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.config.{Parameters}
import org.chipsalliance.cde.config.{Parameters}
import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}