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Add build of ChipLikeQuadRocketConfig to CI

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This commit is contained in:
Jerry Zhao
2023-04-08 14:56:36 -07:00
parent b88e1025e4
commit de293f5fdf
5 changed files with 9 additions and 8 deletions
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3
.github/scripts/defaults.sh vendored
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@@ -29,7 +29,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
# key value store to get the build groups # key value store to get the build groups
declare -A grouping declare -A grouping
grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone" grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals" grouping["group-peripherals"]="chipyard-dmirocket chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike"
grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels" grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels"
grouping["group-constellation"]="chipyard-constellation" grouping["group-constellation"]="chipyard-constellation"
grouping["group-tracegen"]="tracegen tracegen-boom" grouping["group-tracegen"]="tracegen tracegen-boom"
@@ -53,6 +53,7 @@ mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
mapping["chipyard-ibex"]=" CONFIG=IbexConfig" mapping["chipyard-ibex"]=" CONFIG=IbexConfig"
mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'" mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'" mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
mapping["chipyard-chiplike"]=" CONFIG=ChipLikeQuadRocketConfig verilog"
mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog" mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog"
mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog" mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"
mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config" mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"

2
generators/chipyard/src/main/scala/HarnessClocks.scala
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@@ -4,7 +4,7 @@ import chisel3._
import scala.collection.mutable.{ArrayBuffer, LinkedHashMap} import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.config.{Field, Parameters, Config} import org.chipsalliance.cde.config.{Field, Parameters, Config}
import freechips.rocketchip.util.{ResetCatchAndSync} import freechips.rocketchip.util.{ResetCatchAndSync}
import freechips.rocketchip.prci._ import freechips.rocketchip.prci._

2
generators/chipyard/src/main/scala/config/ChipConfigs.scala
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@@ -4,7 +4,7 @@ import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
// A simple config demonstrating how to set up a basic chip in Chipyard // A simple config demonstrating how to set up a basic chip in Chipyard
class ChipLikeRocketConfig extends Config( class ChipLikeQuadRocketConfig extends Config(
//================================== //==================================
// Set up TestHarness // Set up TestHarness
//================================== //==================================

8
generators/chipyard/src/main/scala/example/FlatChipTop.scala
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@@ -2,7 +2,7 @@ package chipyard.example
import chisel3._ import chisel3._
import freechips.rocketchip.config.{Field, Parameters} import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._ import freechips.rocketchip.prci._
import freechips.rocketchip.util._ import freechips.rocketchip.util._
@@ -102,10 +102,10 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
//========================= //=========================
// JTAG/Debug // JTAG/Debug
//========================= //=========================
val debug = system.module.debug.get val debug = system.debug.get
// We never use the PSDIO, so tie it off on-chip // We never use the PSDIO, so tie it off on-chip
system.module.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) } system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) }
system.module.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := false.B } } system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := false.B } }
// Tie off extTrigger // Tie off extTrigger
debug.extTrigger.foreach { t => debug.extTrigger.foreach { t =>

2
generators/chipyard/src/main/scala/example/FlatTestHarness.scala
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@@ -4,7 +4,7 @@ import chisel3._
import scala.collection.mutable.{ArrayBuffer, LinkedHashMap} import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
import freechips.rocketchip.config.{Field, Parameters} import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.prci.{ClockSourceAtFreqFromPlusArg, ClockBundle, ClockBundleParameters} import freechips.rocketchip.prci.{ClockSourceAtFreqFromPlusArg, ClockBundle, ClockBundleParameters}
import freechips.rocketchip.util.{PlusArg} import freechips.rocketchip.util.{PlusArg}