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Bump rocket, make possible to use published deps (#47)

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* Use published rocketchip

* Simulator works!

* Gitignore was masking csrc

* Fix broken submodules

* Update gitignore

* Fix things up

* Some more cleanup

* Clean up so that using maven works

* Incorporate feedback

* Oops

* Add workaround for some of csrc

* Forgot dtm and jtag

* Make name better and add comment

* Extraneous comment

* Fix includes.

After running a clean build, I realized old build state was masking this
problem. verisim/csrc needs to be in the include path until we find a more
permanent solution to our problem.

* Add target to generate verilator-specific files.

* Ignore DS_Store

* Generate bootrom from testchipip

* Oops

* Add extraneous rocket-dsptools reference
This commit is contained in:
Paul Rigge
2019-03-06 18:22:21 -08:00
committed by GitHub
parent e5cbf49bb4
commit ddf3159d61
14 changed files with 531 additions and 215 deletions
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31
verisim/Makefile
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@@ -21,19 +21,15 @@ LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesv
include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag-verilator
sim_blackboxes = \
$(build_dir)/firrtl_black_box_resource_files.f
rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
sim_vsrcs = \
$(VERILOG_FILE) \
$(HARNESS_FILE) \
$(SMEMS_FILE) \
$(rocketchip_vsrc_dir)/AsyncResetReg.v \
$(rocketchip_vsrc_dir)/plusarg_reader.v \
$(testchip_vsrcs)
sim_csrcs = \
$(sim_dir)/csrc/verilator-harness.cc \
$(testchip_csrcs)
$(SMEMS_FILE)
model_dir = $(build_dir)/$(long_name)
model_dir_debug = $(build_dir)/$(long_name).debug
@@ -44,26 +40,27 @@ model_header_debug = $(model_dir_debug)/V$(MODEL).h
model_mk = $(model_dir)/V$(MODEL).mk
model_mk_debug = $(model_dir_debug)/V$(MODEL).mk
$(model_mk): $(sim_vsrcs) $(INSTALLED_VERILATOR)
$(model_mk): $(sim_vsrcs) $(verilator_dotf) $(INSTALLED_VERILATOR)
rm -rf $(build_dir)/$(long_name)
mkdir -p $(build_dir)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
-o $(sim) $(sim_vsrcs) $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(model_header)"
-o $(sim) $(sim_vsrcs) -f $(verilator_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)"
touch $@
$(sim): $(model_mk) $(sim_csrcs)
$(sim): $(model_mk)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk
$(model_mk_debug): $(sim_vsrcs) $(INSTALLED_VERILATOR)
$(model_mk_debug): $(sim_vsrcs) $(verilator_dotf) $(INSTALLED_VERILATOR)
rm -rf $(build_dir)/$(long_name)
mkdir -p $(build_dir)/$(long_name).debug
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
-o $(sim_debug) $(sim_vsrcs) $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(model_header_debug)"
-o $(sim_debug) $(sim_vsrcs) -f $(verilator_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)"
touch $@
$(sim_debug): $(model_mk_debug) $(sim_csrcs)
$(sim_debug): $(model_mk_debug)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk
$(output_dir)/%.out: $(output_dir)/% $(sim)
@@ -83,5 +80,5 @@ run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regress
run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))
clean:
clean: clean-scala
rm -rf generated-src ./simulator-*