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Bump rocket, make possible to use published deps (#47)

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* Use published rocketchip

* Simulator works!

* Gitignore was masking csrc

* Fix broken submodules

* Update gitignore

* Fix things up

* Some more cleanup

* Clean up so that using maven works

* Incorporate feedback

* Oops

* Add workaround for some of csrc

* Forgot dtm and jtag

* Make name better and add comment

* Extraneous comment

* Fix includes.

After running a clean build, I realized old build state was masking this
problem. verisim/csrc needs to be in the include path until we find a more
permanent solution to our problem.

* Add target to generate verilator-specific files.

* Ignore DS_Store

* Generate bootrom from testchipip

* Oops

* Add extraneous rocket-dsptools reference
This commit is contained in:
Paul Rigge
2019-03-06 18:22:21 -08:00
committed by GitHub
parent e5cbf49bb4
commit ddf3159d61
14 changed files with 531 additions and 215 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
verisim/Makefile
View File

@@ -21,19 +21,15 @@ LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesv
include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag-verilator
sim_blackboxes = \
$(build_dir)/firrtl_black_box_resource_files.f
rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
sim_vsrcs = \
$(VERILOG_FILE) \
$(HARNESS_FILE) \
$(SMEMS_FILE) \
$(rocketchip_vsrc_dir)/AsyncResetReg.v \
$(rocketchip_vsrc_dir)/plusarg_reader.v \
$(testchip_vsrcs)
sim_csrcs = \
$(sim_dir)/csrc/verilator-harness.cc \
$(testchip_csrcs)
$(SMEMS_FILE)
model_dir = $(build_dir)/$(long_name)
model_dir_debug = $(build_dir)/$(long_name).debug
@@ -44,26 +40,27 @@ model_header_debug = $(model_dir_debug)/V$(MODEL).h
model_mk = $(model_dir)/V$(MODEL).mk
model_mk_debug = $(model_dir_debug)/V$(MODEL).mk
$(model_mk): $(sim_vsrcs) $(INSTALLED_VERILATOR)
$(model_mk): $(sim_vsrcs) $(verilator_dotf) $(INSTALLED_VERILATOR)
rm -rf $(build_dir)/$(long_name)
mkdir -p $(build_dir)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
-o $(sim) $(sim_vsrcs) $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(model_header)"
-o $(sim) $(sim_vsrcs) -f $(verilator_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)"
touch $@
$(sim): $(model_mk) $(sim_csrcs)
$(sim): $(model_mk)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk
$(model_mk_debug): $(sim_vsrcs) $(INSTALLED_VERILATOR)
$(model_mk_debug): $(sim_vsrcs) $(verilator_dotf) $(INSTALLED_VERILATOR)
rm -rf $(build_dir)/$(long_name)
mkdir -p $(build_dir)/$(long_name).debug
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
-o $(sim_debug) $(sim_vsrcs) $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(model_header_debug)"
-o $(sim_debug) $(sim_vsrcs) -f $(verilator_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)"
touch $@
$(sim_debug): $(model_mk_debug) $(sim_csrcs)
$(sim_debug): $(model_mk_debug)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk
$(output_dir)/%.out: $(output_dir)/% $(sim)
@@ -83,5 +80,5 @@ run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regress
run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))
clean:
clean: clean-scala
rm -rf generated-src ./simulator-*

4
verisim/Makefrag-verilator
View File

@@ -24,8 +24,6 @@ verilator/verilator-$(VERILATOR_VERSION).tar.gz:
mkdir -p $(dir $@)
wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@
rocketchip_csrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/csrc
# Run Verilator to produce a fast binary to emulate this circuit.
VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
VERILATOR_FLAGS := --top-module $(MODEL) \
@@ -33,4 +31,4 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
--output-split 20000 \
-Wno-STMTDLY --x-assign unique \
-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(rocketchip_csrc_dir)/verilator.h"
-O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(MODEL) -DVERILATOR"

167
verisim/csrc/verilator-harness.cc
View File

@@ -1,167 +0,0 @@
// See LICENSE for license details.
#include "verilated.h"
#if VM_TRACE
#include "verilated_vcd_c.h"
#endif
#include <fesvr/tsi.h>
#include <iostream>
#include <fcntl.h>
#include <signal.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
extern tsi_t* tsi;
static uint64_t trace_count = 0;
bool verbose;
bool done_reset;
void handle_sigterm(int sig)
{
tsi->stop();
}
double sc_time_stamp()
{
return trace_count;
}
extern "C" int vpi_get_vlog_info(void* arg)
{
return 0;
}
static inline int copy_argv(int argc, char **argv, char **new_argv)
{
int optind = 1;
int new_argc = argc;
new_argv[0] = argv[0];
for (int i = 1; i < argc; i++) {
if (argv[i][0] != '+' && argv[i][0] != '-') {
optind = i - 1;
new_argc = argc - i + 1;
break;
}
}
for (int i = 1; i < new_argc; i++)
new_argv[i] = argv[i + optind];
return new_argc;
}
int main(int argc, char** argv)
{
unsigned random_seed = (unsigned)time(NULL) ^ (unsigned)getpid();
uint64_t max_cycles = -1;
uint64_t start = 0;
int ret = 0;
FILE *vcdfile = NULL;
bool print_cycles = false;
char *new_argv[argc];
int new_argc;
for (int i = 1; i < argc; i++) {
std::string arg = argv[i];
if (arg.substr(0, 2) == "-v") {
const char* filename = argv[i]+2;
vcdfile = strcmp(filename, "-") == 0 ? stdout : fopen(filename, "w");
if (!vcdfile)
abort();
} else if (arg.substr(0, 2) == "-s")
random_seed = atoi(argv[i]+2);
else if (arg == "+verbose")
verbose = true;
else if (arg.substr(0, 12) == "+max-cycles=")
max_cycles = atoll(argv[i]+12);
else if (arg.substr(0, 7) == "+start=")
start = atoll(argv[i]+7);
else if (arg.substr(0, 12) == "+cycle-count")
print_cycles = true;
}
if (verbose)
fprintf(stderr, "using random seed %u\n", random_seed);
srand(random_seed);
srand48(random_seed);
Verilated::randReset(2);
Verilated::commandArgs(argc, argv);
VTestHarness *tile = new VTestHarness;
#if VM_TRACE
Verilated::traceEverOn(true); // Verilator must compute traced signals
std::unique_ptr<VerilatedVcdFILE> vcdfd(new VerilatedVcdFILE(vcdfile));
std::unique_ptr<VerilatedVcdC> tfp(new VerilatedVcdC(vcdfd.get()));
if (vcdfile) {
tile->trace(tfp.get(), 99); // Trace 99 levels of hierarchy
tfp->open("");
}
#endif
new_argc = copy_argv(argc, argv, new_argv);
tsi = new tsi_t(new_argc, new_argv);
signal(SIGTERM, handle_sigterm);
// reset for several cycles to handle pipelined reset
for (int i = 0; i < 10; i++) {
tile->reset = 1;
tile->clock = 0;
tile->eval();
tile->clock = 1;
tile->eval();
tile->reset = 0;
}
done_reset = true;
while (!tsi->done() && !tile->io_success && trace_count < max_cycles) {
tile->clock = 0;
tile->eval();
#if VM_TRACE
bool dump = tfp && trace_count >= start;
if (dump)
tfp->dump(static_cast<vluint64_t>(trace_count * 2));
#endif
tile->clock = 1;
tile->eval();
#if VM_TRACE
if (dump)
tfp->dump(static_cast<vluint64_t>(trace_count * 2 + 1));
#endif
trace_count++;
}
#if VM_TRACE
if (tfp)
tfp->close();
#endif
if (vcdfile)
fclose(vcdfile);
if (tsi->exit_code())
{
fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %ld cycles\n", tsi->exit_code(), random_seed, trace_count);
ret = tsi->exit_code();
}
else if (trace_count == max_cycles)
{
fprintf(stderr, "*** FAILED *** (timeout, seed %d) after %ld cycles\n", random_seed, trace_count);
ret = 2;
}
else if (verbose || print_cycles)
{
fprintf(stderr, "Completed after %ld cycles\n", trace_count);
}
delete tsi;
delete tile;
return ret;
}