Bump rocket, make possible to use published deps (#47)

* Use published rocketchip

* Simulator works!

* Gitignore was masking csrc

* Fix broken submodules

* Update gitignore

* Fix things up

* Some more cleanup

* Clean up so that using maven works

* Incorporate feedback

* Oops

* Add workaround for some of csrc

* Forgot dtm and jtag

* Make name better and add comment

* Extraneous comment

* Fix includes.

After running a clean build, I realized old build state was masking this
problem. verisim/csrc needs to be in the include path until we find a more
permanent solution to our problem.

* Add target to generate verilator-specific files.

* Ignore DS_Store

* Generate bootrom from testchipip

* Oops

* Add extraneous rocket-dsptools reference

src/main/scala/example/Configs.scala

@@ -10,7 +10,7 @@ import testchipip._
 
 class WithBootROM extends Config((site, here, up) => {
   case BootROMParams => BootROMParams(
-    contentFileName = s"./testchipip/bootrom/bootrom.rv${site(XLen)}.img")
+    contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
 })
 
 object ConfigValName {

src/main/scala/example/TestHarness.scala

@@ -1,6 +1,8 @@
 package example
 
 import chisel3._
+import chisel3.experimental._
+import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper}
 import freechips.rocketchip.diplomacy.LazyModule
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.util.GeneratorApp
@@ -15,8 +17,21 @@ class TestHarness(implicit val p: Parameters) extends Module {
   val dut = p(BuildTop)(clock, reset.toBool, p)
   dut.debug := DontCare
   dut.connectSimAXIMem()
+  dut.connectSimAXIMMIO()
   dut.dontTouchPorts()
   dut.tieOffInterrupts()
+  dut.l2_frontend_bus_axi4.foreach(axi => {
+    axi.tieoff()
+    experimental.DataMirror.directionOf(axi.ar.ready) match {
+      case core.ActualDirection.Input =>
+        axi.r.bits := DontCare
+        axi.b.bits := DontCare
+      case core.ActualDirection.Output =>
+        axi.aw.bits := DontCare
+        axi.ar.bits := DontCare
+        axi.w.bits := DontCare
+    }
+  })
   io.success := dut.connectSimSerial()
 }
 
@@ -24,4 +39,5 @@ object Generator extends GeneratorApp {
   val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
   generateFirrtl
   generateAnno
+  generateArtefacts
 }

src/main/scala/example/Top.scala

@@ -2,26 +2,27 @@ package example
 
 import chisel3._
 import freechips.rocketchip.subsystem._
+import freechips.rocketchip.system._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.util.DontTouch
 import testchipip._
 
-class ExampleTop(implicit p: Parameters) extends RocketSubsystem
+class ExampleTop(implicit p: Parameters) extends ExampleRocketSystem //RocketSubsystem
     with CanHaveMasterAXI4MemPort
     with HasPeripheryBootROM
 //  with HasSystemErrorSlave
-    with HasSyncExtInterrupts
+//    with HasSyncExtInterrupts
     with HasNoDebug
     with HasPeripherySerial {
   override lazy val module = new ExampleTopModule(this)
 }
 
-class ExampleTopModule[+L <: ExampleTop](l: L) extends RocketSubsystemModuleImp(l)
+class ExampleTopModule[+L <: ExampleTop](l: L) extends ExampleRocketSystemModuleImp(l) // RocketSubsystemModuleImp(l)
     with HasRTCModuleImp
     with CanHaveMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
-    with HasExtInterruptsModuleImp
+//    with HasExtInterruptsModuleImp
     with HasNoDebugModuleImp
     with HasPeripherySerialModuleImp
     with DontTouch

src/main/scala/example/Verilator.scala

@@ -0,0 +1,92 @@
+package example
+
+import java.io.File
+
+case class GenerateSimConfig(
+  targetDir: String = ".",
+  dotFName: String = "verilator_files.f",
+)
+
+trait HasGenerateSimConfig {
+  val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") {
+    head("GenerateSimFiles", "0.1")
+
+    opt[String]("target-dir")
+      .abbr("td")
+      .valueName("<target-directory>")
+      .action((x, c) => c.copy(targetDir = x))
+      .text("Target director to put files")
+
+    opt[String]("dotFName")
+      .abbr("df")
+      .valueName("<dot-f filename>")
+      .action((x, c) => c.copy(dotFName = x))
+      .text("Name of generated dot-f file")
+  }
+}
+
+object GenerateSimFiles extends App with HasGenerateSimConfig {
+  def addOption(file: File): String = {
+    val fname = file.getCanonicalPath
+    // add -FI flag for header files
+    if (fname.takeRight(2) == ".h") {
+      s"-FI ${fname}"
+    } else { // do nothing otherwise
+      fname
+    }
+  }
+  def writeDotF(lines: Seq[String], cfg: GenerateSimConfig): Unit = {
+    writeTextToFile(lines.mkString("\n"), new File(cfg.targetDir, cfg.dotFName))
+  }
+  // From FIRRTL
+  def safeFile[A](fileName: String)(code: => A) = try { code } catch {
+    case e@ (_: java.io.FileNotFoundException | _: NullPointerException) => throw new Exception(fileName, e)
+    case t: Throwable                                            => throw t
+  }
+  // From FIRRTL
+  def writeResource(name: String, targetDir: String): File = {
+    val in = getClass.getResourceAsStream(name)
+    val p = java.nio.file.Paths.get(name)
+    val fname = p.getFileName().toString();
+
+    val f = new File(targetDir, fname)
+    val out = new java.io.FileOutputStream(f)
+    safeFile(name)(Iterator.continually(in.read).takeWhile(-1 != _).foreach(out.write))
+    out.close()
+    f
+  }
+  // From FIRRTL
+  def writeTextToFile(text: String, file: File) {
+    val out = new java.io.PrintWriter(file)
+    out.write(text)
+    out.close()
+  }
+  val resources = Seq(
+    // TODO(rigge): make conditional on if we are using verilator
+    "/project-template/csrc/emulator.cc",
+    "/csrc/SimDTM.cc",
+    "/csrc/SimJTAG.cc",
+    "/csrc/remote_bitbang.h",
+    "/csrc/remote_bitbang.cc",
+    "/csrc/verilator.h",
+    "/vsrc/EICG_wrapper.v",
+    "/testchipip/bootrom/bootrom.rv64.img",
+  )
+
+  def writeBootrom(): Unit = {
+    firrtl.FileUtils.makeDirectory("./bootrom/")
+    writeResource("/testchipip/bootrom/bootrom.rv64.img", "./bootrom/")
+  }
+
+  def writeFiles(cfg: GenerateSimConfig): Unit = {
+    writeBootrom()
+    firrtl.FileUtils.makeDirectory(cfg.targetDir)
+    val files = resources.map { writeResource(_, cfg.targetDir) }
+    writeDotF(files.map(addOption), cfg)
+  }
+
+  parser.parse(args, GenerateSimConfig()) match {
+    case Some(cfg) => writeFiles(cfg)
+    case _ => // error message already shown
+  }
+}