add more to docs | 1st spelling pass | more links | proper formatting

docs/Tools/Barstools.rst

@@ -1,3 +1,5 @@
 Barstools
 ===============================
-Barstools is a collection of useful FIRRTL transformations
+
+Barstools is a collection of useful FIRRTL transformations and Compilers to help the build process.
+Included in the tools are a MacroCompiler (used to map Chisel memory constructs to vendor SRAMs), FIRRTL transforms (to separate harness and top-level SoC files), and more.

docs/Tools/Chisel.rst

@@ -1,3 +1,19 @@
 Chisel
 ===========================
-TODO: Chisel intro and pointer to chisel bootcamp
+
+`Chisel <https://chisel.eecs.berkeley.edu/>`__ is an open-source hardware description language embedded in Scala.
+It supports advanced hardware design using highly parameterized generators and supports things such as Rocket Chip and BOOM.
+
+After writing Chisel, there are multiple steps before the Chisel source code "turns into" Verilog.
+First is the compilation step.
+If Chisel is thought as a library within Scala, then these classes being built are just Scala classes which call Chisel functions.
+Thus, any errors that you get in compiling the Scala/Chisel files are errors that you have violated the typing system, messed up syntax, or more.
+After the compilation is complete, elaboration begins.
+The Chisel generator starts elaboration using the module and configuration classes passed to it.
+This is where the Chisel "library functions" are called with the parameters given and Chisel tries to construct a circuit based on the Chisel code.
+If a runtime error happens here, Chisel is stating that it cannot "build" your circuit due to "violations" between your code and the Chisel "library".
+However, if that passes, the output of the generator gives you an FIRRTL file and other misc collateral!
+See :ref:`FIRRTL` for more information on how to get a FIRRTL file to Verilog.
+
+For an interactive tutorial on how to use Chisel and get started please visit the `Chisel Bootcamp <https://github.com/freechipsproject/chisel-bootcamp>`__.
+Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website <>`__.

docs/Tools/FIRRTL.rst

@@ -1,3 +1,12 @@
 FIRRTL
 ================================
 
+`FIRRTL <https://github.com/freechipsproject/firrtl>`__ is an intermediate representation of your circuit.
+It is emitted by the Chisel compiler and is used to translate Chisel source files into another representation such as Verilog.
+Without going into too much detail, FIRRTL is consumed by a FIRRTL compiler (another Scala program) which passes the circuit through a series of circuit-level transformations.
+An example of a FIRRTL pass (transformation) is one that optimizes out unused signals.
+Once the transformations are done, a Verilog file is emitted and the build process is done.
+
+For more information on please visit their `website <https://freechipsproject.github.io/firrtl/>`__.
+
+

docs/Tools/index.rst

@@ -1,7 +1,8 @@
 Tools
 ==============================
-The ReBAR framework relays heavily on a set of scala-based tools. While the framework attempts to hide the complexities of these tools, the following pages will introduce them, and how we can use them in order to generate flexible designs
 
+The REBAR framework relays heavily on a set of Scala-based tools.
+The following pages will introduce them, and how we can use them in order to generate flexible designs.
 
 .. toctree::
    :maxdepth: 2