From cfd555ee94faa34c27906436c648b3eb4c3d2907 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Thu, 21 Dec 2023 14:18:06 -0800
Subject: [PATCH 01/13] Bump testchipip for updated sertl type names

---
 .../main/scala/arty100t/HarnessBinders.scala  | 70 +++++++++++--------
 .../main/scala/example/FlatTestHarness.scala  | 33 +++++----
 .../main/scala/harness/HarnessBinders.scala   | 50 +++++++------
 .../scala/harness/MultiHarnessBinders.scala   | 15 ++--
 .../src/main/scala/iobinders/Ports.scala      |  5 +-
 .../src/main/scala/BridgeBinders.scala        | 26 ++++---
 generators/testchipip                         |  2 +-
 7 files changed, 118 insertions(+), 83 deletions(-)

diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala
index dd7c1a35..d6371ed5 100644
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -19,6 +19,7 @@ import sifive.fpgashells.clocks._
 import chipyard._
 import chipyard.harness._
 import chipyard.iobinders._
+import testchipip.serdes._
 
 class WithArty100TUARTTSI extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
@@ -48,36 +49,47 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
     val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
     val harnessIO = IO(chiselTypeOf(port.io)).suggestName("serial_tl")
     harnessIO <> port.io
-    val clkIO = IOPin(harnessIO.clock)
-    val packagePinsWithPackageIOs = Seq(
-      ("G13", clkIO),
-      ("B11", IOPin(harnessIO.bits.out.valid)),
-      ("A11", IOPin(harnessIO.bits.out.ready)),
-      ("D12", IOPin(harnessIO.bits.in.valid)),
-      ("D13", IOPin(harnessIO.bits.in.ready)),
-      ("B18", IOPin(harnessIO.bits.out.bits, 0)),
-      ("A18", IOPin(harnessIO.bits.out.bits, 1)),
-      ("K16", IOPin(harnessIO.bits.out.bits, 2)),
-      ("E15", IOPin(harnessIO.bits.out.bits, 3)),
-      ("E16", IOPin(harnessIO.bits.in.bits, 0)),
-      ("D15", IOPin(harnessIO.bits.in.bits, 1)),
-      ("C15", IOPin(harnessIO.bits.in.bits, 2)),
-      ("J17", IOPin(harnessIO.bits.in.bits, 3))
-    )
-    packagePinsWithPackageIOs foreach { case (pin, io) => {
-      artyTh.xdc.addPackagePin(io, pin)
-      artyTh.xdc.addIOStandard(io, "LVCMOS33")
-    }}
 
-    // Don't add IOB to the clock, if its an input
-    if (DataMirror.directionOf(port.io.clock) == Direction.Input) {
-      packagePinsWithPackageIOs foreach { case (pin, io) => {
-        artyTh.xdc.addIOB(io)
-      }}
+    harnessIO match {
+      case io: DecoupledSerialIO => {
+        val clkIO = io match {
+          case io: LocallySyncSerialIO => IOPin(io.clock_out)
+          case io: ExternallySyncSerialIO => IOPin(io.clock_in)
+        }
+        val packagePinsWithPackageIOs = Seq(
+          ("G13", clkIO),
+          ("B11", IOPin(io.out.valid)),
+          ("A11", IOPin(io.out.ready)),
+          ("D12", IOPin(io.in.valid)),
+          ("D13", IOPin(io.in.ready)),
+          ("B18", IOPin(io.out.bits, 0)),
+          ("A18", IOPin(io.out.bits, 1)),
+          ("K16", IOPin(io.out.bits, 2)),
+          ("E15", IOPin(io.out.bits, 3)),
+          ("E16", IOPin(io.in.bits, 0)),
+          ("D15", IOPin(io.in.bits, 1)),
+          ("C15", IOPin(io.in.bits, 2)),
+          ("J17", IOPin(io.in.bits, 3))
+        )
+        packagePinsWithPackageIOs foreach { case (pin, io) => {
+          artyTh.xdc.addPackagePin(io, pin)
+          artyTh.xdc.addIOStandard(io, "LVCMOS33")
+        }}
+
+        // Don't add IOB to the clock, if its an input
+        io match {
+          case io: LocallySyncSerialIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
+            artyTh.xdc.addIOB(io)
+          }}
+          case io: ExternallySyncSerialIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
+            artyTh.xdc.addIOB(io)
+          }}
+        }
+
+        artyTh.sdc.addClock("ser_tl_clock", clkIO, 100)
+        artyTh.sdc.addGroup(pins = Seq(clkIO))
+        artyTh.xdc.clockDedicatedRouteFalse(clkIO)
+      }
     }
-
-    artyTh.sdc.addClock("ser_tl_clock", clkIO, 100)
-    artyTh.sdc.addGroup(pins = Seq(clkIO))
-    artyTh.xdc.clockDedicatedRouteFalse(clkIO)
   }
 })
diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
index 304c58a3..d9e37918 100644
--- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
+++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
@@ -11,10 +11,10 @@ import freechips.rocketchip.util.{PlusArg}
 import freechips.rocketchip.subsystem.{CacheBlockBytes}
 import freechips.rocketchip.devices.debug.{SimJTAG}
 import freechips.rocketchip.jtag.{JTAGIO}
-import testchipip.serdes.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey, LocallySyncSerialIO, ExternallySyncSerialIO}
 import testchipip.uart.{UARTAdapter}
 import testchipip.dram.{SimDRAM}
-import testchipip.tsi.{TSIHarness, SimTSI}
+import testchipip.tsi.{TSIHarness, SimTSI, SerialRAM}
 import chipyard.harness.{BuildTop}
 
 // A "flat" TestHarness that doesn't use IOBinders
@@ -46,18 +46,25 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
   val serialTLManagerParams = sVal.manager.get
   require(serialTLManagerParams.isMemoryDevice)
 
-  withClockAndReset(clock, reset) {
-    val serial_bits = dut.serial_tl_pad.bits
-    if (DataMirror.directionOf(dut.serial_tl_pad.clock) == Direction.Input) {
-      dut.serial_tl_pad.clock := clock
-    }
-    val harnessRAM = TSIHarness.connectRAM(
-      p(SerialTLKey)(0),
-      lazyDut.system.serdessers(0),
-      serial_bits,
-      reset)
-    io.success := SimTSI.connect(harnessRAM.module.io.tsi, clock, reset)
+  // Figure out which clock drives the harness TLSerdes, based on the port type
+  val serial_ram_clock = dut.serial_tl_pad match {
+    case io: LocallySyncSerialIO => io.clock_out
+    case io: ExternallySyncSerialIO => clock
+  }
 
+  withClockAndReset(serial_ram_clock, reset) {
+    dut.serial_tl_pad match {
+      case io: ExternallySyncSerialIO => io.clock_in := clock
+      case io: LocallySyncSerialIO =>
+    }
+
+    // SerialRAM implements the memory regions the chip expects
+    val ram = Module(LazyModule(new SerialRAM(lazyDut.system.serdessers(0), p(SerialTLKey)(0))).module)
+    ram.io.ser.in <> dut.serial_tl_pad.out
+    dut.serial_tl_pad.in <> ram.io.ser.out
+
+    // Allow TSI to master the chip
+    io.success := SimTSI.connect(ram.io.tsi, serial_ram_clock, reset)
   }
 
   // JTAG
diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
index 6710696d..128cae0e 100644
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -17,7 +17,7 @@ import testchipip.tsi.{SimTSI, SerialRAM, TSI, TSIIO}
 import testchipip.soc.{TestchipSimDTM}
 import testchipip.spi.{SimSPIFlashModel}
 import testchipip.uart.{UARTAdapter, UARTToSerial}
-import testchipip.serdes.{SerialWidthAdapter}
+import testchipip.serdes._
 import testchipip.iceblk.{SimBlockDevice, BlockDeviceModel}
 import testchipip.cosim.{SpikeCosim}
 import icenet.{NicLoopback, SimNetwork}
@@ -207,33 +207,41 @@ class WithTiedOffDMI extends HarnessBinder({
 
 class WithSerialTLTiedOff extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: SerialTLPort) => {
-    if (DataMirror.directionOf(port.io.clock) == Direction.Input) {
-      port.io.clock := false.B.asClock
+    port.io match {
+      case io: DecoupledSerialIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare;
+    }
+    port.io match {
+      case io: LocallySyncSerialIO =>
+      case io: ExternallySyncSerialIO => io.clock_in := false.B.asClock
     }
-    port.io.bits.out.ready := false.B
-    port.io.bits.in.valid := false.B
-    port.io.bits.in.bits := DontCare
   }
 })
 
 class WithSimTSIOverSerialTL extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: SerialTLPort) => {
-    val bits = port.io.bits
-    if (DataMirror.directionOf(port.io.clock) == Direction.Input) {
-      port.io.clock := th.harnessBinderClock
+    port.io match {
+      case io: LocallySyncSerialIO =>
+      case io: ExternallySyncSerialIO => io.clock_in := false.B.asClock
+    }
+
+    port.io match {
+      case io: DecoupledSerialIO => {
+        // If the port is locally synchronous (provides a clock), drive everything with that clock
+        // Else, drive everything with the harnes clock
+        val clock = port.io match {
+          case io: LocallySyncSerialIO => io.clock_out
+          case io: ExternallySyncSerialIO => th.harnessBinderClock
+        }
+        withClock(clock) {
+          val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module)
+          ram.io.ser.in <> io.out
+          io.in <> ram.io.ser.out
+
+          val success = SimTSI.connect(ram.io.tsi, clock, th.harnessBinderReset)
+          when (success) { th.success := true.B }
+        }
+      }
     }
-    val ram = LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p))
-    Module(ram.module)
-    ram.module.io.ser <> port.io.bits
-    val tsi = Module(new SimTSI)
-    tsi.io.clock := th.harnessBinderClock
-    tsi.io.reset := th.harnessBinderReset
-    tsi.io.tsi <> ram.module.io.tsi.get
-    val exit = tsi.io.exit
-    val success = exit === 1.U
-    val error = exit >= 2.U
-    assert(!error, "*** FAILED *** (exit code = %d)\n", exit >> 1.U)
-    when (success) { th.success := true.B }
   }
 })
 
diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
index d3371dfd..d89d2d98 100644
--- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
@@ -10,7 +10,7 @@ import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.util._
 
-import testchipip._
+import testchipip.serdes._
 
 import chipyard._
 import chipyard.iobinders.{GetSystemParameters, JTAGChipIO, HasChipyardPorts, Port, SerialTLPort}
@@ -60,11 +60,14 @@ class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1p
   (p0: SerialTLPort) => p0.portId == chip0portId,
   (p1: SerialTLPort) => p1.portId == chip1portId,
   (th: HasHarnessInstantiators, p0: SerialTLPort, p1: SerialTLPort) => {
-    (DataMirror.directionOf(p0.io.clock), DataMirror.directionOf(p1.io.clock)) match {
-      case (Direction.Input, Direction.Output) => p0.io.clock := p1.io.clock
-      case (Direction.Output, Direction.Input) => p1.io.clock := p0.io.clock
+    def connectDecoupledSyncSerialIO(clkSource: LocallySyncSerialIO, clkSink: ExternallySyncSerialIO) = {
+      clkSink.clock_in := clkSource.clock_out
+      clkSink.in <> clkSource.out
+      clkSource.in <> clkSink.out
+    }
+    (p0.io, p1.io) match {
+      case (io0: LocallySyncSerialIO   , io1: ExternallySyncSerialIO) => connectDecoupledSyncSerialIO(io0, io1)
+      case (io0: ExternallySyncSerialIO, io1: LocallySyncSerialIO)    => connectDecoupledSyncSerialIO(io1, io0)
     }
-    p0.io.bits.in <> p1.io.bits.out
-    p1.io.bits.in <> p0.io.bits.out
   }
 )
diff --git a/generators/chipyard/src/main/scala/iobinders/Ports.scala b/generators/chipyard/src/main/scala/iobinders/Ports.scala
index ba14cc39..feb7bccb 100644
--- a/generators/chipyard/src/main/scala/iobinders/Ports.scala
+++ b/generators/chipyard/src/main/scala/iobinders/Ports.scala
@@ -72,8 +72,9 @@ case class DMIPort         (val getIO: () => ClockedDMIIO)
 case class JTAGPort        (val getIO: () => JTAGChipIO)
     extends Port[JTAGChipIO]
 
-case class SerialTLPort    (val getIO: () => ClockedIO[SerialIO], val params: SerialTLParams, val serdesser: TLSerdesser, val portId: Int)
-    extends Port[ClockedIO[SerialIO]]
+// Lack of nice union types in scala-2 means we have to set this type as Data
+case class SerialTLPort    (val getIO: () => Data, val params: SerialTLParams, val serdesser: TLSerdesser, val portId: Int)
+    extends Port[Data]
 
 case class UARTTSIPort     (val getIO: () => UARTTSIIO)
     extends Port[UARTTSIIO]
diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
index 954c104c..25ae6668 100644
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -15,6 +15,7 @@ import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import sifive.blocks.devices.uart._
 
+import testchipip.serdes.{ExternallySyncSerialIO}
 import testchipip.tsi.{SerialRAM}
 import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
 
@@ -67,18 +68,21 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
 
 class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
   case (th: FireSim, port: SerialTLPort) => {
-    val bits = port.io.bits
-    port.io.clock := th.harnessBinderClock
-    val ram = LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p))
-    Module(ram.module)
-    ram.module.io.ser <> port.io.bits
+    port.io match {
+      case io: ExternallySyncSerialIO => {
+        io.clock_in := th.harnessBinderClock
+        val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module)
+        ram.io.ser.in <> io.out
+        io.in <> ram.io.ser.out
 
-    // This assumes that:
-    // If ExtMem for the target is defined, then FASED bridge will be attached
-    // If FASED bridge is attached, loadmem widget is present
-    val hasMainMemory = th.chipParameters(th.p(MultiChipIdx))(ExtMem).isDefined
-    val mainMemoryName = Option.when(hasMainMemory)(MainMemoryConsts.globalName(th.p(MultiChipIdx)))
-    TSIBridge(th.harnessBinderClock, ram.module.io.tsi.get, mainMemoryName, th.harnessBinderReset.asBool)(th.p)
+        // This assumes that:
+        // If ExtMem for the target is defined, then FASED bridge will be attached
+        // If FASED bridge is attached, loadmem widget is present
+        val hasMainMemory = th.chipParameters(th.p(MultiChipIdx))(ExtMem).isDefined
+        val mainMemoryName = Option.when(hasMainMemory)(MainMemoryConsts.globalName(th.p(MultiChipIdx)))
+        TSIBridge(th.harnessBinderClock, ram.io.tsi.get, mainMemoryName, th.harnessBinderReset.asBool)(th.p)
+      }
+    }
   }
 })
 
diff --git a/generators/testchipip b/generators/testchipip
index 70e19831..e53f78aa 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 70e198313a7e467f9219e4caba0158a96f851503
+Subproject commit e53f78aa189c0cf7e0d3a9b08b44222ca05ab160

From 194d4462f9d6588d28d538a1d9711391bbd2db00 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Thu, 21 Dec 2023 20:33:24 -0800
Subject: [PATCH 02/13] Update testchipip with source-synchronous serdes

---
 fpga/src/main/scala/arty100t/Configs.scala    |  2 +-
 .../main/scala/arty100t/HarnessBinders.scala  |  8 ++---
 .../main/scala/config/AbstractConfig.scala    |  4 +--
 .../src/main/scala/config/ChipConfigs.scala   | 28 ++++++++++++----
 .../main/scala/example/FlatTestHarness.scala  | 33 ++++++++++---------
 .../main/scala/harness/HarnessBinders.scala   | 12 +++----
 .../scala/harness/MultiHarnessBinders.scala   |  6 ++--
 .../src/main/scala/BridgeBinders.scala        |  4 +--
 .../src/main/scala/TargetConfigs.scala        |  2 +-
 generators/testchipip                         |  2 +-
 10 files changed, 60 insertions(+), 41 deletions(-)

diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala
index c9892aa8..9588d80e 100644
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -56,5 +56,5 @@ class NoCoresArty100TConfig extends Config(
 class BringupArty100TConfig extends Config(
   new WithArty100TSerialTLToGPIO ++
   new WithArty100TTweaks(freqMHz = 50) ++
-  new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
+  new testchipip.serdes.WithSerialTLPHYParams(testchipip.serdes.InternalSyncSerialParams(freqMHz=50)) ++
   new chipyard.ChipBringupHostConfig)
diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala
index d6371ed5..d1af6fdc 100644
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -53,8 +53,8 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
     harnessIO match {
       case io: DecoupledSerialIO => {
         val clkIO = io match {
-          case io: LocallySyncSerialIO => IOPin(io.clock_out)
-          case io: ExternallySyncSerialIO => IOPin(io.clock_in)
+          case io: InternalSyncSerialIO => IOPin(io.clock_out)
+          case io: ExternalSyncSerialIO => IOPin(io.clock_in)
         }
         val packagePinsWithPackageIOs = Seq(
           ("G13", clkIO),
@@ -78,10 +78,10 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
 
         // Don't add IOB to the clock, if its an input
         io match {
-          case io: LocallySyncSerialIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
+          case io: InternalSyncSerialIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
             artyTh.xdc.addIOB(io)
           }}
-          case io: ExternallySyncSerialIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
+          case io: ExternalSyncSerialIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
             artyTh.xdc.addIOB(io)
           }}
         }
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
index cef46e04..c234e21a 100644
--- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala
+++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -65,8 +65,8 @@ class AbstractConfig extends Config(
   new testchipip.boot.WithBootAddrReg ++                            // add a boot-addr-reg for configurable boot address
   new testchipip.serdes.WithSerialTL(Seq(                           // add a serial-tilelink interface
     testchipip.serdes.SerialTLParams(
-      client = Some(testchipip.serdes.SerialTLClientParams(idBits=4)), // serial-tilelink interface will master the FBUS, and support 4 idBits
-      width = 32                                                    // serial-tilelink interface with 32 lanes
+      client = Some(testchipip.serdes.SerialTLClientParams()),      // serial-tilelink interface will master the FBUS, and support 4 idBits
+      phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32) // serial-tilelink interface with 32 lanes
     )
   )) ++
   new chipyard.config.WithDebugModuleAbstractDataWords(8) ++        // increase debug module data capacity
diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
index ffcb3f77..583d40bc 100644
--- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
@@ -22,8 +22,18 @@ class ChipLikeRocketConfig extends Config(
   //==================================
   // Set up I/O
   //==================================
-  new testchipip.serdes.WithSerialTLWidth(4) ++                                         // 4bit wide Serialized TL interface to minimize IO
-  new testchipip.serdes.WithSerialTLMem(size = (1 << 30) * 4L) ++                       // Configure the off-chip memory accessible over serial-tl as backing memory
+  new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(              // 1 serial tilelink port
+    manager = Some(testchipip.serdes.SerialTLManagerParams(                             // port acts as a manager of offchip memory
+      memParams = Seq(testchipip.serdes.ManagerRAMParams(                               // 4 GB of off-chip memory
+        address = BigInt("80000000", 16),
+        size    = BigInt("100000000", 16)
+      )),
+      isMemoryDevice = true
+    )),
+    client = Some(testchipip.serdes.SerialTLClientParams()),                            // Allow an external manager to probe this chip
+    phyParams = testchipip.serdes.ExternalSyncSerialParams(width=4)                     // 4-bit bidir interface, sync'd to an external clock
+  ))) ++
+
   new freechips.rocketchip.subsystem.WithNoMemPort ++                                   // Remove axi4 mem port
   new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++                          // 1 memory channel
 
@@ -60,10 +70,16 @@ class ChipBringupHostConfig extends Config(
   //=============================
   // Setup the SerialTL side on the bringup device
   //=============================
-  new testchipip.serdes.WithSerialTLWidth(4) ++                                // match width with the chip
-  new testchipip.serdes.WithSerialTLMem(base = 0x0, size = 0x80000000L,        // accessible memory of the chip that doesn't come from the tethered host
-                                        idBits = 4, isMainMemory = false) ++   // This assumes off-chip mem starts at 0x8000_0000
-  new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 75MHz clock
+  new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(
+    manager = Some(testchipip.serdes.SerialTLManagerParams(
+      memParams = Seq(testchipip.serdes.ManagerRAMParams(                            // Bringup platform can access all memory from 0 to DRAM_BASE
+        address = BigInt("00000000", 16),
+        size    = BigInt("80000000", 16)
+      ))
+    )),
+    client = Some(testchipip.serdes.SerialTLClientParams()),                         // Allow chip to access this device's memory (DRAM)
+    phyParams = testchipip.serdes.InternalSyncSerialParams(width=4, freqMHz = 75)    // bringup platform provides the clock
+  ))) ++
 
   //============================
   // Setup bus topology on the bringup system
diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
index d9e37918..9eeabecf 100644
--- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
+++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
@@ -11,7 +11,7 @@ import freechips.rocketchip.util.{PlusArg}
 import freechips.rocketchip.subsystem.{CacheBlockBytes}
 import freechips.rocketchip.devices.debug.{SimJTAG}
 import freechips.rocketchip.jtag.{JTAGIO}
-import testchipip.serdes.{SerialTLKey, LocallySyncSerialIO, ExternallySyncSerialIO}
+import testchipip.serdes._
 import testchipip.uart.{UARTAdapter}
 import testchipip.dram.{SimDRAM}
 import testchipip.tsi.{TSIHarness, SimTSI, SerialRAM}
@@ -48,23 +48,26 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
 
   // Figure out which clock drives the harness TLSerdes, based on the port type
   val serial_ram_clock = dut.serial_tl_pad match {
-    case io: LocallySyncSerialIO => io.clock_out
-    case io: ExternallySyncSerialIO => clock
+    case io: InternalSyncSerialIO => io.clock_out
+    case io: ExternalSyncSerialIO => clock
+  }
+  dut.serial_tl_pad match {
+    case io: ExternalSyncSerialIO => io.clock_in := clock
+    case io: InternalSyncSerialIO =>
   }
 
-  withClockAndReset(serial_ram_clock, reset) {
-    dut.serial_tl_pad match {
-      case io: ExternallySyncSerialIO => io.clock_in := clock
-      case io: LocallySyncSerialIO =>
+  dut.serial_tl_pad match {
+    case pad: DecoupledSerialIO => {
+      withClockAndReset(serial_ram_clock, reset) {
+        // SerialRAM implements the memory regions the chip expects
+        val ram = Module(LazyModule(new SerialRAM(lazyDut.system.serdessers(0), p(SerialTLKey)(0))).module)
+        ram.io.ser.in <> pad.out
+        pad.in <> ram.io.ser.out
+
+        // Allow TSI to master the chip
+        io.success := SimTSI.connect(ram.io.tsi, serial_ram_clock, reset)
+      }
     }
-
-    // SerialRAM implements the memory regions the chip expects
-    val ram = Module(LazyModule(new SerialRAM(lazyDut.system.serdessers(0), p(SerialTLKey)(0))).module)
-    ram.io.ser.in <> dut.serial_tl_pad.out
-    dut.serial_tl_pad.in <> ram.io.ser.out
-
-    // Allow TSI to master the chip
-    io.success := SimTSI.connect(ram.io.tsi, serial_ram_clock, reset)
   }
 
   // JTAG
diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
index 128cae0e..a29cf5c0 100644
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -211,8 +211,8 @@ class WithSerialTLTiedOff extends HarnessBinder({
       case io: DecoupledSerialIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare;
     }
     port.io match {
-      case io: LocallySyncSerialIO =>
-      case io: ExternallySyncSerialIO => io.clock_in := false.B.asClock
+      case io: InternalSyncSerialIO =>
+      case io: ExternalSyncSerialIO => io.clock_in := false.B.asClock
     }
   }
 })
@@ -220,8 +220,8 @@ class WithSerialTLTiedOff extends HarnessBinder({
 class WithSimTSIOverSerialTL extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: SerialTLPort) => {
     port.io match {
-      case io: LocallySyncSerialIO =>
-      case io: ExternallySyncSerialIO => io.clock_in := false.B.asClock
+      case io: InternalSyncSerialIO =>
+      case io: ExternalSyncSerialIO => io.clock_in := false.B.asClock
     }
 
     port.io match {
@@ -229,8 +229,8 @@ class WithSimTSIOverSerialTL extends HarnessBinder({
         // If the port is locally synchronous (provides a clock), drive everything with that clock
         // Else, drive everything with the harnes clock
         val clock = port.io match {
-          case io: LocallySyncSerialIO => io.clock_out
-          case io: ExternallySyncSerialIO => th.harnessBinderClock
+          case io: InternalSyncSerialIO => io.clock_out
+          case io: ExternalSyncSerialIO => th.harnessBinderClock
         }
         withClock(clock) {
           val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module)
diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
index d89d2d98..e159e345 100644
--- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
@@ -60,14 +60,14 @@ class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1p
   (p0: SerialTLPort) => p0.portId == chip0portId,
   (p1: SerialTLPort) => p1.portId == chip1portId,
   (th: HasHarnessInstantiators, p0: SerialTLPort, p1: SerialTLPort) => {
-    def connectDecoupledSyncSerialIO(clkSource: LocallySyncSerialIO, clkSink: ExternallySyncSerialIO) = {
+    def connectDecoupledSyncSerialIO(clkSource: InternalSyncSerialIO, clkSink: ExternalSyncSerialIO) = {
       clkSink.clock_in := clkSource.clock_out
       clkSink.in <> clkSource.out
       clkSource.in <> clkSink.out
     }
     (p0.io, p1.io) match {
-      case (io0: LocallySyncSerialIO   , io1: ExternallySyncSerialIO) => connectDecoupledSyncSerialIO(io0, io1)
-      case (io0: ExternallySyncSerialIO, io1: LocallySyncSerialIO)    => connectDecoupledSyncSerialIO(io1, io0)
+      case (io0: InternalSyncSerialIO, io1: ExternalSyncSerialIO) => connectDecoupledSyncSerialIO(io0, io1)
+      case (io0: ExternalSyncSerialIO, io1: InternalSyncSerialIO) => connectDecoupledSyncSerialIO(io1, io0)
     }
   }
 )
diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
index 25ae6668..1cb365bd 100644
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -15,7 +15,7 @@ import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import sifive.blocks.devices.uart._
 
-import testchipip.serdes.{ExternallySyncSerialIO}
+import testchipip.serdes.{ExternalSyncSerialIO}
 import testchipip.tsi.{SerialRAM}
 import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
 
@@ -69,7 +69,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
 class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
   case (th: FireSim, port: SerialTLPort) => {
     port.io match {
-      case io: ExternallySyncSerialIO => {
+      case io: ExternalSyncSerialIO => {
         io.clock_in := th.harnessBinderClock
         val ram = Module(LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)).module)
         ram.io.ser.in <> io.out
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index 9f5f7ef6..eb092944 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -260,7 +260,7 @@ class FireSimSmallSystemConfig extends Config(
   new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
   new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(
     client = Some(testchipip.serdes.SerialTLClientParams(idBits = 4)),
-    width = 32
+    phyParams = testchipip.serdes.ExternalSyncSerialParams(width=32)
   ))) ++
   new testchipip.iceblk.WithBlockDevice ++
   new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
diff --git a/generators/testchipip b/generators/testchipip
index e53f78aa..9011ac85 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit e53f78aa189c0cf7e0d3a9b08b44222ca05ab160
+Subproject commit 9011ac8530f8186e013409f0e2d65f54b2b512d4

From 81cc556c3b79e727a69ae2437e42bd9e85bb3359 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 26 Dec 2023 10:05:44 -0800
Subject: [PATCH 03/13] Add symmetric rocket config

---
 .../main/scala/config/ChipletConfigs.scala    | 38 +++++++++++++++++++
 .../main/scala/harness/HarnessBinders.scala   | 17 +++++++--
 .../scala/harness/MultiHarnessBinders.scala   | 11 ++++++
 generators/testchipip                         |  2 +-
 4 files changed, 63 insertions(+), 5 deletions(-)
 create mode 100644 generators/chipyard/src/main/scala/config/ChipletConfigs.scala

diff --git a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
new file mode 100644
index 00000000..3b802c57
--- /dev/null
+++ b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
@@ -0,0 +1,38 @@
+package chipyard
+
+import org.chipsalliance.cde.config.{Config}
+import freechips.rocketchip.diplomacy.{AddressSet}
+import freechips.rocketchip.subsystem.{SBUS}
+import testchipip.soc.{OBUS}
+
+// ------------------------------------------------
+// Configs demonstrating chip-to-chip communication
+// ------------------------------------------------
+
+// Simple design which exposes a second serial-tl port that can connect to another instance of itself
+class SymmetricChipletRocketConfig extends Config(
+  new chipyard.harness.WithSerialTLTiedOff(tieoffs=Some(Seq(1))) ++ // Tie-off the chip-to-chip link in single-chip sims
+  new testchipip.serdes.WithSerialTL(Seq(
+    testchipip.serdes.SerialTLParams(                               // 0th serial-tl is chip-to-bringup-fpga
+      client = Some(testchipip.serdes.SerialTLClientParams()),      // bringup serial-tl acts only as a client
+      phyParams = testchipip.serdes.ExternalSyncSerialParams()      // bringup serial-tl is sync'd to external clock
+    ),
+    testchipip.serdes.SerialTLParams(                               // 1st serial-tl is chip-to-chip
+      client = Some(testchipip.serdes.SerialTLClientParams()),      // chip-to-chip serial-tl acts as a client
+      manager = Some(testchipip.serdes.SerialTLManagerParams(       // chip-to-chip serial-tl managers other chip's memory
+        memParams = Seq(testchipip.serdes.ManagerRAMParams(
+          address = 0,
+          size = 1L << 32,
+        )),
+        slaveWhere = OBUS
+      )),
+      phyParams = testchipip.serdes.SourceSyncSerialParams()        // chip-to-chip serial-tl is symmetric source-sync'd
+    ))
+  ) ++
+  new testchipip.soc.WithOffchipBusClient(SBUS,                     // obus provides path to other chip's memory
+    blockRange = Seq(AddressSet(0, (1L << 32) - 1)),                // The lower 4GB is mapped to this chip
+    replicationBase = Some(1L << 32)                                // The upper 4GB goes off-chip
+  ) ++
+  new testchipip.soc.WithOffchipBus ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
index a29cf5c0..a50f1743 100644
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -205,23 +205,32 @@ class WithTiedOffDMI extends HarnessBinder({
   }
 })
 
-class WithSerialTLTiedOff extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: SerialTLPort) => {
+// If tieoffs is specified, a list of serial portIds to tie off
+// If tieoffs is unspecified, ties off all serial ports
+class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: SerialTLPort) if (tieoffs.map(_.contains(port.portId)).getOrElse(true)) => {
     port.io match {
       case io: DecoupledSerialIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare;
+      case io: SourceSyncSerialIO => {
+        io.clock_in := false.B.asClock
+        io.reset_in := false.B.asAsyncReset
+        io.in := DontCare
+        io.credit_in := DontCare
+      }
     }
     port.io match {
       case io: InternalSyncSerialIO =>
       case io: ExternalSyncSerialIO => io.clock_in := false.B.asClock
+      case _ =>
     }
   }
 })
 
 class WithSimTSIOverSerialTL extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: SerialTLPort) => {
+  case (th: HasHarnessInstantiators, port: SerialTLPort) if (port.portId == 0) => {
     port.io match {
       case io: InternalSyncSerialIO =>
-      case io: ExternalSyncSerialIO => io.clock_in := false.B.asClock
+      case io: ExternalSyncSerialIO => io.clock_in := th.harnessBinderClock
     }
 
     port.io match {
diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
index e159e345..9cd6afd2 100644
--- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
@@ -65,9 +65,20 @@ class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1p
       clkSink.in <> clkSource.out
       clkSource.in <> clkSink.out
     }
+    def connectSourceSyncSerialIO(a: SourceSyncSerialIO, b: SourceSyncSerialIO) = {
+      a.clock_in := b.clock_out
+      b.clock_in := a.clock_out
+      a.reset_in := b.reset_out
+      b.reset_in := a.reset_out
+      a.in := b.out
+      b.in := a.out
+      a.credit_in := b.credit_out
+      b.credit_in := a.credit_out
+    }
     (p0.io, p1.io) match {
       case (io0: InternalSyncSerialIO, io1: ExternalSyncSerialIO) => connectDecoupledSyncSerialIO(io0, io1)
       case (io0: ExternalSyncSerialIO, io1: InternalSyncSerialIO) => connectDecoupledSyncSerialIO(io1, io0)
+      case (io0: SourceSyncSerialIO  , io1: SourceSyncSerialIO  ) => connectSourceSyncSerialIO   (io0, io1)
     }
   }
 )
diff --git a/generators/testchipip b/generators/testchipip
index 9011ac85..11551255 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 9011ac8530f8186e013409f0e2d65f54b2b512d4
+Subproject commit 11551255834ff4f98c1474a806b7c733cb53d6ee

From 8e37dcdf81d18649f21725014e6e3b07b7a98229 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 26 Dec 2023 12:52:23 -0800
Subject: [PATCH 04/13] Support multi-TSI/multi-SimDRAM

---
 .../chipyard/src/main/scala/config/ChipletConfigs.scala   | 8 ++++++++
 .../chipyard/src/main/scala/harness/HarnessBinders.scala  | 8 +++-----
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
index 3b802c57..e07aa73d 100644
--- a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
@@ -36,3 +36,11 @@ class SymmetricChipletRocketConfig extends Config(
   new testchipip.soc.WithOffchipBus ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
+
+// Simulates 2X of the SymmetricChipletRocketConfig in a multi-sim config
+class MultiSimSymmetricChipletRocketConfig extends Config(
+  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++
+  new chipyard.harness.WithMultiChipSerialTL(chip0=0, chip1=1, chip0portId=1, chip1portId=1) ++
+  new chipyard.harness.WithMultiChip(0, new SymmetricChipletRocketConfig) ++
+  new chipyard.harness.WithMultiChip(1, new SymmetricChipletRocketConfig)
+)
diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
index a50f1743..5d71c1bd 100644
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -50,9 +50,7 @@ class WithGPIOTiedOff extends HarnessBinder({
 class WithUARTAdapter extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: UARTPort) => {
     val div = (th.getHarnessBinderClockFreqMHz.toDouble * 1000000 / port.io.c.initBaudRate.toDouble).toInt
-    val uart_sim = Module(new UARTAdapter(port.uartNo, div, false)).suggestName(s"uart_sim_uartno${port.uartNo}")
-    uart_sim.io.uart.txd := port.io.txd
-    port.io.rxd := uart_sim.io.uart.rxd
+    UARTAdapter.connect(Seq(port.io), div, false)
   }
 })
 // DOC include end: WithUARTAdapter
@@ -113,7 +111,7 @@ class WithBlackBoxSimMem(additionalLatency: Int = 0) extends HarnessBinder({
     val memBase = port.params.master.base
     val lineSize = 64 // cache block size
     val clockFreq = port.clockFreqMHz
-    val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, memBase, port.edge.bundle)).suggestName("simdram")
+    val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, memBase, port.edge.bundle, th.p(MultiChipIdx))).suggestName("simdram")
 
     mem.io.clock := port.io.clock
     mem.io.reset := th.harnessBinderReset.asAsyncReset
@@ -246,7 +244,7 @@ class WithSimTSIOverSerialTL extends HarnessBinder({
           ram.io.ser.in <> io.out
           io.in <> ram.io.ser.out
 
-          val success = SimTSI.connect(ram.io.tsi, clock, th.harnessBinderReset)
+          val success = SimTSI.connect(ram.io.tsi, clock, th.harnessBinderReset, th.p(MultiChipIdx))
           when (success) { th.success := true.B }
         }
       }

From fdeede7b0bbbf1ce818812f27264da7363cda274 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 26 Dec 2023 12:55:32 -0800
Subject: [PATCH 05/13] Add tests for symmetric rocket chiplet config

---
 .github/scripts/defaults.sh              |  3 ++-
 .github/scripts/run-tests.sh             |  4 ++++
 .github/workflows/chipyard-run-tests.yml | 24 +++++++++++++++++++
 generators/testchipip                    |  2 +-
 tests/Makefile                           |  2 +-
 tests/symmetric.c                        | 30 ++++++++++++++++++++++++
 6 files changed, 62 insertions(+), 3 deletions(-)
 create mode 100644 tests/symmetric.c

diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh
index d4eb7b56..94339a5b 100755
--- a/.github/scripts/defaults.sh
+++ b/.github/scripts/defaults.sh
@@ -29,7 +29,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
 # key value store to get the build groups
 declare -A grouping
 grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
-grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered"
+grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric"
 grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
 grouping["group-constellation"]="chipyard-constellation"
 grouping["group-tracegen"]="tracegen tracegen-boom"
@@ -58,6 +58,7 @@ mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_F
 mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
 mapping["chipyard-chiplike"]=" CONFIG=ChipLikeRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog"
 mapping["chipyard-tethered"]=" CONFIG=VerilatorCITetheredChipLikeRocketConfig"
+mapping["chipyard-symmetric"]=" CONFIG=MultiSimSymmetricChipletRocketConfig"
 mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog"
 mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"
 mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"
diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh
index ce272737..eccc5563 100755
--- a/.github/scripts/run-tests.sh
+++ b/.github/scripts/run-tests.sh
@@ -118,6 +118,10 @@ case $1 in
         make -C $LOCAL_CHIPYARD_DIR/tests
         run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv LOADMEM=1 EXTRA_SIM_FLAGS="+cflush_addr=0x2010200"
         ;;
+    chipyard-symmetric)
+        make -C $LOCAL_CHIPYARD_DIR/tests
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/symmetric.riscv LOADMEM=1
+        ;;
     tracegen)
         run_tracegen
         ;;
diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml
index 1c0f10d8..b524ae37 100644
--- a/.github/workflows/chipyard-run-tests.yml
+++ b/.github/workflows/chipyard-run-tests.yml
@@ -708,6 +708,29 @@ jobs:
           group-key: "group-peripherals"
           project-key: "chipyard-tethered"
 
+  chipyard-symmetric-run-tests:
+    name: chipyard-symmetric-run-tests
+    needs: prepare-chipyard-peripherals
+    runs-on: as4
+    steps:
+      - name: Delete old checkout
+        run: |
+            ls -alh .
+            rm -rf ${{ github.workspace }}/* || true
+            rm -rf ${{ github.workspace }}/.* || true
+            ls -alh .
+      - name: Checkout
+        uses: actions/checkout@v3
+      - name: Git workaround
+        uses: ./.github/actions/git-workaround
+      - name: Create conda env
+        uses: ./.github/actions/create-conda-env
+      - name: Run tests
+        uses: ./.github/actions/run-tests
+        with:
+          group-key: "group-peripherals"
+          project-key: "chipyard-symmetric"
+
   chipyard-sha3-run-tests:
     name: chipyard-sha3-run-tests
     needs: prepare-chipyard-accels
@@ -1071,6 +1094,7 @@ jobs:
             chipyard-spiflashwrite-run-tests,
             chipyard-manyperipherals-run-tests,
             chipyard-tethered-run-tests,
+            chipyard-symmetric-run-tests,
             chipyard-sha3-run-tests,
             chipyard-gemmini-run-tests,
             chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests,
diff --git a/generators/testchipip b/generators/testchipip
index 11551255..9d1a2125 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 11551255834ff4f98c1474a806b7c733cb53d6ee
+Subproject commit 9d1a2125799cd7179e280e6901e84235f3f479a8
diff --git a/tests/Makefile b/tests/Makefile
index 670b49ea..1c6df31b 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -29,7 +29,7 @@ include libgloss.mk
 
 PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd \
            streaming-passthrough streaming-fir nvdla spiflashread spiflashwrite fft gcd \
-           hello mt-hello
+           hello mt-hello symmetric
 
 
 .DEFAULT_GOAL := default
diff --git a/tests/symmetric.c b/tests/symmetric.c
new file mode 100644
index 00000000..a6d37627
--- /dev/null
+++ b/tests/symmetric.c
@@ -0,0 +1,30 @@
+#include <stdio.h>
+#include <string.h>
+#include <riscv-pk/encoding.h>
+#include "marchid.h"
+
+#define OBUS_OFFSET (0x1L << 32)
+
+char src[] = "This is a test string. It will be written into the off-chip memory address, then copied back.";
+char dest[4096];
+char test[4096];
+
+int main(void) {
+  size_t write_start = rdcycle();
+  memcpy(dest + OBUS_OFFSET, src, sizeof(src));
+  size_t write_end = rdcycle();
+
+  printf("Wrote %ld bytes in %ld cycles\n", sizeof(src), write_end - write_start);
+
+  size_t read_start = rdcycle();
+  memcpy(test, dest + OBUS_OFFSET, sizeof(src));
+  size_t read_end = rdcycle();
+
+  if (memcmp(src, test, sizeof(src))) {
+    printf("Remote write/read failed\n");
+    exit(1);
+  }
+  printf("Read %ld bytes in %ld cycles\n", sizeof(src), read_end - read_start);
+
+  return 0;
+}

From 3885e79f7734ecd5650ee6cd7644744514178ad2 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 26 Dec 2023 17:19:09 -0800
Subject: [PATCH 06/13] Bump testchipip

---
 generators/testchipip | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/generators/testchipip b/generators/testchipip
index 9d1a2125..e1fc05b0 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 9d1a2125799cd7179e280e6901e84235f3f479a8
+Subproject commit e1fc05b09283524fc09bee7d3ff351b6f83825ca

From 835562238add317102f3312844675826e1e50ce9 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 26 Dec 2023 18:37:39 -0800
Subject: [PATCH 07/13] Explicitly pass chipId to all HarnessBinders

---
 fpga/src/main/scala/arty/HarnessBinders.scala |  8 +--
 .../main/scala/arty100t/HarnessBinders.scala  |  6 +-
 .../scala/nexysvideo/HarnessBinders.scala     |  4 +-
 .../src/main/scala/vc707/HarnessBinders.scala |  6 +-
 .../main/scala/vcu118/HarnessBinders.scala    |  6 +-
 .../scala/vcu118/bringup/HarnessBinders.scala | 10 ++--
 .../main/scala/harness/HarnessBinders.scala   | 58 +++++++++----------
 .../harness/HasHarnessInstantiators.scala     |  2 +-
 .../scala/harness/MultiHarnessBinders.scala   |  4 +-
 .../src/main/scala/harness/package.scala      |  2 +-
 .../src/main/scala/BridgeBinders.scala        | 22 +++----
 11 files changed, 64 insertions(+), 64 deletions(-)

diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala
index d2ce5489..39ddd204 100644
--- a/fpga/src/main/scala/arty/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty/HarnessBinders.scala
@@ -15,19 +15,19 @@ import chipyard.harness.{HarnessBinder}
 import chipyard.iobinders._
 
 class WithArtyDebugResetHarnessBinder extends HarnessBinder({
-  case (th: Arty35THarness, port: DebugResetPort) => {
+  case (th: Arty35THarness, port: DebugResetPort, chipId: Int) => {
     th.dut_ndreset := port.io // Debug module reset
   }
 })
 
 class WithArtyJTAGResetHarnessBinder extends HarnessBinder({
-  case (th: Arty35THarness, port: JTAGResetPort) => {
+  case (th: Arty35THarness, port: JTAGResetPort, chipId: Int) => {
     port.io := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset
   }
 })
 
 class WithArtyJTAGHarnessBinder extends HarnessBinder({
-  case (th: Arty35THarness, port: JTAGPort) => {
+  case (th: Arty35THarness, port: JTAGPort, chipId: Int) => {
     val jtag_wire = Wire(new JTAGIO)
     jtag_wire.TDO.data := port.io.TDO
     jtag_wire.TDO.driven := true.B
@@ -62,7 +62,7 @@ class WithArtyJTAGHarnessBinder extends HarnessBinder({
 })
 
 class WithArtyUARTHarnessBinder extends HarnessBinder({
-  case (th: Arty35THarness, port: UARTPort) => {
+  case (th: Arty35THarness, port: UARTPort, chipId: Int) => {
     withClockAndReset(th.clock_32MHz, th.ck_rst) {
       IOBUF(th.uart_rxd_out,  port.io.txd)
       port.io.rxd := IOBUF(th.uart_txd_in)
diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala
index d1af6fdc..b6c7273a 100644
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -22,7 +22,7 @@ import chipyard.iobinders._
 import testchipip.serdes._
 
 class WithArty100TUARTTSI extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
+  case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
     val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
     ath.io_uart_bb.bundle <> port.io.uart
     ath.other_leds(1) := port.io.dropped
@@ -34,7 +34,7 @@ class WithArty100TUARTTSI extends HarnessBinder({
 })
 
 class WithArty100TDDRTL extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: TLMemPort) => {
+  case (th: HasHarnessInstantiators, port: TLMemPort, chipId: Int) => {
     val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
     val bundles = artyTh.ddrClient.out.map(_._1)
     val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
@@ -45,7 +45,7 @@ class WithArty100TDDRTL extends HarnessBinder({
 
 // Uses PMOD JA/JB
 class WithArty100TSerialTLToGPIO extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: SerialTLPort) => {
+  case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) => {
     val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
     val harnessIO = IO(chiselTypeOf(port.io)).suggestName("serial_tl")
     harnessIO <> port.io
diff --git a/fpga/src/main/scala/nexysvideo/HarnessBinders.scala b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala
index e6865eff..29deeadb 100644
--- a/fpga/src/main/scala/nexysvideo/HarnessBinders.scala
+++ b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala
@@ -15,7 +15,7 @@ import chipyard.harness._
 import chipyard.iobinders._
 
 class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
+  case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
     val nexysvideoth = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
     nexysvideoth.io_uart_bb.bundle <> port.io.uart
     nexysvideoth.other_leds(1) := port.io.dropped
@@ -27,7 +27,7 @@ class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder
 })
 
 class WithNexysVideoDDRTL extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: TLMemPort) => {
+  case (th: HasHarnessInstantiators, port: TLMemPort, chipId: Int) => {
     val nexysTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
     val bundles = nexysTh.ddrClient.get.out.map(_._1)
     val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
diff --git a/fpga/src/main/scala/vc707/HarnessBinders.scala b/fpga/src/main/scala/vc707/HarnessBinders.scala
index 25224d57..d08fba76 100644
--- a/fpga/src/main/scala/vc707/HarnessBinders.scala
+++ b/fpga/src/main/scala/vc707/HarnessBinders.scala
@@ -16,21 +16,21 @@ import chipyard.iobinders._
 
 /*** UART ***/
 class WithVC707UARTHarnessBinder extends HarnessBinder({
-  case (th: VC707FPGATestHarnessImp, port: UARTPort) => {
+  case (th: VC707FPGATestHarnessImp, port: UARTPort, chipId: Int) => {
     th.vc707Outer.io_uart_bb.bundle <> port.io
   }
 })
 
 /*** SPI ***/
 class WithVC707SPISDCardHarnessBinder extends HarnessBinder({
-  case (th: VC707FPGATestHarnessImp, port: SPIPort) => {
+  case (th: VC707FPGATestHarnessImp, port: SPIPort, chipId: Int) => {
     th.vc707Outer.io_spi_bb.bundle <> port.io
   }
 })
 
 /*** Experimental DDR ***/
 class WithVC707DDRMemHarnessBinder extends HarnessBinder({
-  case (th: VC707FPGATestHarnessImp, port: TLMemPort) => {
+  case (th: VC707FPGATestHarnessImp, port: TLMemPort, chipId: Int) => {
     val bundles = th.vc707Outer.ddrClient.out.map(_._1)
     val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
     bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
diff --git a/fpga/src/main/scala/vcu118/HarnessBinders.scala b/fpga/src/main/scala/vcu118/HarnessBinders.scala
index 769e5b42..c03f551f 100644
--- a/fpga/src/main/scala/vcu118/HarnessBinders.scala
+++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala
@@ -15,21 +15,21 @@ import chipyard.iobinders._
 
 /*** UART ***/
 class WithUART extends HarnessBinder({
-  case (th: VCU118FPGATestHarnessImp, port: UARTPort) => {
+  case (th: VCU118FPGATestHarnessImp, port: UARTPort, chipId: Int) => {
     th.vcu118Outer.io_uart_bb.bundle <> port.io
   }
 })
 
 /*** SPI ***/
 class WithSPISDCard extends HarnessBinder({
-  case (th: VCU118FPGATestHarnessImp, port: SPIPort) => {
+  case (th: VCU118FPGATestHarnessImp, port: SPIPort, chipId: Int) => {
     th.vcu118Outer.io_spi_bb.bundle <> port.io
   }
 })
 
 /*** Experimental DDR ***/
 class WithDDRMem extends HarnessBinder({
-  case (th: VCU118FPGATestHarnessImp, port: TLMemPort) => {
+  case (th: VCU118FPGATestHarnessImp, port: TLMemPort, chipId: Int) => {
     val bundles = th.vcu118Outer.ddrClient.out.map(_._1)
     val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
     bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
index c130a697..27933bf6 100644
--- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
+++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
@@ -18,34 +18,34 @@ import chipyard.iobinders._
 
 /*** UART ***/
 class WithBringupUART extends HarnessBinder({
-  case (th: BringupVCU118FPGATestHarnessImp, port: UARTPort) => {
+  case (th: BringupVCU118FPGATestHarnessImp, port: UARTPort, chipId: Int) => {
     th.bringupOuter.io_fmc_uart_bb.bundle <> port.io
   }
 })
 
 /*** I2C ***/
 class WithBringupI2C extends HarnessBinder({
-  case (th: BringupVCU118FPGATestHarnessImp, port: chipyard.iobinders.I2CPort) => {
+  case (th: BringupVCU118FPGATestHarnessImp, port: chipyard.iobinders.I2CPort, chipId: Int) => {
     th.bringupOuter.io_i2c_bb.bundle <> port.io
   }
 })
 
 /*** GPIO ***/
 class WithBringupGPIO extends HarnessBinder({
-  case (th: BringupVCU118FPGATestHarnessImp, port: GPIOPort) => {
+  case (th: BringupVCU118FPGATestHarnessImp, port: GPIOPort, chipId: Int) => {
     th.bringupOuter.io_gpio_bb(port.pinId).bundle <> port.io
   }
 })
 
 /*** TSI Host Widget ***/
 class WithBringupTSIHost extends HarnessBinder({
-  case (th: BringupVCU118FPGATestHarnessImp, port: TLMemPort) => {
+  case (th: BringupVCU118FPGATestHarnessImp, port: TLMemPort, chipId: Int) => {
     val tsiBundles = th.bringupOuter.tsiDdrClient.out.map(_._1)
     val tsiDdrClientBundle = Wire(new HeterogeneousBag(tsiBundles.map(_.cloneType)))
     tsiBundles.zip(tsiDdrClientBundle).foreach { case (bundle, io) => bundle <> io }
     tsiDdrClientBundle <> port.io
   }
-  case (th: BringupVCU118FPGATestHarnessImp, port: TSIHostWidgetPort) => {
+  case (th: BringupVCU118FPGATestHarnessImp, port: TSIHostWidgetPort, chipId: Int) => {
     th.bringupOuter.io_tsi_serial_bb.bundle <> port.io
   }
 })
diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
index 5d71c1bd..999c8877 100644
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -28,8 +28,8 @@ import chipyard.iobinders._
 case object HarnessBinders extends Field[HarnessBinderFunction]({case _ => })
 
 object ApplyHarnessBinders {
-  def apply(th: HasHarnessInstantiators, ports: Seq[Port[_]])(implicit p: Parameters): Unit = {
-    ports.foreach(port => p(HarnessBinders)(th, port))
+  def apply(th: HasHarnessInstantiators, ports: Seq[Port[_]], chipId: Int)(implicit p: Parameters): Unit = {
+    ports.foreach(port => p(HarnessBinders)(th, port, chipId))
   }
 }
 
@@ -41,14 +41,14 @@ class HarnessBinder[T <: HasHarnessInstantiators, S <: Port[_]](
 
 
 class WithGPIOTiedOff extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: GPIOPort) => {
+  case (th: HasHarnessInstantiators, port: GPIOPort, chipId: Int) => {
     port.io <> AnalogConst(0)
   }
 })
 
 // DOC include start: WithUARTAdapter
 class WithUARTAdapter extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: UARTPort) => {
+  case (th: HasHarnessInstantiators, port: UARTPort, chipId: Int) => {
     val div = (th.getHarnessBinderClockFreqMHz.toDouble * 1000000 / port.io.c.initBaudRate.toDouble).toInt
     UARTAdapter.connect(Seq(port.io), div, false)
   }
@@ -56,7 +56,7 @@ class WithUARTAdapter extends HarnessBinder({
 // DOC include end: WithUARTAdapter
 
 class WithSimSPIFlashModel(rdOnly: Boolean = true) extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: SPIFlashPort) => {
+  case (th: HasHarnessInstantiators, port: SPIFlashPort, chipId: Int) => {
     val spi_mem = Module(new SimSPIFlashModel(port.params.fSize, port.spiId, rdOnly)).suggestName(s"spi_mem${port.spiId}")
     spi_mem.io.sck := port.io.sck
     require(port.params.csWidth == 1, "I don't know what to do with your extra CS bits. Fix me please.")
@@ -67,7 +67,7 @@ class WithSimSPIFlashModel(rdOnly: Boolean = true) extends HarnessBinder({
 })
 
 class WithSimBlockDevice extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: BlockDevicePort) => {
+  case (th: HasHarnessInstantiators, port: BlockDevicePort, chipId: Int) => {
     val sim_blkdev = Module(new SimBlockDevice(port.params))
     sim_blkdev.io.bdev <> port.io.bits
     sim_blkdev.io.clock := port.io.clock
@@ -76,7 +76,7 @@ class WithSimBlockDevice extends HarnessBinder({
 })
 
 class WithBlockDeviceModel extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: BlockDevicePort) => {
+  case (th: HasHarnessInstantiators, port: BlockDevicePort, chipId: Int) => {
     val blkdev_model = Module(new BlockDeviceModel(16, port.params))
     blkdev_model.io <> port.io.bits
     blkdev_model.clock := port.io.clock
@@ -85,19 +85,19 @@ class WithBlockDeviceModel extends HarnessBinder({
 })
 
 class WithLoopbackNIC extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: NICPort) => {
+  case (th: HasHarnessInstantiators, port: NICPort, chipId: Int) => {
     withClock(port.io.clock) { NicLoopback.connect(port.io.bits, port.params) }
   }
 })
 
 class WithSimNetwork extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: NICPort) => {
+  case (th: HasHarnessInstantiators, port: NICPort, chipId: Int) => {
     withClock(port.io.clock) { SimNetwork.connect(Some(port.io.bits), port.io.clock, th.harnessBinderReset.asBool) }
   }
 })
 
 class WithSimAXIMem extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: AXI4MemPort) => {
+  case (th: HasHarnessInstantiators, port: AXI4MemPort, chipId: Int) => {
     val mem = LazyModule(new SimAXIMem(port.edge, size=port.params.master.size)(Parameters.empty))
     withClock(port.io.clock) { Module(mem.module) }
     mem.io_axi4.head <> port.io
@@ -105,13 +105,13 @@ class WithSimAXIMem extends HarnessBinder({
 })
 
 class WithBlackBoxSimMem(additionalLatency: Int = 0) extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: AXI4MemPort) => {
+  case (th: HasHarnessInstantiators, port: AXI4MemPort, chipId: Int) => {
     // TODO FIX: This currently makes each SimDRAM contain the entire memory space
     val memSize = port.params.master.size
     val memBase = port.params.master.base
     val lineSize = 64 // cache block size
     val clockFreq = port.clockFreqMHz
-    val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, memBase, port.edge.bundle, th.p(MultiChipIdx))).suggestName("simdram")
+    val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, memBase, port.edge.bundle, chipId)).suggestName("simdram")
 
     mem.io.clock := port.io.clock
     mem.io.reset := th.harnessBinderReset.asAsyncReset
@@ -138,7 +138,7 @@ class WithBlackBoxSimMem(additionalLatency: Int = 0) extends HarnessBinder({
 })
 
 class WithSimAXIMMIO extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: AXI4MMIOPort) => {
+  case (th: HasHarnessInstantiators, port: AXI4MMIOPort, chipId: Int) => {
     val mmio_mem = LazyModule(new SimAXIMem(port.edge, size = port.params.size)(Parameters.empty))
     withClock(port.io.clock) { Module(mmio_mem.module).suggestName("mmio_mem") }
     mmio_mem.io_axi4.head <> port.io.bits
@@ -146,13 +146,13 @@ class WithSimAXIMMIO extends HarnessBinder({
 })
 
 class WithTieOffInterrupts extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: ExtIntPort) => {
+  case (th: HasHarnessInstantiators, port: ExtIntPort, chipId: Int) => {
     port.io := 0.U
   }
 })
 
 class WithTieOffL2FBusAXI extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: AXI4InPort) => {
+  case (th: HasHarnessInstantiators, port: AXI4InPort, chipId: Int) => {
     port.io := DontCare
     port.io.bits.aw.valid := false.B
     port.io.bits.w.valid := false.B
@@ -163,7 +163,7 @@ class WithTieOffL2FBusAXI extends HarnessBinder({
 })
 
 class WithSimJTAGDebug extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: JTAGPort) => {
+  case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => {
     val dtm_success = WireInit(false.B)
     when (dtm_success) { th.success := true.B }
     val jtag_wire = Wire(new JTAGIO)
@@ -178,7 +178,7 @@ class WithSimJTAGDebug extends HarnessBinder({
 })
 
 class WithSimDMI extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: DMIPort) => {
+  case (th: HasHarnessInstantiators, port: DMIPort, chipId: Int) => {
     val dtm_success = WireInit(false.B)
     when (dtm_success) { th.success := true.B }
     val dtm = Module(new TestchipSimDTM()(Parameters.empty)).connect(th.harnessBinderClock, th.harnessBinderReset.asBool, port.io, dtm_success)
@@ -186,7 +186,7 @@ class WithSimDMI extends HarnessBinder({
 })
 
 class WithTiedOffJTAG extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: JTAGPort) => {
+  case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => {
     port.io.TCK := true.B.asClock
     port.io.TMS := true.B
     port.io.TDI := true.B
@@ -194,7 +194,7 @@ class WithTiedOffJTAG extends HarnessBinder({
 })
 
 class WithTiedOffDMI extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: DMIPort) => {
+  case (th: HasHarnessInstantiators, port: DMIPort, chipId: Int) => {
     port.io.dmi.req.valid := false.B
     port.io.dmi.req.bits := DontCare
     port.io.dmi.resp.ready := true.B
@@ -206,7 +206,7 @@ class WithTiedOffDMI extends HarnessBinder({
 // If tieoffs is specified, a list of serial portIds to tie off
 // If tieoffs is unspecified, ties off all serial ports
 class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: SerialTLPort) if (tieoffs.map(_.contains(port.portId)).getOrElse(true)) => {
+  case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (tieoffs.map(_.contains(port.portId)).getOrElse(true)) => {
     port.io match {
       case io: DecoupledSerialIO => io.out.ready := false.B; io.in.valid := false.B; io.in.bits := DontCare;
       case io: SourceSyncSerialIO => {
@@ -225,7 +225,7 @@ class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinde
 })
 
 class WithSimTSIOverSerialTL extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: SerialTLPort) if (port.portId == 0) => {
+  case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) if (port.portId == 0) => {
     port.io match {
       case io: InternalSyncSerialIO =>
       case io: ExternalSyncSerialIO => io.clock_in := th.harnessBinderClock
@@ -244,7 +244,7 @@ class WithSimTSIOverSerialTL extends HarnessBinder({
           ram.io.ser.in <> io.out
           io.in <> ram.io.ser.out
 
-          val success = SimTSI.connect(ram.io.tsi, clock, th.harnessBinderReset, th.p(MultiChipIdx))
+          val success = SimTSI.connect(ram.io.tsi, clock, th.harnessBinderReset, chipId)
           when (success) { th.success := true.B }
         }
       }
@@ -253,7 +253,7 @@ class WithSimTSIOverSerialTL extends HarnessBinder({
 })
 
 class WithSimUARTToUARTTSI extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: UARTPort) => {
+  case (th: HasHarnessInstantiators, port: UARTPort, chipId: Int) => {
     UARTAdapter.connect(Seq(port.io),
       baudrate=port.io.c.initBaudRate,
       clockFrequency=th.getHarnessBinderClockFreqHz.toInt,
@@ -262,7 +262,7 @@ class WithSimUARTToUARTTSI extends HarnessBinder({
 })
 
 class WithSimTSIToUARTTSI extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
+  case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
     val freq = th.getHarnessBinderClockFreqHz.toInt
     val uart_to_serial = Module(new UARTToSerial(freq, port.io.uart.c))
     val serial_width_adapter = Module(new SerialWidthAdapter(8, TSI.WIDTH))
@@ -276,27 +276,27 @@ class WithSimTSIToUARTTSI extends HarnessBinder({
 })
 
 class WithTraceGenSuccess extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: SuccessPort) => {
+  case (th: HasHarnessInstantiators, port: SuccessPort, chipId: Int) => {
     when (port.io) { th.success := true.B }
   }
 })
 
 class WithCospike extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: TracePort) => {
+  case (th: HasHarnessInstantiators, port: TracePort, chipId: Int) => {
     port.io.traces.zipWithIndex.map(t => SpikeCosim(t._1, t._2, port.cosimCfg))
   }
 })
 
 
 class WithCustomBootPinPlusArg extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: CustomBootPort) => {
+  case (th: HasHarnessInstantiators, port: CustomBootPort, chipId: Int) => {
     val pin = PlusArg("custom_boot_pin", width=1)
     port.io := pin
   }
 })
 
 class WithClockFromHarness extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: ClockPort) => {
+  case (th: HasHarnessInstantiators, port: ClockPort, chipId: Int) => {
 // DOC include start: HarnessClockInstantiatorEx
     port.io := th.harnessClockInstantiator.requestClockMHz(s"clock_${port.freqMHz}MHz", port.freqMHz)
 // DOC include end: HarnessClockInstantiatorEx
@@ -304,7 +304,7 @@ class WithClockFromHarness extends HarnessBinder({
 })
 
 class WithResetFromHarness extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: ResetPort) => {
+  case (th: HasHarnessInstantiators, port: ResetPort, chipId: Int) => {
     port.io := th.referenceReset.asAsyncReset
   }
 })
diff --git a/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala b/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala
index 35331715..b8674623 100644
--- a/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala
+++ b/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala
@@ -89,7 +89,7 @@ trait HasHarnessInstantiators {
     withClockAndReset (harnessBinderClock, harnessBinderReset) {
       lazyDuts.zipWithIndex.foreach {
         case (d: HasChipyardPorts, i: Int) => {
-          ApplyHarnessBinders(this, d.ports)(chipParameters(i))
+          ApplyHarnessBinders(this, d.ports, i)(chipParameters(i))
         }
         case _ =>
       }
diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
index 9cd6afd2..4f32880e 100644
--- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
@@ -38,10 +38,10 @@ class MultiHarnessBinder[T <: Port[_], S <: HasHarnessInstantiators](
 )(implicit tag0: ClassTag[T], tag1: ClassTag[S]) extends Config((site, here, up) => {
     // Override any HarnessBinders for chip0/chip1
     case MultiChipParameters(`chip0`) => new Config(
-      new HarnessBinder({case (th: S, port: T) if chip0portFn(port) => }) ++ up(MultiChipParameters(chip0))
+      new HarnessBinder({case (th: S, port: T, chipId: Int) if chip0portFn(port) => }) ++ up(MultiChipParameters(chip0))
     )
     case MultiChipParameters(`chip1`) => new Config(
-      new HarnessBinder({case (th: S, port: T) if chip1portFn(port) => }) ++ up(MultiChipParameters(chip1))
+      new HarnessBinder({case (th: S, port: T, chipId: Int) if chip1portFn(port) => }) ++ up(MultiChipParameters(chip1))
     )
     // Set the multiharnessbinder key
     case MultiHarnessBinders(`chip0`, `chip1`) => up(MultiHarnessBinders(chip0, chip1)) :+ {
diff --git a/generators/chipyard/src/main/scala/harness/package.scala b/generators/chipyard/src/main/scala/harness/package.scala
index d0366c55..d49c1119 100644
--- a/generators/chipyard/src/main/scala/harness/package.scala
+++ b/generators/chipyard/src/main/scala/harness/package.scala
@@ -6,6 +6,6 @@ import scala.collection.immutable.ListMap
 package object harness
 {
   import chipyard.iobinders.Port
-  type HarnessBinderFunction = PartialFunction[(HasHarnessInstantiators, Port[_]), Unit]
+  type HarnessBinderFunction = PartialFunction[(HasHarnessInstantiators, Port[_], Int), Unit]
   type MultiHarnessBinderFunction = (HasHarnessInstantiators, Seq[Port[_]], Seq[Port[_]]) => Unit
 }
diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
index 1cb365bd..bd662a27 100644
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -67,7 +67,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
 })
 
 class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
-  case (th: FireSim, port: SerialTLPort) => {
+  case (th: FireSim, port: SerialTLPort, chipId: Int) => {
     port.io match {
       case io: ExternalSyncSerialIO => {
         io.clock_in := th.harnessBinderClock
@@ -78,8 +78,8 @@ class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
         // This assumes that:
         // If ExtMem for the target is defined, then FASED bridge will be attached
         // If FASED bridge is attached, loadmem widget is present
-        val hasMainMemory = th.chipParameters(th.p(MultiChipIdx))(ExtMem).isDefined
-        val mainMemoryName = Option.when(hasMainMemory)(MainMemoryConsts.globalName(th.p(MultiChipIdx)))
+        val hasMainMemory = th.chipParameters(chipId)(ExtMem).isDefined
+        val mainMemoryName = Option.when(hasMainMemory)(MainMemoryConsts.globalName(chipId))
         TSIBridge(th.harnessBinderClock, ram.io.tsi.get, mainMemoryName, th.harnessBinderReset.asBool)(th.p)
       }
     }
@@ -87,26 +87,26 @@ class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
 })
 
 class WithNICBridge extends HarnessBinder({
-  case (th: FireSim, port: NICPort) => {
+  case (th: FireSim, port: NICPort, chipId: Int) => {
     NICBridge(port.io.clock, port.io.bits)(th.p)
   }
 })
 
 class WithUARTBridge extends HarnessBinder({
-  case (th: FireSim, port: UARTPort) =>
+  case (th: FireSim, port: UARTPort, chipId: Int) =>
     val uartSyncClock = th.harnessClockInstantiator.requestClockMHz("uart_clock", port.freqMHz)
     UARTBridge(uartSyncClock, port.io, th.harnessBinderReset.asBool, port.freqMHz)(th.p)
 })
 
 class WithBlockDeviceBridge extends HarnessBinder({
-  case (th: FireSim, port: BlockDevicePort) => {
+  case (th: FireSim, port: BlockDevicePort, chipId: Int) => {
     BlockDevBridge(port.io.clock, port.io.bits, th.harnessBinderReset.asBool)
   }
 })
 
 
 class WithFASEDBridge extends HarnessBinder({
-  case (th: FireSim, port: AXI4MemPort) => {
+  case (th: FireSim, port: AXI4MemPort, chipId: Int) => {
     val nastiKey = NastiParameters(port.io.bits.r.bits.data.getWidth,
                                    port.io.bits.ar.bits.addr.getWidth,
                                    port.io.bits.ar.bits.id.getWidth)
@@ -114,24 +114,24 @@ class WithFASEDBridge extends HarnessBinder({
       CompleteConfig(th.p(firesim.configs.MemModelKey),
         nastiKey,
         Some(AXI4EdgeSummary(port.edge)),
-        Some(MainMemoryConsts.globalName(th.p(MultiChipIdx)))))(th.p)
+        Some(MainMemoryConsts.globalName(chipId))))(th.p)
   }
 })
 
 class WithTracerVBridge extends HarnessBinder({
-  case (th: FireSim, port: TracePort) => {
+  case (th: FireSim, port: TracePort, chipId: Int) => {
     port.io.traces.map(tileTrace => TracerVBridge(tileTrace)(th.p))
   }
 })
 
 class WithCospikeBridge extends HarnessBinder({
-  case (th: FireSim, port: TracePort) => {
+  case (th: FireSim, port: TracePort, chipId: Int) => {
     port.io.traces.zipWithIndex.map(t => CospikeBridge(t._1, t._2, port.cosimCfg))
   }
 })
 
 class WithSuccessBridge extends HarnessBinder({
-  case (th: FireSim, port: SuccessPort) => {
+  case (th: FireSim, port: SuccessPort, chipId: Int) => {
     GroundTestBridge(th.harnessBinderClock, port.io)(th.p)
   }
 })

From 86f028ac783dd8327efd0283be68788afc21e7d0 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Wed, 27 Dec 2023 07:55:00 -0800
Subject: [PATCH 08/13] Update SimTSI API in spiketile

---
 generators/chipyard/src/main/resources/csrc/spiketile.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/generators/chipyard/src/main/resources/csrc/spiketile.cc b/generators/chipyard/src/main/resources/csrc/spiketile.cc
index 5483cf6b..dd02d55e 100644
--- a/generators/chipyard/src/main/resources/csrc/spiketile.cc
+++ b/generators/chipyard/src/main/resources/csrc/spiketile.cc
@@ -12,7 +12,7 @@
 
 #if __has_include("spiketile_tsi.h")
 #define SPIKETILE_HTIF_TSI
-extern htif_t* tsi;
+extern std::map<int, htif_t*> tsis;
 #endif
 #if __has_include("spiketile_dtm.h")
 #define SPIKETILE_HTIF_DTM
@@ -346,8 +346,8 @@ extern "C" void spike_tile(int hartid, char* isa,
   chipyard_simif_t* simif = tile->simif;
   processor_t* proc = tile->proc;
 #if defined(SPIKETILE_HTIF_TSI)
-  if (!simif->htif && tsi)
-    simif->htif = tsi;
+  if (!simif->htif && tsis.size() > 0 && tsis[0])
+    simif->htif = tsis[0];
 #endif
 #if defined(SPIKETILE_HTIF_DTM)
   if (!simif->htif && dtm)

From cce5122fd22dacda35dd97bb107c4a6cdee8322b Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Wed, 27 Dec 2023 12:05:26 -0800
Subject: [PATCH 09/13] Bump testchipip to fix memory leak

---
 generators/testchipip | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/generators/testchipip b/generators/testchipip
index e1fc05b0..b3b74435 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit e1fc05b09283524fc09bee7d3ff351b6f83825ca
+Subproject commit b3b744353875056cbe865d5b767e488713f4c7f1

From 8600640a40c232717acf6530c373a226c53a9fa8 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Thu, 28 Dec 2023 07:36:53 -0800
Subject: [PATCH 10/13] Bump verilator to v5.018

---
 conda-reqs/chipyard.yaml                      |   6 +-
 ...irements-esp-tools-linux-64.conda-lock.yml | 664 +++++++++---------
 ...ements-riscv-tools-linux-64.conda-lock.yml | 660 ++++++++---------
 sims/verilator/Makefile                       |   7 +-
 4 files changed, 680 insertions(+), 657 deletions(-)

diff --git a/conda-reqs/chipyard.yaml b/conda-reqs/chipyard.yaml
index cc63f613..564f05e3 100644
--- a/conda-reqs/chipyard.yaml
+++ b/conda-reqs/chipyard.yaml
@@ -23,8 +23,8 @@ dependencies:
     # bundle FireSim driver with deps into installer shell-script
     - constructor
 
-    - gcc<13
-    - gxx<13
+    - gcc<12
+    - gxx<12
     - sysroot_linux-64=2.17 # needed to match pre-built CI XRT glibc version
     - conda-gcc-specs
     - binutils
@@ -88,7 +88,7 @@ dependencies:
     - graphviz
     - expect
     - dtc
-    - verilator==5.008
+    - verilator==5.018
     - screen
     - elfutils
     - libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock
diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
index f5fc3fbf..f61642e8 100644
--- a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
+++ b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
@@ -9,7 +9,7 @@
 # To update a single package to the latest version compatible with the version constraints in the source:
 #     conda-lock lock  --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml --update PACKAGE
 # To re-solve the entire environment, e.g. after changing a version constraint in the source file:
-#     conda-lock -f /scratch/abejgonza/cy-fixes-1/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy-fixes-1/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml
+#     conda-lock -f /nscratch/jerryz/chipyard-proj/chipyard-master/conda-reqs/chipyard.yaml -f /nscratch/jerryz/chipyard-proj/chipyard-master/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml
 metadata:
   channels:
   - url: ucb-bar
@@ -21,12 +21,12 @@ metadata:
   - url: nodefaults
     used_env_vars: []
   content_hash:
-    linux-64: db7fdb1eff05509c5804999acd40af2d5f212a2f7d2eca69702241bfbebef70d
+    linux-64: ff6d08e475547b935387001d63d60acbd5f49e2b4fe52cca99a819e4d97a1861
   platforms:
   - linux-64
   sources:
-  - /scratch/abejgonza/cy-fixes-1/conda-reqs/chipyard.yaml
-  - /scratch/abejgonza/cy-fixes-1/conda-reqs/esp-tools.yaml
+  - /nscratch/jerryz/chipyard-proj/chipyard-master/conda-reqs/chipyard.yaml
+  - /nscratch/jerryz/chipyard-proj/chipyard-master/conda-reqs/esp-tools.yaml
 package:
 - category: main
   dependencies: {}
@@ -141,25 +141,25 @@ package:
 - category: main
   dependencies: {}
   hash:
-    md5: 1d7f6d1825bd6bf21ee04336ec87a777
-    sha256: 92bec8177aacfcd49a8e5bda49c10e4b77e239e9d58a0ca4ef31344a2be1fc82
+    md5: 2390dcf3fd78c2c426f1c5b6664fa4b7
+    sha256: 12904b795e5cb877ce6a7bb30feba9bfbe1dd38bd5f520e6af8d89a51bb6b6a6
   manager: conda
   name: libgcc-devel_linux-64
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/libgcc-devel_linux-64-12.3.0-h8bca6fd_103.conda
-  version: 12.3.0
+  url: https://conda.anaconda.org/conda-forge/noarch/libgcc-devel_linux-64-11.4.0-h922705a_103.conda
+  version: 11.4.0
 - category: main
   dependencies: {}
   hash:
-    md5: 3f784d2c059e960156d1ab3858cbf200
-    sha256: 8a78b0ab9f845a90d3b66a5d83e4e1131a236d1c5badd3660fb7c12daac796bf
+    md5: be10a739476d68c464101836773463f1
+    sha256: 4957848888d7a8cdc77c605357e759f0c9b08c18510f08a205f567666602ca2b
   manager: conda
   name: libstdcxx-devel_linux-64
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/libstdcxx-devel_linux-64-12.3.0-h8bca6fd_103.conda
-  version: 12.3.0
+  url: https://conda.anaconda.org/conda-forge/noarch/libstdcxx-devel_linux-64-11.4.0-h922705a_103.conda
+  version: 11.4.0
 - category: main
   dependencies: {}
   hash:
@@ -174,14 +174,14 @@ package:
 - category: main
   dependencies: {}
   hash:
-    md5: 5b874a5f133b1bd0c5f227eed4758fdb
-    sha256: 9aa01c1102811cae6f60efa9d17f8f44365791d53a712dce3fe9a0488b6f6c2f
+    md5: ca8ce27415e2e304ec35b3de2af12364
+    sha256: b6f56d6c0a95dbd27bdcd5c666781c58c037850cebbaf62536a4fdf2bdcf2a2e
   manager: conda
   name: open_pdks.sky130a
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.458_0_g8c68aca-20231104_052339.tar.bz2
-  version: 1.0.458_0_g8c68aca
+  url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.460_0_gfdb1863-20231104_052339.tar.bz2
+  version: 1.0.460_0_gfdb1863
 - category: main
   dependencies: {}
   hash:
@@ -196,14 +196,14 @@ package:
 - category: main
   dependencies: {}
   hash:
-    md5: 939e3e74d8be4dac89ce83b20de2492a
-    sha256: 0449138224adfa125b220154408419ec37c06b0b49f63c5954724325903ecf55
+    md5: 8dee24b8be2d9ff81e7bd4d7d97ff1b0
+    sha256: 04f2ab3e36f2015841551415bf16bf62933bd94b7085d4be5493b388e95a9c3d
   manager: conda
   name: tzdata
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2023c-h71feb2d_0.conda
-  version: 2023c
+  url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2023d-h0c530f3_0.conda
+  version: 2023d
 - category: main
   dependencies:
     font-ttf-dejavu-sans-mono: ''
@@ -371,14 +371,14 @@ package:
   dependencies:
     libgcc-ng: '>=12'
   hash:
-    md5: d459949bc10f64dee1595c176c2e6291
-    sha256: 6b0eee827bade11c2964a05867499a50ad2a9d1b14dfe18fb867a3bc9357f56f
+    md5: f5842b88e9cbfa177abfaeacd457a45d
+    sha256: b68b0611d1c9d0222b56d5fe3d634e7a26979c3aef30f5f48b1593e7249e8f7a
   manager: conda
   name: c-ares
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/c-ares-1.23.0-hd590300_0.conda
-  version: 1.23.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/c-ares-1.24.0-hd590300_0.conda
+  version: 1.24.0
 - category: main
   dependencies:
     libgcc-ng: '>=12'
@@ -567,15 +567,15 @@ package:
   version: '1.18'
 - category: main
   dependencies:
-    libgcc-ng: '>=7.5.0'
+    libgcc-ng: '>=12'
   hash:
-    md5: 6f8720dff19e17ce5d48cfe7f3d2f0a3
-    sha256: 8c9635aa0ea28922877dc96358f9547f6a55fc7e2eb75a556b05f1725496baf9
+    md5: 172bf1cd1ff8629f2b1179945ed45055
+    sha256: 1cd6048169fa0395af74ed5d8f1716e22c19a81a8a36f934c110ca3ad4dd27b4
   manager: conda
   name: libev
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/libev-4.33-h516909a_1.tar.bz2
+  url: https://conda.anaconda.org/conda-forge/linux-64/libev-4.33-hd590300_2.conda
   version: '4.33'
 - category: main
   dependencies:
@@ -627,15 +627,15 @@ package:
   version: 13.2.0
 - category: main
   dependencies:
-    libgcc-ng: '>=10.3.0'
+    libgcc-ng: '>=12'
   hash:
-    md5: b62b52da46c39ee2bc3c162ac7f1804d
-    sha256: 6a81ebac9f1aacdf2b4f945c87ad62b972f0f69c8e0981d68e111739e6720fd7
+    md5: d66573916ffcf376178462f1b61c941e
+    sha256: 8ac2f6a9f186e76539439e50505d98581472fedb347a20e7d1f36429849f05c9
   manager: conda
   name: libiconv
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/libiconv-1.17-h166bdaf_0.tar.bz2
+  url: https://conda.anaconda.org/conda-forge/linux-64/libiconv-1.17-hd590300_2.conda
   version: '1.17'
 - category: main
   dependencies:
@@ -663,16 +663,16 @@ package:
   version: 2.0.1
 - category: main
   dependencies:
-    libgcc-ng: '>=12.3.0'
+    libgcc-ng: '>=11.4.0'
   hash:
-    md5: eda05ab0db8f8490945fd99244183e3a
-    sha256: 903c5786e0379da751e297dbe603be19b030994bac3caa74b3a596c1858c0296
+    md5: e6f89a7be0ec320c1b1746971045b0e7
+    sha256: c4c5c87f5c717e83299740f6a20393f9a131f05e2e9df63faafd6bb71dc58346
   manager: conda
   name: libsanitizer
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/libsanitizer-12.3.0-h0f45ef3_3.conda
-  version: 12.3.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/libsanitizer-11.4.0-h4dcbe23_3.conda
+  version: 11.4.0
 - category: main
   dependencies:
     libgcc-ng: '>=7.5.0'
@@ -757,6 +757,18 @@ package:
   platform: linux-64
   url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-base-1.3.1-hd590300_0.conda
   version: 1.3.1
+- category: main
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-    sha256: 0040b85370375694ae48d21af3e14471f78578fb22cd284c80da3741def0ad4a
+    md5: aaafd70a6934549210865f558a0eee96
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   manager: conda
   name: types-awscrt
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/types-awscrt-0.19.19-pyhd8ed1ab_0.conda
-  version: 0.19.19
+  url: https://conda.anaconda.org/conda-forge/noarch/types-awscrt-0.20.0-pyhd8ed1ab_0.conda
+  version: 0.20.0
 - category: main
   dependencies:
     cffi: ''
@@ -4651,21 +4678,6 @@ package:
   platform: linux-64
   url: https://conda.anaconda.org/conda-forge/linux-64/ukkonen-1.0.1-py39h7633fee_4.conda
   version: 1.0.1
-- category: main
-  dependencies:
-    distlib: <1,>=0.3.7
-    filelock: <4,>=3.12.2
-    platformdirs: <5,>=3.9.1
-    python: '>=3.8'
-  hash:
-    md5: db990278c2c00b268eed778de44f6057
-    sha256: ad661ae59c64bd73c25dfadb00c601659f4d9cafbf428e36a690075e52bac96a
-  manager: conda
-  name: virtualenv
-  optional: false
-  platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.24.7-pyhd8ed1ab_0.conda
-  version: 20.24.7
 - category: main
   dependencies:
     libgcc-ng: '>=9.3.0'
@@ -4742,21 +4754,21 @@ package:
     aws-c-http: '>=0.7.14,<0.7.15.0a0'
     aws-c-io: '>=0.13.36,<0.13.37.0a0'
     aws-c-mqtt: '>=0.9.10,<0.9.11.0a0'
-    aws-c-s3: '>=0.4.3,<0.4.4.0a0'
+    aws-c-s3: '>=0.4.4,<0.4.5.0a0'
     aws-checksums: '>=0.1.17,<0.1.18.0a0'
     libgcc-ng: '>=12'
     python: '>=3.9,<3.10.0a0'
     python_abi: 3.9.* *_cp39
-    s2n: '>=1.3.56,<1.3.57.0a0'
+    s2n: '>=1.4.0,<1.4.1.0a0'
   hash:
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-    sha256: b30260ea6484450ad8f5e2ad0cc342302ef199d6ee55f57c1c78fbb8c8b7dad6
+    md5: 111dc2570e8dd2eebecbfd8be3bc4616
+    sha256: 22fc0c664015c56fd5d96c93a5abd04a51b76b69b21981afd9ed521c72e64b73
   manager: conda
   name: awscrt
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/awscrt-0.19.18-py39h13f1633_0.conda
-  version: 0.19.18
+  url: https://conda.anaconda.org/conda-forge/linux-64/awscrt-0.19.19-py39hf0530f4_2.conda
+  version: 0.19.19
 - category: main
   dependencies:
     python: '>=3.6'
@@ -4778,14 +4790,14 @@ package:
     types-awscrt: ''
     typing_extensions: '>=4.1.0'
   hash:
-    md5: 3e24267b0fce04a61f7532f3096c45a5
-    sha256: 5e0daa0d40c5a6ea3b3798d31e0ae6bdc1d53c487e59153e5e4d9ee8c2ccc47c
+    md5: 75715c2695eb5d1da023a79140e923cd
+    sha256: e539bb5b339fc2136b086ce084fbf7b8c8f694d0c6ac30db2565c426bcdf28da
   manager: conda
   name: botocore-stubs
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.33.5-pyhd8ed1ab_0.conda
-  version: 1.33.5
+  url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.34.11-pyhd8ed1ab_0.conda
+  version: 1.34.11
 - category: main
   dependencies:
     msgpack-python: '>=0.5.2'
@@ -4881,14 +4893,14 @@ package:
     python: '>=3.6'
     ukkonen: ''
   hash:
-    md5: 3ef8e9bab1bfaf900bb0a5db8c0c742c
-    sha256: 0783aa58f43d1c113a2ec300a29ba3313184056f9893671c75037fbadaf9e546
+    md5: 93c8f8ceb83827d88deeba796f07fba7
+    sha256: ce2a64c18221af96226be23278d81f22ff9f64b3c047d8865590f6718915303f
   manager: conda
   name: identify
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/identify-2.5.32-pyhd8ed1ab_0.conda
-  version: 2.5.32
+  url: https://conda.anaconda.org/conda-forge/noarch/identify-2.5.33-pyhd8ed1ab_0.conda
+  version: 2.5.33
 - category: main
   dependencies:
     importlib_metadata: ''
@@ -4957,14 +4969,14 @@ package:
     python: '>=3.6'
     requests: <3,>=2.0.0
   hash:
-    md5: 4b2d7e21aa309356a9396d54800cd271
-    sha256: 8a37a7c3efae510b90669cbae7b4f736477361406028953cd804d09a2d24c53a
+    md5: 9d9b0ef23f5dbe0d612ca037b9bfb410
+    sha256: e0eb5606b4a164964d663d7a215ac9cd18db1ce1eca544aa61348e0a2bda94a9
   manager: conda
   name: msal
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/msal-1.25.0-pyhd8ed1ab_0.conda
-  version: 1.25.0
+  url: https://conda.anaconda.org/conda-forge/noarch/msal-1.26.0-pyhd8ed1ab_0.conda
+  version: 1.26.0
 - category: main
   dependencies:
     alsa-lib: '>=1.2.9,<1.2.10.0a0'
@@ -5006,14 +5018,14 @@ package:
     python_abi: 3.9.* *_cp39
     pytz: '>=2020.1'
   hash:
-    md5: 961b398d8c421a3752e26f01f2dcbdac
-    sha256: cb67f58e2a5c3c5f033e5901dbc067fcf8b1caebb8c9afd728471c9e75f2073f
+    md5: dcfd2f15c6f8f0bbf234412b18a2a5d0
+    sha256: 3344059c6df1a07e9e5824990c53f8ac4ee7a19a209e33f0009b5af266844d2b
   manager: conda
   name: pandas
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/pandas-2.1.3-py39hddac248_0.conda
-  version: 2.1.3
+  url: https://conda.anaconda.org/conda-forge/linux-64/pandas-2.1.4-py39hddac248_0.conda
+  version: 2.1.4
 - category: main
   dependencies:
     cairo: '>=1.16.0,<2.0a0'
@@ -5041,29 +5053,29 @@ package:
     pynacl: '>=1.5'
     python: '>=3.6'
   hash:
-    md5: 8d4563992b27cdb8e673d1ca16962c9d
-    sha256: 9139c13cb7ea5729af862db5fb0523daa5900b9b4fa36637cd7f9c01be665f80
+    md5: a5e792523b028b06d7ce6e65a6cd4a33
+    sha256: 2e66359261954a79b66858c30e69ea6dd4380bf8bd733940527386b25e31dd13
   manager: conda
   name: paramiko
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/paramiko-3.3.1-pyhd8ed1ab_0.conda
-  version: 3.3.1
+  url: https://conda.anaconda.org/conda-forge/noarch/paramiko-3.4.0-pyhd8ed1ab_0.conda
+  version: 3.4.0
 - category: main
   dependencies:
     annotated-types: '>=0.4.0'
-    pydantic-core: 2.14.5
+    pydantic-core: 2.14.6
     python: '>=3.7'
     typing-extensions: '>=4.6.1'
   hash:
-    md5: 3f908ebfccbfd09946961862d26bb9af
-    sha256: e3baa6424af931d8d7c5a0554b24d85faf3471df8036181d598065beed3096de
+    md5: 3569001fd8b37e542aaefdf5de124e19
+    sha256: 07ec778cbf17737b740f0547fb5cba91a7bff52945fe637287458e4119c58ffe
   manager: conda
   name: pydantic
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/pydantic-2.5.2-pyhd8ed1ab_0.conda
-  version: 2.5.2
+  url: https://conda.anaconda.org/conda-forge/noarch/pydantic-2.5.3-pyhd8ed1ab_0.conda
+  version: 2.5.3
 - category: main
   dependencies:
     cryptography: '>=38.0.0,<41'
@@ -5113,16 +5125,16 @@ package:
 - category: main
   dependencies:
     botocore: '>=1.33.2,<2.0a.0'
-    python: '>=3.7'
+    python: '>=3.8'
   hash:
-    md5: 75e12933f4bf755c9cdd37072bcb6203
-    sha256: 2e5679abcec8eb646df37518ecdbdaa224d7ff5295a1e56707317d52b47d9c79
+    md5: 2d52125a7fe49248ce5e883fed6c935a
+    sha256: 5f1fccbbc0460971f12dda7ab0465d8f6037486042d156b611881e57d218ce95
   manager: conda
   name: s3transfer
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/s3transfer-0.8.2-pyhd8ed1ab_0.conda
-  version: 0.8.2
+  url: https://conda.anaconda.org/conda-forge/noarch/s3transfer-0.10.0-pyhd8ed1ab_0.conda
+  version: 0.10.0
 - category: main
   dependencies:
     attrs: ''
@@ -5169,7 +5181,7 @@ package:
   version: 3.3.1
 - category: main
   dependencies:
-    awscrt: 0.19.18
+    awscrt: '>=0.19.18,<=0.19.19'
     colorama: '>=0.2.5,<0.4.7'
     cryptography: '>=3.3.2,<=40.0.2'
     distro: '>=1.5.0,<1.9.0'
@@ -5184,29 +5196,29 @@ package:
     ruamel.yaml.clib: '>=0.2.0,<=0.2.7'
     urllib3: '>=1.25.4,<1.27'
   hash:
-    md5: 5ffefcaa01088d683a89ed416cee51be
-    sha256: 272e0c846b7288e179e1a58ce18a5ec1d8bd4f3a0829df27dbe4ebe799ec3f3f
+    md5: 602c85ef4db55f9b4b34c5bb6aaa2795
+    sha256: 11a001f8ac7000eaaa9f5c3e6d9978abf263f5ad8487a15ef8676bdc1fc1a7e7
   manager: conda
   name: awscli
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/awscli-2.14.4-py39hf3d152e_0.conda
-  version: 2.14.4
+  url: https://conda.anaconda.org/conda-forge/linux-64/awscli-2.15.6-py39hf3d152e_0.conda
+  version: 2.15.6
 - category: main
   dependencies:
-    botocore: '>=1.33.4,<1.34.0'
+    botocore: '>=1.34.11,<1.35.0'
     jmespath: '>=0.7.1,<2.0.0'
-    python: '>=3.7'
-    s3transfer: '>=0.8.2,<0.9.0'
+    python: '>=3.8'
+    s3transfer: '>=0.10.0,<0.11.0'
   hash:
-    md5: 914d59cf685448451de9ac736cb0fb2a
-    sha256: cb63cadfb3c593cb7295b14450e4310af88d32dc1bbf185ec82a325a12e86f28
+    md5: b1256264fc531fca35aabab7d517438a
+    sha256: b4d3415b4beee1623c02b7ddc593ae7ca5c5843c943424a73b7648e05858e008
   manager: conda
   name: boto3
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.33.4-pyhd8ed1ab_0.conda
-  version: 1.33.4
+  url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.34.11-pyhd8ed1ab_0.conda
+  version: 1.34.11
 - category: main
   dependencies:
     cachecontrol: 0.13.1 pyhd8ed1ab_0
@@ -5245,14 +5257,14 @@ package:
     urllib3: '>=1.26.0'
     websocket-client: '>=0.32.0'
   hash:
-    md5: c95d23d8bae7e21491868cc7772d7c73
-    sha256: 7c3031602e92fd7682302ef98a45bdf7374d48a849cdd3900b7c68a32d162177
+    md5: aec5f308cb9055e83c59afecd5fcb58a
+    sha256: b9bf5990dc968123e5817096daddd2105857cfd4c5b94c0937d929bc74fc7a31
   manager: conda
   name: docker-py
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/docker-py-6.1.3-pyhd8ed1ab_0.conda
-  version: 6.1.3
+  url: https://conda.anaconda.org/conda-forge/noarch/docker-py-7.0.0-pyhd8ed1ab_0.conda
+  version: 7.0.0
 - category: main
   dependencies:
     atk-1.0: '>=2.36.0'
@@ -5383,18 +5395,18 @@ package:
     cfgv: '>=2.0.0'
     identify: '>=1.0.0'
     nodeenv: '>=0.11.1'
-    python: '>=3.8'
+    python: '>=3.9'
     pyyaml: '>=5.1'
     virtualenv: '>=20.10.0'
   hash:
-    md5: 964e3d762e427661c59263435a14c492
-    sha256: 51a4a17334a15ec92805cd075776563ff93b3b6c20732c4cb607c98a761ae02f
+    md5: 473a7cfca197da0a10cff3f6dded7d4b
+    sha256: 7d1f4b4a2eb4946b5808769642c5f643788c3a9e090f1c02a6c63f8794fb3d54
   manager: conda
   name: pre-commit
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.5.0-pyha770c72_0.conda
-  version: 3.5.0
+  url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.6.0-pyha770c72_0.conda
+  version: 3.6.0
 - category: main
   dependencies:
     __unix: ''
@@ -5416,14 +5428,14 @@ package:
     python: '>=3.7,<4.0'
     typing-extensions: <5,>=4.4
   hash:
-    md5: d9f3ca99e7d10b05ead04edcdcb7e0cb
-    sha256: 1bf5fa0d34e4de0843eaa82311e3dd680fdbe02cd74a6945f9b662f504bbcd08
+    md5: 9fabf343ed3cdb5803480768e6338826
+    sha256: 6cdad8582e270b88147295e9ec4817bdcda14212098efa77165a96870a31bbf4
   manager: conda
   name: aws-sam-translator
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/aws-sam-translator-1.81.0-pyhd8ed1ab_0.conda
-  version: 1.81.0
+  url: https://conda.anaconda.org/conda-forge/noarch/aws-sam-translator-1.82.0-pyhd8ed1ab_0.conda
+  version: 1.82.0
 - category: main
   dependencies:
     azure-core: <2.0.0,>=1.23.0
@@ -5446,14 +5458,14 @@ package:
     python: ''
     typing_extensions: ''
   hash:
-    md5: 23cf1bb1fb33251d3f0caf4198a90782
-    sha256: 44363a8ede827c4bac4c1e6535461ab6f12a19c658dff0a4d908c6d1e19c5d70
+    md5: 8e4b38b9dfc865ffb06a2bf2f3719d91
+    sha256: e8d31daecb364f893495430612721bb7b8f240e0834be5d1226810ace22cde68
   manager: conda
   name: boto3-stubs
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.33.5-pyhd8ed1ab_0.conda
-  version: 1.33.5
+  url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.34.11-pyhd8ed1ab_0.conda
+  version: 1.34.11
 - category: main
   dependencies:
     archspec: ''
@@ -5549,28 +5561,28 @@ package:
     python: '>=3.6'
     typing-extensions: ''
   hash:
-    md5: 01f46d3078f21041719d2c5fb83200de
-    sha256: ef1e693434f0d3c84389e459486d57abda67df228c2671d11285ba73baa5c11a
+    md5: 768ff0d711180b901b1490ebe7010ada
+    sha256: 9482dd403e24f5e5c155624de7d89f5521a97e8130f0a014899b12486a331a85
   manager: conda
   name: mypy-boto3-s3
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.33.2-pyhd8ed1ab_0.conda
-  version: 1.33.2
+  url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.34.0-pyhd8ed1ab_0.conda
+  version: 1.34.0
 - category: main
   dependencies:
     boto3: ''
     python: '>=3.6'
     typing-extensions: ''
   hash:
-    md5: 687d78daf8e04f4c5e5cfa92ead666c4
-    sha256: 2fecbcc276e13a119ec87602d9547aa537bf690724288d368ebf606351c19f67
+    md5: a810296f4cdd969085c1c3d78c846588
+    sha256: 3975c31a2c88ff9925922537bb653f84a1c91ed5152043788bc8cc49d541951d
   manager: conda
   name: mypy_boto3_ec2
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.33.0-pyhd8ed1ab_0.conda
-  version: 1.33.0
+  url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.34.4-pyhd8ed1ab_0.conda
+  version: 1.34.4
 - category: main
   dependencies:
     importlib_resources: '>=5.8,<7.0'
@@ -5604,7 +5616,7 @@ package:
   version: 0.4.2
 - category: main
   dependencies:
-    aws-sam-translator: '>=1.79.0'
+    aws-sam-translator: '>=1.82.0'
     jschema-to-python: '>=1.2.3,<1.3.dev0'
     jsonpatch: ''
     jsonschema: '>=3.0,<5'
@@ -5616,14 +5628,14 @@ package:
     sarif-om: '>=1.0.4,<1.1.dev0'
     sympy: '>=1.0.0'
   hash:
-    md5: 8fa5ac9497fc51cb02377e38500ce964
-    sha256: a77254900a3bc62e4c216f1223c9a14982db30e3c24a1b3fcc9cd9dcf3d1f5a4
+    md5: 6bf6c385031287e86a5821f57544fc12
+    sha256: deed7d4700694a25d440816d13de89468fe92dfc87ba506f3fee72b5d1131c75
   manager: conda
   name: cfn-lint
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.83.3-pyhd8ed1ab_0.conda
-  version: 0.83.3
+  url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.83.6-pyhd8ed1ab_0.conda
+  version: 0.83.6
 - category: main
   dependencies:
     colorama: ''
@@ -5699,14 +5711,14 @@ package:
     werkzeug: '>=0.5,!=2.2.0,!=2.2.1'
     xmltodict: ''
   hash:
-    md5: cd76850f625a821bd553380913baf5d6
-    sha256: 307ce3acd4c5c3b25f25e871924e96ee052c09a8a2832fcb7a89a2dc26f309cb
+    md5: 9447c344fde58f458a55b05729ae74aa
+    sha256: f0586fd89bcc4e7df9cd12e66627473bed9b4bc33814b01f48e6059628af2f6b
   manager: conda
   name: moto
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/moto-4.2.10-pyhd8ed1ab_0.conda
-  version: 4.2.10
+  url: https://conda.anaconda.org/conda-forge/noarch/moto-4.2.12-pyhd8ed1ab_0.conda
+  version: 4.2.12
 - category: main
   dependencies:
     livereload: '>=2.3.0'
diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
index 760a7911..9187da76 100644
--- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
+++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
@@ -9,7 +9,7 @@
 # To update a single package to the latest version compatible with the version constraints in the source:
 #     conda-lock lock  --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE
 # To re-solve the entire environment, e.g. after changing a version constraint in the source file:
-#     conda-lock -f /scratch/abejgonza/cy-fixes-1/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy-fixes-1/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml
+#     conda-lock -f /nscratch/jerryz/chipyard-proj/chipyard-master/conda-reqs/chipyard.yaml -f /nscratch/jerryz/chipyard-proj/chipyard-master/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml
 metadata:
   channels:
   - url: ucb-bar
@@ -21,12 +21,12 @@ metadata:
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     used_env_vars: []
   content_hash:
-    linux-64: f1bcd6ae2c33f314a2957b51c4689ea4e99a5ea5a2bf7e6d199abfb9f6ae65c4
+    linux-64: d002c72bdb6dab9165fd4a7c10f2c91ead3a528494418421f075feaf35d0646c
   platforms:
   - linux-64
   sources:
-  - /scratch/abejgonza/cy-fixes-1/conda-reqs/chipyard.yaml
-  - /scratch/abejgonza/cy-fixes-1/conda-reqs/riscv-tools.yaml
+  - /nscratch/jerryz/chipyard-proj/chipyard-master/conda-reqs/chipyard.yaml
+  - /nscratch/jerryz/chipyard-proj/chipyard-master/conda-reqs/riscv-tools.yaml
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   dependencies: {}
@@ -141,25 +141,25 @@ package:
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   optional: false
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-  url: https://conda.anaconda.org/conda-forge/noarch/libgcc-devel_linux-64-12.3.0-h8bca6fd_103.conda
-  version: 12.3.0
+  url: https://conda.anaconda.org/conda-forge/noarch/libgcc-devel_linux-64-11.4.0-h922705a_103.conda
+  version: 11.4.0
 - category: main
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+    md5: be10a739476d68c464101836773463f1
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   manager: conda
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   optional: false
   platform: linux-64
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-  version: 12.3.0
+  url: https://conda.anaconda.org/conda-forge/noarch/libstdcxx-devel_linux-64-11.4.0-h922705a_103.conda
+  version: 11.4.0
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+    md5: ca8ce27415e2e304ec35b3de2af12364
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   manager: conda
   name: open_pdks.sky130a
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.458_0_g8c68aca-20231104_052339.tar.bz2
-  version: 1.0.458_0_g8c68aca
+  url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.460_0_gfdb1863-20231104_052339.tar.bz2
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+    md5: 8dee24b8be2d9ff81e7bd4d7d97ff1b0
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   manager: conda
   name: tzdata
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2023c-h71feb2d_0.conda
-  version: 2023c
+  url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2023d-h0c530f3_0.conda
+  version: 2023d
 - category: main
   dependencies:
     font-ttf-dejavu-sans-mono: ''
@@ -371,14 +371,14 @@ package:
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+    md5: f5842b88e9cbfa177abfaeacd457a45d
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   manager: conda
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   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/c-ares-1.23.0-hd590300_0.conda
-  version: 1.23.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/c-ares-1.24.0-hd590300_0.conda
+  version: 1.24.0
 - category: main
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@@ -567,15 +567,15 @@ package:
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 - category: main
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+    libgcc-ng: '>=12'
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+    md5: 172bf1cd1ff8629f2b1179945ed45055
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   manager: conda
   name: libev
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/libev-4.33-h516909a_1.tar.bz2
+  url: https://conda.anaconda.org/conda-forge/linux-64/libev-4.33-hd590300_2.conda
   version: '4.33'
 - category: main
   dependencies:
@@ -627,15 +627,15 @@ package:
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 - category: main
   dependencies:
-    libgcc-ng: '>=10.3.0'
+    libgcc-ng: '>=12'
   hash:
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-    sha256: 6a81ebac9f1aacdf2b4f945c87ad62b972f0f69c8e0981d68e111739e6720fd7
+    md5: d66573916ffcf376178462f1b61c941e
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   manager: conda
   name: libiconv
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/libiconv-1.17-h166bdaf_0.tar.bz2
+  url: https://conda.anaconda.org/conda-forge/linux-64/libiconv-1.17-hd590300_2.conda
   version: '1.17'
 - category: main
   dependencies:
@@ -663,16 +663,16 @@ package:
   version: 2.0.1
 - category: main
   dependencies:
-    libgcc-ng: '>=12.3.0'
+    libgcc-ng: '>=11.4.0'
   hash:
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-    sha256: 903c5786e0379da751e297dbe603be19b030994bac3caa74b3a596c1858c0296
+    md5: e6f89a7be0ec320c1b1746971045b0e7
+    sha256: c4c5c87f5c717e83299740f6a20393f9a131f05e2e9df63faafd6bb71dc58346
   manager: conda
   name: libsanitizer
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/libsanitizer-12.3.0-h0f45ef3_3.conda
-  version: 12.3.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/libsanitizer-11.4.0-h4dcbe23_3.conda
+  version: 11.4.0
 - category: main
   dependencies:
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@@ -757,6 +757,18 @@ package:
   platform: linux-64
   url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-base-1.3.1-hd590300_0.conda
   version: 1.3.1
+- category: main
+  dependencies:
+    libgcc-ng: '>=12'
+  hash:
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+    sha256: 6ae68e0b86423ef188196fff6207ed0c8195dd84273cb5623b85aa08033a410c
+  manager: conda
+  name: libxcrypt
+  optional: false
+  platform: linux-64
+  url: https://conda.anaconda.org/conda-forge/linux-64/libxcrypt-4.4.36-hd590300_1.conda
+  version: 4.4.36
 - category: main
   dependencies:
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@@ -1128,14 +1140,14 @@ package:
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     libgcc-ng: '>=12'
   hash:
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   manager: conda
   name: aws-c-sdkutils
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/aws-c-sdkutils-0.1.12-h7f92143_6.conda
-  version: 0.1.12
+  url: https://conda.anaconda.org/conda-forge/linux-64/aws-c-sdkutils-0.1.13-h7f92143_0.conda
+  version: 0.1.13
 - category: main
   dependencies:
     aws-c-common: '>=0.9.10,<0.9.11.0a0'
@@ -1219,34 +1231,34 @@ package:
 - category: main
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-    libgcc-devel_linux-64: 12.3.0 h8bca6fd_103
-    libgcc-ng: '>=12.3.0'
-    libgomp: '>=12.3.0'
-    libsanitizer: 12.3.0 h0f45ef3_3
-    libstdcxx-ng: '>=12.3.0'
+    libgcc-devel_linux-64: 11.4.0 h922705a_103
+    libgcc-ng: '>=11.4.0'
+    libgomp: '>=11.4.0'
+    libsanitizer: 11.4.0 h4dcbe23_3
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   optional: false
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-  version: 12.3.0
+  url: https://conda.anaconda.org/conda-forge/linux-64/gcc_impl_linux-64-11.4.0-h7aa1c59_3.conda
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-  version: '1.7'
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 - category: main
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     libgcc-ng: '>=12'
     libstdcxx-ng: '>=12'
     libzlib: '>=1.2.13,<1.3.0a0'
-    openssl: '>=3.1.4,<4.0a0'
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   optional: false
   platform: linux-64
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+  url: https://conda.anaconda.org/conda-forge/linux-64/libnghttp2-1.58.0-h47da74e_1.conda
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+  url: https://conda.anaconda.org/conda-forge/linux-64/perl-5.32.1-7_hd590300_perl5.conda
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   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.33.4-pyhd8ed1ab_0.conda
-  version: 1.33.4
+  url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.34.11-pyhd8ed1ab_0.conda
+  version: 1.34.11
 - category: main
   dependencies:
     cachecontrol: 0.13.1 pyhd8ed1ab_0
@@ -5246,14 +5258,14 @@ package:
     urllib3: '>=1.26.0'
     websocket-client: '>=0.32.0'
   hash:
-    md5: c95d23d8bae7e21491868cc7772d7c73
-    sha256: 7c3031602e92fd7682302ef98a45bdf7374d48a849cdd3900b7c68a32d162177
+    md5: aec5f308cb9055e83c59afecd5fcb58a
+    sha256: b9bf5990dc968123e5817096daddd2105857cfd4c5b94c0937d929bc74fc7a31
   manager: conda
   name: docker-py
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/docker-py-6.1.3-pyhd8ed1ab_0.conda
-  version: 6.1.3
+  url: https://conda.anaconda.org/conda-forge/noarch/docker-py-7.0.0-pyhd8ed1ab_0.conda
+  version: 7.0.0
 - category: main
   dependencies:
     atk-1.0: '>=2.36.0'
@@ -5383,18 +5395,18 @@ package:
     cfgv: '>=2.0.0'
     identify: '>=1.0.0'
     nodeenv: '>=0.11.1'
-    python: '>=3.8'
+    python: '>=3.9'
     pyyaml: '>=5.1'
     virtualenv: '>=20.10.0'
   hash:
-    md5: 964e3d762e427661c59263435a14c492
-    sha256: 51a4a17334a15ec92805cd075776563ff93b3b6c20732c4cb607c98a761ae02f
+    md5: 473a7cfca197da0a10cff3f6dded7d4b
+    sha256: 7d1f4b4a2eb4946b5808769642c5f643788c3a9e090f1c02a6c63f8794fb3d54
   manager: conda
   name: pre-commit
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.5.0-pyha770c72_0.conda
-  version: 3.5.0
+  url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.6.0-pyha770c72_0.conda
+  version: 3.6.0
 - category: main
   dependencies:
     __unix: ''
@@ -5416,14 +5428,14 @@ package:
     python: '>=3.7,<4.0'
     typing-extensions: <5,>=4.4
   hash:
-    md5: d9f3ca99e7d10b05ead04edcdcb7e0cb
-    sha256: 1bf5fa0d34e4de0843eaa82311e3dd680fdbe02cd74a6945f9b662f504bbcd08
+    md5: 9fabf343ed3cdb5803480768e6338826
+    sha256: 6cdad8582e270b88147295e9ec4817bdcda14212098efa77165a96870a31bbf4
   manager: conda
   name: aws-sam-translator
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/aws-sam-translator-1.81.0-pyhd8ed1ab_0.conda
-  version: 1.81.0
+  url: https://conda.anaconda.org/conda-forge/noarch/aws-sam-translator-1.82.0-pyhd8ed1ab_0.conda
+  version: 1.82.0
 - category: main
   dependencies:
     azure-core: <2.0.0,>=1.23.0
@@ -5446,14 +5458,14 @@ package:
     python: ''
     typing_extensions: ''
   hash:
-    md5: 23cf1bb1fb33251d3f0caf4198a90782
-    sha256: 44363a8ede827c4bac4c1e6535461ab6f12a19c658dff0a4d908c6d1e19c5d70
+    md5: 8e4b38b9dfc865ffb06a2bf2f3719d91
+    sha256: e8d31daecb364f893495430612721bb7b8f240e0834be5d1226810ace22cde68
   manager: conda
   name: boto3-stubs
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.33.5-pyhd8ed1ab_0.conda
-  version: 1.33.5
+  url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.34.11-pyhd8ed1ab_0.conda
+  version: 1.34.11
 - category: main
   dependencies:
     archspec: ''
@@ -5550,28 +5562,28 @@ package:
     python: '>=3.6'
     typing-extensions: ''
   hash:
-    md5: 01f46d3078f21041719d2c5fb83200de
-    sha256: ef1e693434f0d3c84389e459486d57abda67df228c2671d11285ba73baa5c11a
+    md5: 768ff0d711180b901b1490ebe7010ada
+    sha256: 9482dd403e24f5e5c155624de7d89f5521a97e8130f0a014899b12486a331a85
   manager: conda
   name: mypy-boto3-s3
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.33.2-pyhd8ed1ab_0.conda
-  version: 1.33.2
+  url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.34.0-pyhd8ed1ab_0.conda
+  version: 1.34.0
 - category: main
   dependencies:
     boto3: ''
     python: '>=3.6'
     typing-extensions: ''
   hash:
-    md5: 687d78daf8e04f4c5e5cfa92ead666c4
-    sha256: 2fecbcc276e13a119ec87602d9547aa537bf690724288d368ebf606351c19f67
+    md5: a810296f4cdd969085c1c3d78c846588
+    sha256: 3975c31a2c88ff9925922537bb653f84a1c91ed5152043788bc8cc49d541951d
   manager: conda
   name: mypy_boto3_ec2
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.33.0-pyhd8ed1ab_0.conda
-  version: 1.33.0
+  url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.34.4-pyhd8ed1ab_0.conda
+  version: 1.34.4
 - category: main
   dependencies:
     importlib_resources: '>=5.8,<7.0'
@@ -5605,7 +5617,7 @@ package:
   version: 0.4.2
 - category: main
   dependencies:
-    aws-sam-translator: '>=1.79.0'
+    aws-sam-translator: '>=1.82.0'
     jschema-to-python: '>=1.2.3,<1.3.dev0'
     jsonpatch: ''
     jsonschema: '>=3.0,<5'
@@ -5617,14 +5629,14 @@ package:
     sarif-om: '>=1.0.4,<1.1.dev0'
     sympy: '>=1.0.0'
   hash:
-    md5: 8fa5ac9497fc51cb02377e38500ce964
-    sha256: a77254900a3bc62e4c216f1223c9a14982db30e3c24a1b3fcc9cd9dcf3d1f5a4
+    md5: 6bf6c385031287e86a5821f57544fc12
+    sha256: deed7d4700694a25d440816d13de89468fe92dfc87ba506f3fee72b5d1131c75
   manager: conda
   name: cfn-lint
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.83.3-pyhd8ed1ab_0.conda
-  version: 0.83.3
+  url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.83.6-pyhd8ed1ab_0.conda
+  version: 0.83.6
 - category: main
   dependencies:
     colorama: ''
@@ -5700,14 +5712,14 @@ package:
     werkzeug: '>=0.5,!=2.2.0,!=2.2.1'
     xmltodict: ''
   hash:
-    md5: cd76850f625a821bd553380913baf5d6
-    sha256: 307ce3acd4c5c3b25f25e871924e96ee052c09a8a2832fcb7a89a2dc26f309cb
+    md5: 9447c344fde58f458a55b05729ae74aa
+    sha256: f0586fd89bcc4e7df9cd12e66627473bed9b4bc33814b01f48e6059628af2f6b
   manager: conda
   name: moto
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/moto-4.2.10-pyhd8ed1ab_0.conda
-  version: 4.2.10
+  url: https://conda.anaconda.org/conda-forge/noarch/moto-4.2.12-pyhd8ed1ab_0.conda
+  version: 4.2.12
 - category: main
   dependencies:
     livereload: '>=2.3.0'
diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile
index 0341ff7d..86463fa1 100644
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -162,8 +162,7 @@ VERILATOR_NONCC_OPTS = \
 VERILATOR_CXXFLAGS = \
 	$(SIM_CXXFLAGS) \
 	$(RUNTIME_PROFILING_CFLAGS) \
-	-DVERILATOR \
-	-include $(build_dir)/$(long_name).plusArgs
+	-DVERILATOR
 
 VERILATOR_LDFLAGS = $(SIM_LDFLAGS)
 
@@ -194,13 +193,13 @@ model_mk_debug = $(model_dir_debug)/V$(TB).mk
 $(model_mk): $(sim_common_files) $(EXTRA_SIM_REQS)
 	rm -rf $(model_dir)
 	mkdir -p $(model_dir)
-	$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)"
+	$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir)
 	touch $@
 
 $(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS)
 	rm -rf $(model_dir_debug)
 	mkdir -p $(model_dir_debug)
-	$(VERILATOR) $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
+	$(VERILATOR) $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug)
 	touch $@
 
 #########################################################################################

From 5f2b2181c2e57cf90d0ea8de43542b2a92028aff Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Mon, 1 Jan 2024 11:42:37 -0800
Subject: [PATCH 11/13] Bump to verilator v5.020

---
 conda-reqs/chipyard.yaml                      |  2 +-
 ...irements-esp-tools-linux-64.conda-lock.yml | 26 +++++++++----------
 ...ements-riscv-tools-linux-64.conda-lock.yml | 26 +++++++++----------
 3 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/conda-reqs/chipyard.yaml b/conda-reqs/chipyard.yaml
index 564f05e3..ec49a0a4 100644
--- a/conda-reqs/chipyard.yaml
+++ b/conda-reqs/chipyard.yaml
@@ -88,7 +88,7 @@ dependencies:
     - graphviz
     - expect
     - dtc
-    - verilator==5.018
+    - verilator==5.020
     - screen
     - elfutils
     - libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock
diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
index f61642e8..f63afc45 100644
--- a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
+++ b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
@@ -21,7 +21,7 @@ metadata:
   - url: nodefaults
     used_env_vars: []
   content_hash:
-    linux-64: ff6d08e475547b935387001d63d60acbd5f49e2b4fe52cca99a819e4d97a1861
+    linux-64: de1e2d263317a6a0c7c45acb734d166b9975ff1a94cd138e3427bb7b7bdd8db4
   platforms:
   - linux-64
   sources:
@@ -2100,14 +2100,14 @@ package:
   dependencies:
     python: '>=3.7'
   hash:
-    md5: 3edfead7cedd1ab4400a6c588f3e75f8
-    sha256: 063639cd568f5c7a557b0fb1cc27f098598c0d8ff869088bfeb82934674f8821
+    md5: 5e4c0743c70186509d1412e03c2d8dfa
+    sha256: 77c7d03bdb243a048fff398cedc74327b7dc79169ebe3b4c8448b0331ea55fea
   manager: conda
   name: attrs
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/attrs-23.1.0-pyh71513ae_1.conda
-  version: 23.1.0
+  url: https://conda.anaconda.org/conda-forge/noarch/attrs-23.2.0-pyh71513ae_0.conda
+  version: 23.2.0
 - category: main
   dependencies:
     aws-c-common: '>=0.9.10,<0.9.11.0a0'
@@ -3398,14 +3398,14 @@ package:
     perl: ''
     python: ''
   hash:
-    md5: 6ecc6f19e3a0661c096d0e84015c8122
-    sha256: 582ae4513d3ef87d4b0c5d53a3a691575de2aabe8cc5a5554bb1db5bcd6a40b4
+    md5: 0b2929f84fe7d3a6117439507d5d50d9
+    sha256: 1d6af07d2d19be7adc296e8b6c43bd3eb12b48d8ab8e0cec566e8f9872661813
   manager: conda
   name: verilator
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/verilator-5.018-h4f9daa6_0.conda
-  version: '5.018'
+  url: https://conda.anaconda.org/conda-forge/linux-64/verilator-5.020-h7cd9344_0.conda
+  version: '5.020'
 - category: main
   dependencies:
     python: '>=3.8'
@@ -4061,14 +4061,14 @@ package:
     python: '>=3.7'
     tomli: '>=1.0.0'
   hash:
-    md5: 5bdca0aca30b0ee62bb84854e027eae0
-    sha256: 14e948e620ec87d9e62a8d9c21d40084b4805a939cfee322be7d457379dc96a0
+    md5: a9d145de8c5f064b5fa68fb34725d9f4
+    sha256: 8979721b7f86b183d21103f3ec2734783847d317c1b754f462f407efc7c60886
   manager: conda
   name: pytest
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/pytest-7.4.3-pyhd8ed1ab_0.conda
-  version: 7.4.3
+  url: https://conda.anaconda.org/conda-forge/noarch/pytest-7.4.4-pyhd8ed1ab_0.conda
+  version: 7.4.4
 - category: main
   dependencies:
     python: '>=3.6'
diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
index 9187da76..61cc9654 100644
--- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
+++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
@@ -21,7 +21,7 @@ metadata:
   - url: nodefaults
     used_env_vars: []
   content_hash:
-    linux-64: d002c72bdb6dab9165fd4a7c10f2c91ead3a528494418421f075feaf35d0646c
+    linux-64: ca6a27eca59955764c48c1f6e92b9c0d88ab3b0ce2cf79bc2b35e847e0aecff4
   platforms:
   - linux-64
   sources:
@@ -2100,14 +2100,14 @@ package:
   dependencies:
     python: '>=3.7'
   hash:
-    md5: 3edfead7cedd1ab4400a6c588f3e75f8
-    sha256: 063639cd568f5c7a557b0fb1cc27f098598c0d8ff869088bfeb82934674f8821
+    md5: 5e4c0743c70186509d1412e03c2d8dfa
+    sha256: 77c7d03bdb243a048fff398cedc74327b7dc79169ebe3b4c8448b0331ea55fea
   manager: conda
   name: attrs
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/attrs-23.1.0-pyh71513ae_1.conda
-  version: 23.1.0
+  url: https://conda.anaconda.org/conda-forge/noarch/attrs-23.2.0-pyh71513ae_0.conda
+  version: 23.2.0
 - category: main
   dependencies:
     aws-c-common: '>=0.9.10,<0.9.11.0a0'
@@ -3412,14 +3412,14 @@ package:
     perl: ''
     python: ''
   hash:
-    md5: 6ecc6f19e3a0661c096d0e84015c8122
-    sha256: 582ae4513d3ef87d4b0c5d53a3a691575de2aabe8cc5a5554bb1db5bcd6a40b4
+    md5: 0b2929f84fe7d3a6117439507d5d50d9
+    sha256: 1d6af07d2d19be7adc296e8b6c43bd3eb12b48d8ab8e0cec566e8f9872661813
   manager: conda
   name: verilator
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/verilator-5.018-h4f9daa6_0.conda
-  version: '5.018'
+  url: https://conda.anaconda.org/conda-forge/linux-64/verilator-5.020-h7cd9344_0.conda
+  version: '5.020'
 - category: main
   dependencies:
     python: '>=3.8'
@@ -4075,14 +4075,14 @@ package:
     python: '>=3.7'
     tomli: '>=1.0.0'
   hash:
-    md5: 5bdca0aca30b0ee62bb84854e027eae0
-    sha256: 14e948e620ec87d9e62a8d9c21d40084b4805a939cfee322be7d457379dc96a0
+    md5: a9d145de8c5f064b5fa68fb34725d9f4
+    sha256: 8979721b7f86b183d21103f3ec2734783847d317c1b754f462f407efc7c60886
   manager: conda
   name: pytest
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/pytest-7.4.3-pyhd8ed1ab_0.conda
-  version: 7.4.3
+  url: https://conda.anaconda.org/conda-forge/noarch/pytest-7.4.4-pyhd8ed1ab_0.conda
+  version: 7.4.4
 - category: main
   dependencies:
     python: '>=3.6'

From 41651edbdc206d63e248b48056b2bdfd0eb1d28c Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Mon, 1 Jan 2024 15:44:23 -0800
Subject: [PATCH 12/13] Bump firesim | fix testchipip segfaults

---
 fpga/src/main/scala/arty100t/HarnessBinders.scala             | 4 ++--
 .../chipyard/src/main/scala/harness/HarnessBinders.scala      | 2 +-
 generators/testchipip                                         | 2 +-
 sims/firesim                                                  | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala
index e8029884..7b1640ba 100644
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -107,7 +107,7 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
 
 // Maps the UART device to the on-board USB-UART
 class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: UARTPort) => {
+  case (th: HasHarnessInstantiators, port: UARTPort, chipId: Int) => {
     val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
     val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart")
     harnessIO <> port.io
@@ -126,7 +126,7 @@ class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends Ha
 class WithArty100TPMODUART extends WithArty100TUART("G2", "F3")
 
 class WithArty100TJTAG extends HarnessBinder({
-  case (th: HasHarnessInstantiators, port: JTAGPort) => {
+  case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => {
     val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
     val harnessIO = IO(chiselTypeOf(port.io)).suggestName("jtag")
     harnessIO <> port.io
diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
index 999c8877..d70519b3 100644
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -100,7 +100,7 @@ class WithSimAXIMem extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: AXI4MemPort, chipId: Int) => {
     val mem = LazyModule(new SimAXIMem(port.edge, size=port.params.master.size)(Parameters.empty))
     withClock(port.io.clock) { Module(mem.module) }
-    mem.io_axi4.head <> port.io
+    mem.io_axi4.head <> port.io.bits
   }
 })
 
diff --git a/generators/testchipip b/generators/testchipip
index b3b74435..263980a9 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit b3b744353875056cbe865d5b767e488713f4c7f1
+Subproject commit 263980a9f503e0e57705b6d31002077fa6269aa6
diff --git a/sims/firesim b/sims/firesim
index e9758935..c113e2d6 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit e975893595129c2682a72fb7e5898273fcc2d071
+Subproject commit c113e2d6001080749b20c5a60b67eb338267a823

From f84b2428d56bba8b47aac0c55716fbf08123837e Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Thu, 11 Jan 2024 16:40:57 -0800
Subject: [PATCH 13/13] Fix CanHaveClockTap

---
 .../chipyard/src/main/scala/clocking/CanHaveClockTap.scala    | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala b/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala
index 5d0ce538..9af30ddf 100644
--- a/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala
+++ b/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala
@@ -13,10 +13,10 @@ import freechips.rocketchip.prci._
 case object ClockTapKey extends Field[Boolean](true)
 
 trait CanHaveClockTap { this: BaseSubsystem =>
-  require(p(SubsystemDriveAsyncClockGroupsKey).isEmpty, "Subsystem asyncClockGroups must be undriven")
+  require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem must not drive clocks from IO")
   val clockTapNode = Option.when(p(ClockTapKey)) {
     val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap"))))
-    clockTap := ClockGroup() := asyncClockGroupsNode
+    clockTap := ClockGroup() := allClockGroupsNode
     clockTap
   }
   val clockTapIO = clockTapNode.map { node => InModuleBody {