wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

changing tutorial VLSI_TOP to RocketTile to save time

Browse Source
This commit is contained in:
Nayiri Krzysztofowicz
2023-03-12 19:04:14 -07:00
parent 02a0714117
commit dd7e221a45
3 changed files with 87 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
vlsi/tutorial.mk
View File

@@ -30,7 +30,10 @@ ifeq ($(tutorial),sky130-openroad)
TOOLS_CONF ?= example-openroad.yml
TECH_CONF ?= example-sky130.yml
DESIGN_CONF ?= example-designs/sky130-openroad.yml
EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, )
EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), \
example-designs/sky130-rocket.yml, \
$(if $(filter $(VLSI_TOP),RocketTile), \
example-designs/sky130-openroad-rockettile.yml, ))
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
VLSI_OBJ_DIR ?= build-sky130-openroad
# Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.