UART Working... Bumped to newer fpga-shells

2020-10-19 11:29:25 -07:00
parent 9ba4918cb8
commit dd358f45ab
6 changed files with 23 additions and 13 deletions
--- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
@@ -181,6 +181,9 @@ class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) exte
  val dutReset = harnessReset
  val success = false.B

+  childClock := harnessClock
+  childReset := harnessReset
+
  // harness binders are non-lazy
  _outer.topDesign match { case d: HasTestHarnessFunctions =>
    d.harnessFunctions.foreach(_(this))