Basic working with UART

2020-10-14 16:15:10 -07:00
parent 949d60597f
commit dcac9b79df
3 changed files with 98 additions and 26 deletions
--- a/fpga/src/main/scala/vcu118/Configs.scala
+++ b/fpga/src/main/scala/vcu118/Configs.scala
@@ -73,11 +73,11 @@ class FakeBringupConfig extends Config(
  new WithBringupUART ++
  //new WithBringupSPI ++
  //new WithBringupI2C ++
-  new WithBringupGPIO ++
-  new chipyard.iobinders.WithUARTIOCells ++
+  //new WithBringupGPIO ++
+  new WithUARTIOPassthrough ++
  //new WithSPICells ++
  //new WithI2CCells ++
-  new chipyard.iobinders.WithGPIOCells ++
+  //new chipyard.iobinders.WithGPIOCells ++
  //new WithBringupDDR ++
  new WithBringupPeripherals ++
  new chipyard.config.WithNoSubsystemDrivenClocks ++