Merge pull request #554 from ucb-bar/generator-unification-p1

Have FireChip use the standard Chipyard generator

generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala

@@ -11,7 +11,12 @@ private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptio
   override val options = Seq(
     new ShellOption[String](
       longOption = "legacy-configs",
-      toAnnotationSeq = a => Seq(new ConfigsAnnotation(a.split("_"))),
+      toAnnotationSeq = a => {
+        val split = a.split('.')
+        val packageName = split.init.mkString(".")
+        val configs     = split.last.split("_")
+        Seq(new ConfigsAnnotation(configs map { config => s"${packageName}.${config}" } ))
+      },
       helpText = "A string of underscore-delimited configs (configs have decreasing precendence from left to right).",
       shortOption = Some("LC")
     )

generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala

@@ -16,6 +16,7 @@ import freechips.rocketchip.stage.RocketChipOptions
 import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}
 import freechips.rocketchip.system.{RocketTestSuite, TestGeneration}
 import freechips.rocketchip.util.HasRocketChipStageUtils
+import freechips.rocketchip.tile.XLen
 
 import chipyard.TestSuiteHelper
 
@@ -30,9 +31,13 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS
   private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = {
     val annotations = mutable.ArrayBuffer[Annotation]()
     val suiteHelper = new TestSuiteHelper
-    suiteHelper.addRocketTestSuites
+    // Use Xlen as a proxy for detecting if we are a processor-like target
-    suiteHelper.addBoomTestSuites
+    // The underlying test suites expect this field to be defined
-    suiteHelper.addArianeTestSuites
+    if (p.lift(XLen).nonEmpty) {
+      suiteHelper.addRocketTestSuites
+      suiteHelper.addBoomTestSuites
+      suiteHelper.addArianeTestSuites
+    }
 
     // if hwacha parameter exists then generate its tests
     // TODO: find a more elegant way to do this. either through

generators/firechip/src/main/scala/FireSim.scala

@@ -29,6 +29,7 @@ object NodeIdx {
 }
 
 class FireSim(implicit val p: Parameters) extends RawModule {
+  freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary())
   val clockBridge = Module(new RationalClockBridge)
   val clock = clockBridge.io.clocks.head
   val reset = WireInit(false.B)

generators/firechip/src/main/scala/FireSimMulticlockPOC.scala

@@ -84,6 +84,7 @@ class FiresimMulticlockTopModule[+L <: DigitalTop](l: L) extends chipyard.Digita
 
 // Harness Definition
 class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule {
+  freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary())
   val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*))
   val refClock = clockBridge.io.clocks.head
   val reset = WireInit(false.B)

generators/firechip/src/main/scala/Generator.scala

@@ -1,73 +0,0 @@
-//See LICENSE for license details.
-
-package firesim.firesim
-
-import java.io.{File, FileWriter}
-
-import chisel3.RawModule
-import chisel3.internal.firrtl.{Circuit, Port}
-
-import freechips.rocketchip.diplomacy.{ValName, AutoBundle}
-import freechips.rocketchip.devices.debug.DebugIO
-import freechips.rocketchip.util.{ElaborationArtefacts}
-import freechips.rocketchip.system.DefaultTestSuites._
-import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
-import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.subsystem.RocketTilesKey
-import freechips.rocketchip.tile.XLen
-
-import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGeneratorUtilities}
-
-import scala.util.Try
-
-import chipyard.TestSuiteHelper
-
-trait HasTestSuites {
-  def addTestSuites(targetName: String, params: Parameters) {
-    val suiteHelper = new TestSuiteHelper
-    suiteHelper.addRocketTestSuites(params)
-    suiteHelper.addBoomTestSuites(params)
-    suiteHelper.addArianeTestSuites(params)
-    TestGeneration.addSuites(suiteHelper.suites.values.toSeq)
-    TestGeneration.addSuite(FastBlockdevTests)
-    TestGeneration.addSuite(SlowBlockdevTests)
-    if (!targetName.contains("NoNIC"))
-      TestGeneration.addSuite(NICLoopbackTests)
-
-    import hwacha.HwachaTestSuites._
-    if (Try(params(hwacha.HwachaNLanes)).getOrElse(0) > 0) {
-      TestGeneration.addSuites(rv64uv.map(_("p")))
-      TestGeneration.addSuites(rv64uv.map(_("vp")))
-      TestGeneration.addSuite(rv64sv("p"))
-      TestGeneration.addSuite(hwachaBmarks)
-    }
-  }
-}
-
-// Mixed into an App or into a TestSuite
-trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSuites {
-  /** Output software test Makefrags, which provide targets for integration testing. */
-  def generateTestSuiteMakefrags {
-    addTestSuites(names.topModuleClass, targetParams)
-    writeOutputFile(s"$longName.d", TestGeneration.generateMakeFrag) // Subsystem-specific test suites
-  }
-
-  // Output miscellaneous files produced as a side-effect of elaboration
-  def generateArtefacts {
-    // generate RC's artefacts
-    ElaborationArtefacts.files.foreach { case (extension, contents) =>
-      writeOutputFile(s"${longName}.${extension}", contents ())
-    }
-  }
-}
-
-object FireSimGenerator extends App with IsFireSimGeneratorLike {
-  override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
-  lazy val generatorArgs = GeneratorArgs(args)
-  lazy val genDir = new File(names.targetDir)
-  // The only reason this is not generateFirrtl; generateAnno is that we need to use a different
-  // JsonProtocol to properly write out the annotations. Fix once the generated are unified
-  elaborate
-  generateTestSuiteMakefrags
-  generateArtefacts
-}

generators/firechip/src/test/scala/ScalaTestSuite.scala

@@ -6,44 +6,34 @@ import java.io.File
 import scala.concurrent.{Future, Await, ExecutionContext}
 import scala.sys.process.{stringSeqToProcess, ProcessLogger}
 import scala.io.Source
+import org.scalatest.Suites
 
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.system.{RocketTestSuite, BenchmarkTestSuite}
 import freechips.rocketchip.system.TestGeneration._
 import freechips.rocketchip.system.DefaultTestSuites._
 
-import firesim.util.GeneratorArgs
-
 abstract class FireSimTestSuite(
     topModuleClass: String,
     targetConfigs: String,
     platformConfigs: String,
     N: Int = 8
-  ) extends firesim.TestSuiteCommon with IsFireSimGeneratorLike {
+  ) extends firesim.TestSuiteCommon {
   import scala.concurrent.duration._
   import ExecutionContext.Implicits.global
 
-  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
+  val topModuleProject = "firesim.firesim"
 
-  lazy val generatorArgs = GeneratorArgs(
+  val chipyardLongName = topModuleProject + "." + topModuleClass + "." + targetConfigs
-    midasFlowKind = "midas",
-    targetDir = "generated-src",
-    topModuleProject = "firesim.firesim",
-    topModuleClass = topModuleClass,
-    targetConfigProject = "firesim.firesim",
-    targetConfigs = targetConfigs ++ "_WithScalaTestFeatures",
-    platformConfigProject = "firesim.firesim",
-    platformConfigs = platformConfigs)
-
-  // From HasFireSimGeneratorUtilities
-  // For the firesim utilities to use the same directory as the test suite
-  override lazy val testDir = genDir
 
   // From TestSuiteCommon
-  val targetTuple = generatorArgs.tupleName
+  val targetTuple = s"$topModuleClass-$targetConfigs-$platformConfigs"
-  val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}",
+  val commonMakeArgs = Seq(s"DESIGN=${topModuleClass}",
-                           s"TARGET_CONFIG=${generatorArgs.targetConfigs}",
+                           s"TARGET_CONFIG=${targetConfigs}",
-                           s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}")
+                           s"PLATFORM_CONFIG=${platformConfigs}")
+
+  override lazy val genDir  = new File(firesimDir, s"generated-src/${chipyardLongName}")
+
 
   def invokeMlSimulator(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = {
     make((Seq(s"${outDir.getAbsolutePath}/${name}.%s".format(if (debug) "vpd" else "out"),
@@ -61,12 +51,6 @@ abstract class FireSimTestSuite(
     }
   }
 
-  //def runReplay(backend: String, replayBackend: String, name: String) = {
-  //  val dir = (new File(outDir, backend)).getAbsolutePath
-  //  (Seq("make", s"replay-$replayBackend",
-  //       s"SAMPLE=${dir}/${name}.sample", s"output_dir=$dir") ++ makeArgs).!
-  //}
-
   def runSuite(backend: String, debug: Boolean = false)(suite: RocketTestSuite) {
     // compile emulators
     behavior of s"${suite.makeTargetName} running on $backend"
@@ -83,20 +67,6 @@ abstract class FireSimTestSuite(
       results.flatten foreach { case (name, exitcode) =>
         it should s"pass $name" in { assert(exitcode == 0) }
       }
-      //replayBackends foreach { replayBackend =>
-      //  if (platformParams(midas.EnableSnapshot) && isCmdAvailable("vcs")) {
-      //    assert((Seq("make", s"vcs-$replayBackend") ++ makeArgs).! == 0) // compile vcs
-      //    suite.names foreach { name =>
-      //      it should s"replay $name in $replayBackend" in {
-      //        assert(runReplay(backend, replayBackend, s"$name$postfix") == 0)
-      //      }
-      //    }
-      //  } else {
-      //    suite.names foreach { name =>
-      //      ignore should s"replay $name in $backend"
-      //    }
-      //  }
-      //}
     } else {
       ignore should s"pass $backend"
     }
@@ -127,66 +97,24 @@ abstract class FireSimTestSuite(
   }
 
   clean
-  mkdirs
-  elaborate
-  generateTestSuiteMakefrags
-  generateArtefacts
   runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0"""))
-  //diffTracelog("rv64ui-p-simple.out")
   runSuite("verilator")(benchmarks)
-  runSuite("verilator")(FastBlockdevTests)
 }
 
 class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "WithSynthAsserts_BaseF1Config")
 class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig", "BaseF1Config")
-class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") {
+class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config")
-  runSuite("verilator")(NICLoopbackTests)
-}
-//class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") {
-//  runSuite("verilator")(NICLoopbackTests)
-//}
-// Disabled until RAM optimizations re-enabled in multiclock
-//class RamModelRocketF1Tests extends FireSimTestSuite("FireSim", "FireSimDualRocketConfig", "BaseF1Config_MCRams")
-//class RamModelBoomF1Tests extends FireSimTestSuite("FireSim", "FireSimBoomConfig", "BaseF1Config_MCRams")
-
 // Multiclock tests
 class RocketMulticlockF1Tests extends FireSimTestSuite(
   "FireSimMulticlockPOC",
   "FireSimQuadRocketMulticlockConfig",
   "WithSynthAsserts_BaseF1Config")
 
-// Jerry broke these -- damn it Jerry.
+class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config")
-//abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String)
+
-//    extends firesim.TestSuiteCommon with IsFireSimGeneratorLike {
+// This test suite only mirrors what is run in CI. CI invokes each test individually, using a testOnly call.
-//  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
+class CITests extends Suites(
-//
+  new RocketF1Tests,
-//  lazy val generatorArgs = GeneratorArgs(
+  new BoomF1Tests,
-//    midasFlowKind = "midas",
+  new RocketNICF1Tests,
-//    targetDir = "generated-src",
+  new RocketMulticlockF1Tests)
-//    topModuleProject = "firesim.firesim",
-//    topModuleClass = "FireSimTraceGen",
-//    targetConfigProject = "firesim.firesim",
-//    targetConfigs = targetConfig ++ "_WithScalaTestFeatures",
-//    platformConfigProject = "firesim.firesim",
-//    platformConfigs = platformConfig)
-//
-//  // From HasFireSimGeneratorUtilities
-//  // For the firesim utilities to use the same directory as the test suite
-//  override lazy val testDir = genDir
-//
-//  // From TestSuiteCommon
-//  val targetTuple = generatorArgs.tupleName
-//  val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}",
-//                           s"TARGET_CONFIG=${generatorArgs.targetConfigs}",
-//                           s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}")
-//
-//  it should "pass" in {
-//    assert(make("fsim-tracegen") == 0)
-//  }
-//}
-//
-//class FireSimLLCTraceGenTest extends FireSimTraceGenTest(
-//  "DDR3FRFCFSLLC4MB_FireSimTraceGenConfig", "BaseF1Config")
-//
-//class FireSimL2TraceGenTest extends FireSimTraceGenTest(
-//  "DDR3FRFCFS_FireSimTraceGenL2Config", "BaseF1Config")