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Removing redefinitions of HasHarnessSignalReferences and HasTestHarnessFunctions in TestHarness.scala.

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This commit is contained in:
James Dunn
2020-10-10 19:55:02 -07:00
parent 54acfe71fc
commit dca56cd858
4 changed files with 5 additions and 369 deletions
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15
fpga/src/main/scala/arty/TestHarness.scala
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@@ -6,22 +6,9 @@ import scala.collection.mutable.{ArrayBuffer}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.config.{Field, Parameters}
import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
import chipyard.{BuildTop, HasHarnessSignalReferences}
import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions}
import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
trait HasTestHarnessFunctions {
val lazySystem: LazyModule
val harnessFunctions = ArrayBuffer.empty[HasHarnessSignalReferences => Seq[Any]]
val portMap = scala.collection.mutable.Map[String, Seq[Data]]()
}
trait HasHarnessSignalReferences {
def harnessClock: Clock
def harnessReset: Reset
def dutReset: Reset
def success: Bool
}
class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences {
val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop")