Merge remote-tracking branch 'origin/main' into bump-verilator

.github/workflows/chipyard-full-flow.yml

@@ -107,6 +107,60 @@ jobs:
           source env.sh
           cd sims/verilator
           make verilog
+      - name: VLSI test
+        run: |
+          cd ${{ env.REMOTE_WORK_DIR }}
+          eval "$(conda shell.bash hook)"
+          source env.sh
+
+          cd vlsi
+
+          # NOTE: most conda installs are in separate conda envs because they mess up 
+          #   each other's versions (for no apparent reason) and we need the latest versions
+          conda config --add channels defaults
+          conda config --add channels litex-hub
+
+          # installs for example-sky130.yml
+          conda create -y --prefix ./.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9
+          git clone https://github.com/rahulk29/sram22_sky130_macros.git
+
+          # installs for example-openroad.yml
+          conda create -y --prefix ./.conda-yosys yosys=0.27_4_gb58664d44
+          conda create -y --prefix ./.conda-openroad openroad=2.0_7070_g0264023b6
+          conda create -y --prefix ./.conda-klayout klayout=0.28.5_98_g87e2def28
+          conda create -y --prefix ./.conda-signoff magic=8.3.376_0_g5e5879c netgen=1.5.250_0_g178b172
+
+          echo "# Tutorial configs" > tutorial.yml
+          echo "# pdk" > tutorial.yml
+          echo "technology.sky130.sky130A: $PWD/.conda-sky130/share/pdk/sky130A" >> tutorial.yml
+          echo "technology.sky130.sram22_sky130_macros: $PWD/sram22_sky130_macros" >> tutorial.yml
+          echo "" >> tutorial.yml
+          echo "# tools" >> tutorial.yml
+          echo "synthesis.yosys.yosys_bin: $PWD/.conda-yosys/bin/yosys" >> tutorial.yml
+          echo "par.openroad.openroad_bin: $PWD/.conda-openroad/bin/openroad" >> tutorial.yml
+          echo "par.openroad.klayout_bin: $PWD/.conda-klayout/bin/klayout" >> tutorial.yml
+          echo "drc.magic.magic_bin: $PWD/.conda-signoff/bin/magic" >> tutorial.yml
+          echo "lvs.netgen.netgen_bin: $PWD/.conda-signoff/bin/netgen" >> tutorial.yml
+          echo "" >> tutorial.yml
+          echo "# speed up tutorial runs & declutter log output" >> tutorial.yml
+          echo "par.openroad.timing_driven: false" >> tutorial.yml
+          echo "par.openroad.write_reports: false" >> tutorial.yml
+
+          conda config --remove channels litex-hub
+          conda config --remove channels defaults
+
+          export tutorial=sky130-openroad
+          export EXTRA_CONFS=tutorial.yml
+          export VLSI_TOP=RocketTile
+          make buildfile
+          make syn
+          # openroad freezes during some write commands after detailed route
+          # so need to stop the flow & run last step separately
+          make par HAMMER_EXTRA_ARGS="--stop_after_step extraction"
+          make redo-par HAMMER_EXTRA_ARGS="--start_before_step extraction"
+          make drc
+          make lvs
+
 
   cleanup:
     name: cleanup

README.md

@@ -84,6 +84,7 @@ These additional publications cover many of the internal components used in Chip
     * **FireMarshal**: N. Pemberton, et al., *ISPASS'21*. [PDF](https://ieeexplore.ieee.org/document/9408192).
 * **VLSI**
     * **Hammer**: E. Wang, et al., *ISQED'20*. [PDF](https://www.isqed.org/English/Archives/2020/Technical_Sessions/113.html).
+    * **Hammer**: H. Liew, et al., *DAC'22*. [PDF](https://dl.acm.org/doi/abs/10.1145/3489517.3530672).
 
 ## Acknowledgements
 

conda-reqs/chipyard.yaml

@@ -1,5 +1,6 @@
 channels:
     - ucb-bar
+    - litex-hub
     - conda-forge
     - nodefaults
 
@@ -46,7 +47,6 @@ dependencies:
     - doit>=0.34.0
     - gitpython
     - humanfriendly
-    - e2fsprogs
     - ctags
     - bison
     - flex
@@ -101,8 +101,9 @@ dependencies:
 
     # hammer packages
     - sty
+    - open_pdks.sky130a
     - pip:
-        - hammer-vlsi[asap7]==1.0.1
+        - hammer-vlsi[asap7]==1.0.5
 
     # doc requirements
     - sphinx

conda-reqs/esp-tools.yaml

@@ -1,5 +1,6 @@
 channels:
     - ucb-bar
+    - litex-hub
     - conda-forge
     - nodefaults
 

conda-reqs/riscv-tools.yaml

@@ -1,5 +1,6 @@
 channels:
     - ucb-bar
+    - litex-hub
     - conda-forge
     - nodefaults
 
@@ -14,4 +15,4 @@ dependencies:
     # https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications
     #   documentation on package_spec syntax for constraining versions
 
-    - riscv-tools=1.0.1 # from ucb-bar channel - https://github.com/ucb-bar/riscv-tools-feedstock
+    - riscv-tools=1.0.3 # from ucb-bar channel - https://github.com/ucb-bar/riscv-tools-feedstock

docs/VLSI/ASAP7-Tutorial.rst

@@ -126,9 +126,9 @@ To run DRC & LVS, and view the results in Calibre:
 .. code-block:: shell
 
     make drc CONFIG=TinyRocketConfig
-    ./build/drc-rundir/generated-scripts/view-drc
+    ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view-drc
     make lvs CONFIG=TinyRocketConfig
-    ./build/lvs-rundir/generated-scripts/view-lvs
+    ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view-lvs
 
 Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/asap7>`__.
 Furthermore, the dummy SRAMs that are provided in this tutorial and PDK do not have any geometry inside, so will certainly cause DRC errors.

docs/VLSI/Sky130-Commercial-Tutorial.rst

@@ -1,7 +1,7 @@
 .. _sky130-commercial-tutorial:
 
-Sky130 Tutorial
+Sky130 Commercial Tutorial
-===============
+==========================
 The ``vlsi`` folder of this repository contains an example Hammer flow with the TinyRocketConfig from Chipyard. This example tutorial uses the built-in Sky130 technology plugin and requires access to the included Cadence and Mentor tool plugin submodules. Cadence is necessary for synthesis & place-and-route, while Mentor is needed for DRC & LVS.
 
 Project Structure
@@ -47,7 +47,23 @@ Prerequisites
 
 * Python 3.9+
 * Genus, Innovus, Voltus, VCS, and Calibre licenses
-* Sky130 PDK, install using `these directions  <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
+* Sky130A PDK, install `using conda <https://anaconda.org/litex-hub/open_pdks.sky130a>`__ or `these directions  <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
+* `Sram22 Sky130 SRAM macros  <https://github.com/rahulk29/sram22_sky130_macros>`__ 
+
+  * These SRAM macros were generated using the `Sram22 SRAM generator  <https://github.com/rahulk29/sram22>`__ (still very heavily under development)
+
+Quick Prerequisite Setup
+^^^^^^^^^^^^^^^^^^^^^^^^
+As of recently, the Sky130A PDK may be installed via conda.
+The prerequisite setup for this tutorial may eventually be scripted, but for now the directions to set them up are below.
+
+.. code-block:: shell
+
+    # download all files for Sky130A PDK
+    conda create -c litex-hub --prefix ~/.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9
+    # clone the SRAM22 Sky130 SRAM macros
+    git clone https://github.com/rahulk29/sram22_sky130_macros ~/sram22_sky130_macros
+
 
 Initial Setup
 -------------
@@ -59,6 +75,38 @@ In the Chipyard root, ensure that you have the Chipyard conda environment activa
 
 to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
 
+Now navigate to the ``vlsi`` directory. The remainder of the tutorial will assume you are in this directory. 
+We will summarize a few files in this directory that will be important for the rest of the tutorial.
+
+.. code-block:: shell
+
+    cd ~chipyard/vlsi
+
+example-vlsi-sky130
+^^^^^^^^^^^^^^^^^^^
+This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow.
+
+
+example-sky130.yml
+^^^^^^^^^^^^^^^^^^
+This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
+
+Add the following YAML keys to the top of this file to specify the location of the Sky130A PDK and SRAM macros.
+
+.. code-block:: yaml
+
+    # all ~ should be replaced with absolute paths to these directories
+    # technology paths
+    technology.sky130.sky130A: ~/.conda-sky130/share/pdk/sky130A
+    technology.sky130.sram22_sky130_macros: ~/sram22_sky130_macros
+
+
+example-tools.yml
+^^^^^^^^^^^^^^^^^
+This contains the Hammer configuration for a commercial tool flow.
+It selects tools for synthesis (Cadence Genus), place and route (Cadence Innovus), DRC and LVS (Mentor Calibre).
+
+
 Building the Design
 --------------------
 To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build system to push the design and SRAM macros through the flow:
@@ -71,12 +119,21 @@ The command ``make buildfile`` generates a set of Make targets in ``build/hammer
 It needs to be re-run if environment variables are changed.
 It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment.
 
+The ``buildfile`` make target has dependencies on both (1) the Verilog that is elaborated from all Chisel sources
+and (2) the mapping of memory instances in the design to SRAM macros;
+all files related to these two steps reside in the ``generated-src/chipyard.TestHarness.TinyRocketConfig-ChipTop`` directory.
+Note that the files in ``generated-src`` vary for each tool/technology flow.
+This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows 
+(due to the ``ENABLE_YOSYS_FLOW`` flag present for the OpenROAD flow), so these flows should be run in separate
+chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly.
+
+
 For the purpose of brevity, in this tutorial we will set the Make variable ``tutorial=sky130-commercial``,
 which will cause additional variables to be set in ``tutorial.mk``, a few of which are summarized as follows:
 
 * ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime.
 * ``tech_name=sky130`` sets a few more necessary paths in the ``Makefile``, such as the appropriate Hammer plugin
-* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-tools.yml`` and ``example-sky130.yml``, which are described below
+* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-tools.yml`` and ``example-sky130.yml``, which are described above
 * ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml``
 * ``VLSI_OBJ_DIR=build-sky130-commercial`` gives the build directory a unique name to allow running multiple flows in the same repo. Note that for the rest of the tutorial we will still refer to this directory in file paths as ``build``, again for brevity.
 * ``VLSI_TOP`` is by default ``ChipTop``, which is the name of the top-level Verilog module generated in the Chipyard SoC configs. By instead setting ``VLSI_TOP=Rocket``, we can use the Rocket core as the top-level module for the VLSI flow, which consists only of a single RISC-V core (and no caches, peripherals, buses, etc). This is useful to run through this tutorial quickly, and does not rely on any SRAMs.
@@ -84,24 +141,6 @@ which will cause additional variables to be set in ``tutorial.mk``, a few of whi
 Running the VLSI Flow
 ---------------------
 
-example-vlsi-sky130
-^^^^^^^^^^^^^^^^^^^
-This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow.
-
-
-example-sky130.yml
-^^^^^^^^^^^^^^^^^^
-This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
-
-First, set ``technology.sky130.sky130A/sky130_nda/openram_lib`` to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the
-`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
-for details about the PDK setup.
-
-example-tools.yml
-^^^^^^^^^^^^^^^^^
-This contains the Hammer configuration for a commercial tool flow.
-It selects tools for synthesis (Cadence Genus), place and route (Cadence Innovus), DRC and LVS (Mentor Calibre).
-
 Synthesis
 ^^^^^^^^^
 .. code-block:: shell
@@ -160,3 +199,20 @@ Post-P&R power and rail (IR drop) analysis is supported with Voltus:
 If you append the ``BINARY`` variable to the command, it will use the activity file generated from a ``sim-<syn/par>-debug`` run and report dynamic power & IR drop from the toggles encoded in the waveform.
 
 To bypass gate-level simulation, you will need to run the power tool manually (see the generated commands in the generated ``hammer.d`` buildfile). Static and active (vectorless) power & IR drop will be reported.
+
+
+VLSI Flow Control
+^^^^^^^^^^^^^^^^^
+Firt, refer to the :ref:`VLSI/Hammer:VLSI Flow Control` documentation. The below examples use the ``redo-par`` Make target to re-run only place-and-route. ``redo-`` may be prepended to any of the VLSI flow actions to re-run only that action.
+
+.. code-block:: shell
+
+      # the following two statements are equivalent because the
+      #   extraction step immediately precedes the write_design step
+      make redo-par HAMMER_EXTRA_ARGS="--start_after_step extraction"
+      make redo-par HAMMER_EXTRA_ARGS="--start_before_step write_design"
+
+      # example of re-running only floorplanning to test out a new floorplan configuration
+      #   the "-p file.yml" causes file.yml to override any previous yaml/json configurations
+      make redo-par \
+        HAMMER_EXTRA_ARGS="--only_step floorplan_design -p example-designs/sky130-openroad.yml"

docs/VLSI/Sky130-OpenROAD-Tutorial.rst

@@ -20,7 +20,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
 
 * ``env.yml``
 
-  * A template file for tool environment configuration. Fill in the install and license server paths for your environment. For SLICE and BWRC affiliates, example environment configs are found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/env>`__.
+  * This file is not used in this tutorial, but is required for the commercial tool flow. A template file for tool environment configuration. Fill in the install and license server paths for your environment. For SLICE and BWRC affiliates, example environment configs are found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/env>`__.
 
 * ``example-vlsi-sky130``
 
@@ -28,7 +28,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
 
 * ``example-sky130.yml``, ``example-openroad.yml``, ``example-designs/sky130-openroad.yml``
 
-  * Hammer IR for this tutorial. For SLICE and BWRC affiliates, an example ASAP7 config is found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/pdks>`__.
+  * Hammer IR for this tutorial. For SLICE and BWRC affiliates, an example Sky130 config is found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/pdks>`__.
 
 * ``example-design.yml``, ``example-asap7.yml``, ``example-tech.yml``
 
@@ -48,12 +48,35 @@ Prerequisites
 * Python 3.9+
 * OpenROAD flow tools:
 
-  * Yosys (synthesis), install `from source <https://yosyshq.net/yosys/download.html>`__ or `using conda <https://anaconda.org/TimVideos/yosys>`__
+  * Yosys (synthesis), install `using conda <https://anaconda.org/litex-hub/yosys>`__ or `from source <https://yosyshq.net/yosys/download.html>`__
-  * OpenROAD (place-and-route), install `from source <https://openroad.readthedocs.io/en/latest/main/README.html#install-dependencies>`__
+  * OpenROAD (place-and-route), install `using conda <https://anaconda.org/litex-hub/openroad>`__ (note that GUI is disabled in conda package) or `from source <https://openroad.readthedocs.io/en/latest/main/README.html#install-dependencies>`__
-  * Magic (DRC), install `from source <http://www.opencircuitdesign.com/magic/install.html>`__
+  * KLayout (DEF to GDSII conversion), install `using conda <https://anaconda.org/litex-hub/klayout>`__ or `from source <https://www.klayout.de/build.html>`__
-  * NetGen (LVS), install `from source <http://www.opencircuitdesign.com/netgen/install.html>`__ or `using conda <https://anaconda.org/conda-forge/netgen>`__
+  * Magic (DRC), , install `using conda <https://anaconda.org/litex-hub/magic>`__ or `from source <http://www.opencircuitdesign.com/magic/install.html>`__
+  * NetGen (LVS), , install `using conda <https://anaconda.org/litex-hub/netgen>`__ or `from source <http://www.opencircuitdesign.com/netgen/install.html>`__
 
-* Sky130 PDK, install using `these directions  <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
+* Sky130A PDK, install `using conda <https://anaconda.org/litex-hub/open_pdks.sky130a>`__ or `these directions  <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
+* `Sram22 Sky130 SRAM macros  <https://github.com/rahulk29/sram22_sky130_macros>`__ 
+
+  * These SRAM macros were generated using the `Sram22 SRAM generator  <https://github.com/rahulk29/sram22>`__ (still very heavily under development)
+
+Quick Prerequisite Setup
+^^^^^^^^^^^^^^^^^^^^^^^^
+As of recently, most of the prerequisites of this tutorial may now be installed as conda packages.
+The prerequisite setup for this tutorial may eventually be scripted, but for now the directions to set them up are below.
+Note that we create a new conda environment for each tool because some of them have conflicting dependencies.
+
+.. code-block:: shell
+
+    # download all files for Sky130A PDK
+    conda create -c litex-hub --prefix ~/.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9
+    # clone the SRAM22 Sky130 SRAM macros
+    git clone https://github.com/rahulk29/sram22_sky130_macros ~/sram22_sky130_macros
+
+    # install all VLSI tools
+    conda create -c litex-hub --prefix ~/.conda-yosys yosys=0.27_4_gb58664d44
+    conda create -c litex-hub --prefix ~/.conda-openroad openroad=2.0_7070_g0264023b6
+    conda create -c litex-hub --prefix ~/.conda-klayout klayout=0.28.5_98_g87e2def28
+    conda create -c litex-hub --prefix ~/.conda-signoff magic=8.3.376_0_g5e5879c netgen=1.5.250_0_g178b172
 
 Initial Setup
 -------------
@@ -66,31 +89,13 @@ In the Chipyard root, ensure that you have the Chipyard conda environment activa
 to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule is cloned in the ``vlsi`` folder, 
 and for the commercial tool flow (set up by omitting the ``openroad`` argument), the tool plugin submodules are cloned into the ``vlsi`` folder.
 
-Building the Design
+Now navigate to the ``vlsi`` directory. The remainder of the tutorial will assume you are in this directory. 
---------------------
+We will summarize a few files in this directory that will be important for the rest of the tutorial.
-To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build system to push the design and SRAM macros through the flow:
 
 .. code-block:: shell
 
-    make buildfile tutorial=sky130-openroad
+    cd ~chipyard/vlsi
 
-The command ``make buildfile`` generates a set of Make targets in ``build/hammer.d``.
-It needs to be re-run if environment variables are changed.
-It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment.
-
-For the purpose of brevity, in this tutorial we will set the Make variable ``tutorial=sky130-openroad``,
-which will cause additional variables to be set in ``tutorial.mk``, a few of which are summarized as follows:
-
-* ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime.
-* ``tech_name=sky130`` sets a few more necessary paths in the ``Makefile``, such as the appropriate Hammer plugin
-* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-openroad.yml`` and ``example-sky130.yml``, which are described below
-* ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml``
-* ``VLSI_OBJ_DIR=build-sky130-openroad`` gives the build directory a unique name to allow running multiple flows in the same repo. Note that for the rest of the tutorial we will still refer to this directory in file paths as ``build``, again for brevity.
-* ``VLSI_TOP`` is by default ``ChipTop``, which is the name of the top-level Verilog module generated in the Chipyard SoC configs. By instead setting ``VLSI_TOP=Rocket``, we can use the Rocket core as the top-level module for the VLSI flow, which consists only of a single RISC-V core (and no caches, peripherals, buses, etc). This is useful to run through this tutorial quickly, and does not rely on any SRAMs.
-* ``ENABLE_CUSTOM_FIRRTL_PASS = 1`` is required for synthesis through Yosys. This reverts to the Scala FIRRTL Compiler so that unsupported multidimensional arrays are not generated in the Verilog.
-
-Running the VLSI Flow
----------------------
 
 example-vlsi-sky130
 ^^^^^^^^^^^^^^^^^^^
@@ -101,16 +106,70 @@ example-sky130.yml
 ^^^^^^^^^^^^^^^^^^
 This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
 
-First, set ``technology.sky130.<sky130A, openram_lib>`` to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the
+Add the following YAML keys to the top of this file to specify the location of the Sky130A PDK and SRAM macros.
-`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
-for details about the PDK setup.
 
+.. code-block:: yaml
+
+    # all ~ should be replaced with absolute paths to these directories
+    # technology paths
+    technology.sky130.sky130A: ~/.conda-sky130/share/pdk/sky130A
+    technology.sky130.sram22_sky130_macros: ~/sram22_sky130_macros
 
 example-openroad.yml
 ^^^^^^^^^^^^^^^^^^^^
 This contains the Hammer configuration for the OpenROAD tool flow.
 It selects tools for synthesis (Yosys), place and route (OpenROAD), DRC (Magic), and LVS (NetGen).
 
+Add the following YAML keys to the top of this file to specify the locations of the tool binaries.
+Note that this is not required if the tools are already on your PATH.
+
+.. code-block:: yaml
+
+    # all ~ should be replaced with absolute paths to these directories
+    # tool binary paths
+    synthesis.yosys.yosys_bin: ~/.conda-yosys/bin/yosys
+    par.openroad.openroad_bin: ~/.conda-openroad/bin/openroad
+    par.openroad.klayout_bin: ~/.conda-klayout/bin/klayout
+    drc.magic.magic_bin: ~/.conda-signoff/bin/magic
+    lvs.netgen.netgen_bin: ~/.conda-signoff/bin/netgen
+
+
+Building the Design
+--------------------
+
+To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build system to push the design and SRAM macros through the flow:
+
+.. code-block:: shell
+
+    make buildfile tutorial=sky130-openroad
+
+The command ``make buildfile`` generates a set of Make targets in ``build/hammer.d``.
+It needs to be re-run if environment variables are changed.
+It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment.
+
+The ``buildfile`` make target has dependencies on both (1) the Verilog that is elaborated from all Chisel sources
+and (2) the mapping of memory instances in the design to SRAM macros;
+all files related to these two steps reside in the ``generated-src/chipyard.TestHarness.TinyRocketConfig-ChipTop`` directory.
+Note that the files in ``generated-src`` vary for each tool/technology flow.
+This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows 
+(due to the ``ENABLE_YOSYS_FLOW`` flag, explained below), so these flows should be run in separate
+chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly.
+
+
+For the sake of brevity, in this tutorial we will set the Make variable ``tutorial=sky130-openroad``,
+which will cause additional variables to be set in ``tutorial.mk``, a few of which are summarized as follows:
+
+* ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime.
+* ``tech_name=sky130`` sets a few more necessary paths in the ``Makefile``, such as the appropriate Hammer plugin
+* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-openroad.yml`` and ``example-sky130.yml``, which are described above
+* ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml``
+* ``VLSI_OBJ_DIR=build-sky130-openroad`` gives the build directory a unique name to allow running multiple flows in the same repo. Note that for the rest of the tutorial we will still refer to this directory in file paths as ``build``, again for brevity.
+* ``VLSI_TOP`` is by default ``ChipTop``, which is the name of the top-level Verilog module generated in the Chipyard SoC configs. By instead setting ``VLSI_TOP=Rocket``, we can use the Rocket core as the top-level module for the VLSI flow, which consists only of a single RISC-V core (and no caches, peripherals, buses, etc). This is useful to run through this tutorial quickly, and does not rely on any SRAMs.
+* ``ENABLE_YOSYS_FLOW = 1`` is required for synthesis through Yosys. This reverts to the Scala FIRRTL Compiler so that unsupported multidimensional arrays are not generated in the Verilog.
+
+Running the VLSI Flow
+---------------------
+
 Synthesis
 ^^^^^^^^^
 
@@ -128,38 +187,79 @@ Place-and-Route
 
     make par tutorial=sky130-openroad
 
+Note that sometimes OpenROAD freezes on commands following the ``detailed_route`` step,
+so for now we recomment running place-and-route until the ``extraction`` step, 
+then re-starting the flow at this step. See the :ref:`VLSI/Sky130-OpenROAD-Tutorial:VLSI Flow Control` documentation
+below for how to break up the flow into these steps.
+
 After completion, the final database can be opened in an interactive OpenROAD session.
+Hammer generates a convenient script to launch these sessions
 
 .. code-block:: shell
 
-    cd ./build/par-rundir
+    cd ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir
     ./generated-scripts/open_chip
 
+Note that the conda OpenROAD package was compiled with the GUI disabled, so in order to view the layout,
+you will need to install OpenROAD from source.
 
 Below is the post-PnR layout for the TinyRocketConfig in Sky130 generated by OpenROAD.
 
 .. image:: ../_static/images/vlsi-openroad-par-tinyrocketconfig.png
 
-Intermediate databases are written in ``build/par-rundir`` between each step of the ``par`` action. These databases can be restored in an interactive OpenROAD session as desired for debugging purposes.
+Intermediate databases are written in ``build/par-rundir`` between each step of the ``par`` action,
+These databases can be restored using the same ``open_chip`` script for debugging purposes.
 
 .. code-block:: shell
 
-    openroad  # launch OpenROAD tool
+    cd build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir
-    openroad> read_db pre_global_route
+    ./generated_scripts/open_chip -h
+    "
+        Usage: ./generated-scripts/open_chip [-t] [openroad_db_name]
 
-.. Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files.
+        Options
+          openroad_db_name    : Name of database to load (default=latest)
+          -t, --timing        : Load timing info (default=disabled because of slow load time)
+          -h, --help          : Display this message
+    "
+    # load pre-global route database without timing information
+    ./generated_scripts/open_chip pre_global_route
+
+    # load post-clock tree database with timing inforamtion
+    ./generated_scripts/open_chip -t post_clock_tree
+
+Various reports, including timing reports, are found in ``build/par-rundir/reports``.
+
+See the `OpenROAD tool plugin <https://github.com/ucb-bar/hammer/blob/master/hammer/par/openroad>`__ for the full list of OpenROAD tool steps and their implementations.
 
 DRC & LVS
 ^^^^^^^^^
-To run DRC & LVS:
+
+As a note, this tutorial has been run extensively through commercial signoff tools,
+thus the open-source signoff flow is not stable or guaranteed to produce useful results.
+We welcome any contributions to improving both our `Magic tool plugin <https://github.com/ucb-bar/hammer/blob/master/hammer/drc/magic>`__
+and `Netgen tool plugin <https://github.com/ucb-bar/hammer/blob/master/hammer/lvs/netgen>`__.
+
+To run DRC & LVS in Magic & Netgen, respectively:
 
 .. code-block:: shell
 
     make drc tutorial=sky130-openroad
+    ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc
     make lvs tutorial=sky130-openroad
+    ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs
 
-Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the
+Note that in ``sky130-openroad.yml`` we have set the following YAML keys:
-`Sky130 Hammer plugin README  <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__.
+
+.. code-block:: yaml
+
+    drc.magic.generate_only: true
+    lvs.netgen.generate_only: true
+
+These keys cause the Hammer plugin to only generate all necessary scripts, without executing them with the respective tool.
+This is because Magic and Netgen, as of the writing of this tutorial, do not have a database format that may be loaded interactively,
+so to view the DRC/LVS results for debugging you must launch the tool interactively, then run DRC/LVS checks,
+which is done by the ``generated-scripts/view_[drc|lvs]`` scripts.
 
 
 VLSI Flow Control
@@ -168,15 +268,20 @@ Firt, refer to the :ref:`VLSI/Hammer:VLSI Flow Control` documentation. The below
 
 .. code-block:: shell
 
-      # the following two statements are equivalent because the
+      # the following two commands run the entire flow, using the pre_extraction
-      #   extraction step immediately precedes the write_design step
+      #   database to save and reload a checkpoint of the design
+      make par HAMMER_EXTRA_ARGS="--stop_after_step extraction"
+      make redo-par HAMMER_EXTRA_ARGS="--start_before_step extraction"
+
+      # the following two commands are equivalent because the extraction 
+      #   step immediately precedes the write_design step
       make redo-par HAMMER_EXTRA_ARGS="--start_after_step extraction"
       make redo-par HAMMER_EXTRA_ARGS="--start_before_step write_design"
 
       # example of re-running only floorplanning to test out a new floorplan configuration
-      make redo-par HAMMER_EXTRA_ARGS="--only_step floorplan_design -p example-sky130.yml"
+      #   the "-p file.yml" causes file.yml to override any previous yaml/json configurations
-
+      make redo-par \
-See the `OpenROAD tool plugin <https://github.com/ucb-bar/hammer/blob/master/hammer/par/openroad>`__ for the full list of OpenROAD tool steps and their implementations.
+        HAMMER_EXTRA_ARGS="--only_step floorplan_design -p example-designs/sky130-openroad.yml"
 
 Documentation
 -------------

generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala

@@ -21,6 +21,12 @@ class FPGemminiRocketConfig extends Config(
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
+class LeanGemminiRocketConfig extends Config(
+  new gemmini.LeanGemminiConfig ++                                 // use Lean Gemmini systolic array GEMM accelerator
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new chipyard.config.AbstractConfig)
+
 class HwachaRocketConfig extends Config(
   new chipyard.config.WithHwachaTest ++
   new hwacha.DefaultHwachaConfig ++                              // use Hwacha vector accelerator

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -288,3 +288,9 @@ class FireSimRocketMMIOOnlyConfig extends Config(
   new WithDefaultMemModel ++
   new WithFireSimConfigTweaks ++
   new chipyard.RocketConfig)
+
+class FireSimGemminiRocketMMIOOnlyConfig extends Config(
+  new WithDefaultMMIOOnlyFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.LeanGemminiRocketConfig)

vlsi/example-asap7.yml

@@ -37,54 +37,47 @@ vlsi.inputs.placement_constraints:
       right: 0
       top: 0
       bottom: 0
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
     type: hardmacro
     x: 550
     y: 25
     orientation: "r0"
     top_layer: "M4"
     master: "SRAM1RW4096x8"
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1"
     type: hardmacro
     x: 550
     y: 270
     orientation: "r0"
     top_layer: "M4"
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2"
     type: hardmacro
     x: 675
     y: 25
     orientation: "r0"
     top_layer: "M4"
     master: "SRAM1RW4096x8"
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3"
     type: hardmacro
     x: 675
     y: 270
     orientation: "r0"
     top_layer: "M4"
     master: "SRAM1RW4096x8"
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
     type: hardmacro
     x: 125
     y: 150
     orientation: "my"
     top_layer: "M4"
     master: "SRAM1RW64x21"
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
     type: hardmacro
     x: 0
     y: 25
     orientation: "my"
     top_layer: "M4"
     master: "SRAM1RW1024x32"
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
-    type: hardmacro
-    x: 0
-    y: 260
-    orientation: "my"
-    top_layer: "M4"
-    master: "SRAM1RW1024x37"
 
 # Pin placement constraints
 vlsi.inputs.pin_mode: generated

vlsi/example-designs/sky130-commercial.yml

@@ -2,149 +2,18 @@
 
 # Specify clock signals
 vlsi.inputs.clocks: [
-  {name: "clock_clock", period: "5ns", uncertainty: "1ns"}
+  {name: "clock_clock", period: "30ns", uncertainty: "2ns"}
 ]
 
-# Power Straps
-par.power_straps_mode: generate
-par.generate_power_straps_method: by_tracks
-par.blockage_spacing: 40.0
-par.blockage_spacing_top_layer: met4
-par.generate_power_straps_options:
-  by_tracks:
-    strap_layers:
-      - met4
-      - met5
-    pin_layers:
-      - met5
-    blockage_spacing_met2: 4.0
-    blockage_spacing_met4: 2.0
-    track_width: 3
-    track_width_met5: 1
-    track_spacing: 5
-    track_start: 10
-    track_start_met5: 1
-    power_utilization: 0.1
-    power_utilization_met4: 0.1
-    power_utilization_met5: 0.1
-
 # Placement Constraints
-vlsi.inputs.placement_constraints:
+# If overriding the placement constraints in example-sky130.yml,
-  - path: "ChipTop"
+# ensure one of the toplevel margin sides corresponding with the power pin metal layers
-    type: toplevel
+# is set to 0 so that Innovus actually creates those pins (otherwise LVS will fail).
-    x: 0
+# For example, in example-sky130.yml we set 
-    y: 0
+#   par.generate_power_straps_options.by_tracks.pin_layers: 'met5'  # horizontal layer
-    width: 4000
+# therefore we must also set:
-    height: 2500
+#   vlsi.inputs.placement_constraints:
-    margins:
+#     - path: "ChipTop"
-      left: 0
+#       ...
-      right: 0
+#       margins:
-      top: 0
+#         right: 0  # or left: 0
-      bottom: 0
-
-  # Place data cache SRAM instances
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
-    type: hardmacro
-    x: 50
-    y: 100
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
-    type: hardmacro
-    x: 50
-    y: 700
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0"
-    type: hardmacro
-    x: 50
-    y: 1300
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0"
-    type: hardmacro
-    x: 50
-    y: 1900
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0"
-    type: hardmacro
-    x: 1000
-    y: 1900
-    orientation: r0
-
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0"
-    type: hardmacro
-    x: 1000
-    y: 1300
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0"
-    type: hardmacro
-    x: 1000
-    y: 700
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0"
-    type: hardmacro
-    x: 1000
-    y: 100
-    orientation: r0
-
-  # Place instruction cache SRAM instances
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
-    type: hardmacro
-    x: 3250
-    y: 100
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0"
-    type: hardmacro
-    x: 3250
-    y: 700
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
-    type: hardmacro
-    x: 3450
-    y: 1300
-    orientation: r0
-
-  # Place L2 TLB SRAM instances
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
-    type: hardmacro
-    x: 2000
-    y: 1300
-    orientation: "r0"
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1"
-    type: hardmacro
-    x: 2000
-    y: 1900
-    orientation: "r0"
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2"
-    type: hardmacro
-    x: 2750
-    y: 1300
-    orientation: "r0"
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3"
-    type: hardmacro
-    x: 2750
-    y: 1900
-    orientation: "r0"
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4"
-    type: hardmacro
-    x: 3460
-    y: 1900
-    orientation: "r0"
-
-# Pin placement constraints
-vlsi.inputs.pin_mode: generated
-vlsi.inputs.pin.generate_mode: semi_auto
-vlsi.inputs.pin.assignments: [
-  {pins: "*", layers: ["met2", "met4"], side: "bottom"}
-]

vlsi/example-designs/sky130-openroad-rockettile.yml

@@ -0,0 +1,60 @@
+# Override configurations in ../example-sky130.yml and example-designs
+
+# Specify clock signals
+# Rocket/RocketTile names clock signal "clock" instead of "clock_clock"
+vlsi.inputs.clocks: [
+  {name: "clock", period: "30ns", uncertainty: "3ns"}
+]
+
+# Placement Constraints
+# Placement Constraints
+vlsi.inputs.placement_constraints:
+  - path: "RocketTile"
+    type: toplevel
+    x: 0
+    y: 0
+    width: 4000
+    height: 3000
+    margins:
+      left: 10
+      right: 0
+      top: 10
+      bottom: 10
+
+  # Place SRAM memory instances
+  # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
+  # data cache
+  - path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 50
+    orientation: r90
+  - path: "RocketTile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 450
+    orientation: r90
+  - path: "RocketTile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 850
+    orientation: r90
+  - path: "RocketTile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 1250
+    orientation: r90
+ 
+  # tag array
+  - path: "RocketTile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 1600
+    orientation: r90
+
+  # instruction cache
+  - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 2100
+    orientation: r90

vlsi/example-designs/sky130-openroad.yml

@@ -3,9 +3,42 @@
 # Specify clock signals
 # Relax the clock period for OpenROAD to meet timing
 vlsi.inputs.clocks: [
-  {name: "clock_clock", period: "30ns", uncertainty: "1ns"}
+  {name: "clock_clock", period: "50ns", uncertainty: "2ns"}
 ]
 
+# Flow parameters that yield a routable design with reasonable timing
+par.openroad:
+  timing_driven: true  # set to false to drastically speed up runs
+  create_archive_mode: none
+
+  write_reports: true  # set to false to slightly speed up runs
+
+  floorplan_mode: generate
+
+  macro_placement.halo: [50, 50]
+
+  global_placement.timing_driven: true
+  global_placement.routability_driven: true
+
+  global_placement.placement_padding: 6
+  detailed_placement.placement_padding: 4
+  clock_tree.placement_padding: 2
+  clock_tree_resize.placement_padding: 0
+
+  clock_tree_resize.setup_margin: 0.0
+  clock_tree_resize.hold_margin: 0.20
+  global_route_resize.hold_margin: 0.60
+  clock_tree_resize.hold_max_buffer_percent: 80  
+
+  global_placement.routing_adjustment: 0.5
+  global_route.routing_adjustment: 0.3
+  global_route_resize.routing_adjustment: 0.2
+
+# DRC/LVS configuration
+drc.magic.generate_only: true
+lvs.netgen.generate_only: true
+
+
 # Placement Constraints
 vlsi.inputs.placement_constraints:
   - path: "ChipTop"
@@ -13,78 +46,47 @@ vlsi.inputs.placement_constraints:
     x: 0
     y: 0
     width: 4000
-    height: 2500
+    height: 3000
     margins:
       left: 10
-      right: 10
+      right: 0
       top: 10
       bottom: 10
 
- # Place data cache SRAM instances
+  # Place SRAM memory instances
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_0"
+  # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
+  # data cache
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
     type: hardmacro
     x: 50
-    y: 100
+    y: 50
-    orientation: r0
+    orientation: r90
-
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_0"
     type: hardmacro
     x: 50
-    y: 700
+    y: 450
-    orientation: r0
+    orientation: r90
-
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_0"
     type: hardmacro
     x: 50
-    y: 1300
+    y: 850
-    orientation: r0
+    orientation: r90
-
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_0"
     type: hardmacro
     x: 50
-    y: 1900
+    y: 1250
-    orientation: r0
+    orientation: r90
  
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_4_0"
+  # tag array
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
     type: hardmacro
-    x: 1000
+    x: 50
-    y: 1900
+    y: 1600
-    orientation: r0
+    orientation: r90
 
-
+  # instruction cache
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_5_0"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
     type: hardmacro
-    x: 1000
+    x: 50
-    y: 1300
+    y: 2100
-    orientation: r0
+    orientation: r90
-
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_6_0"
-    type: hardmacro
-    x: 1000
-    y: 700
-    orientation: r0
-
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_7_0"
-    type: hardmacro
-    x: 1000
-    y: 100
-    orientation: r0
-
-  # Place instruction cache SRAM instances
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_0_0"
-    type: hardmacro
-    x: 3250
-    y: 100
-    orientation: r0
-
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_1_0"
-    type: hardmacro
-    x: 3250
-    y: 700
-    orientation: r0
-
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.tag_array.tag_array_ext.mem_0_0"
-    type: hardmacro
-    x: 3450
-    y: 1300
-    orientation: r0

vlsi/example-sky130.yml

@@ -7,7 +7,7 @@ vlsi.core.max_threads: 12
 # Technology paths
 technology.sky130:
   sky130A: "/path/to/sky130A"
-  openram_lib: "/path/to/sky130_sram_macros"
+  sram22_sky130_macros: "/path/to/sram22_sky130_macros"
 
   # this key is OPTIONAL, no NDA files will be used if it does not point to a valid path
   sky130_nda: "/path/to/skywater-src-nda"
@@ -20,31 +20,55 @@ vlsi.inputs.power_spec_type: "cpf"
 
 # Specify clock signals
 vlsi.inputs.clocks: [
-  {name: "clock_clock", period: "10ns", uncertainty: "1ns"}
+  {name: "clock_clock", period: "20ns", uncertainty: "1ns"}
 ]
 
 # Generate Make include to aid in flow
 vlsi.core.build_system: make
 
+
 # Placement Constraints
 vlsi.inputs.placement_constraints:
   - path: "ChipTop"
     type: toplevel
     x: 0
     y: 0
-    width: 3500
+    width: 4000
-    height: 2500
+    height: 3000
     margins:
       left: 10
-      right: 10
+      right: 0
       top: 10
       bottom: 10
 
+  # Place SRAM memory instances
+    # data cache
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 50
+    orientation: r90
+
+  # tag array
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 1600
+    orientation: r90
+
+  # instruction cache
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 2100
+    orientation: r90
+
+
 # Power Straps
 par.power_straps_mode: generate
 par.generate_power_straps_method: by_tracks
-par.blockage_spacing: 40.0
+par.blockage_spacing: 2.0
-par.blockage_spacing_top_layer: met4
+par.blockage_spacing_top_layer: met3
 par.generate_power_straps_options:
   by_tracks:
     strap_layers:
@@ -63,6 +87,7 @@ par.generate_power_straps_options:
     power_utilization_met4: 0.1
     power_utilization_met5: 0.1
 
+
 # Pin placement constraints
 vlsi.inputs.pin_mode: generated
 vlsi.inputs.pin.generate_mode: semi_auto
@@ -70,5 +95,6 @@ vlsi.inputs.pin.assignments: [
   {pins: "*", layers: ["met2", "met4"], side: "bottom"}
 ]
 
+
 # SRAM Compiler compiler options
 vlsi.core.sram_generator_tool: "hammer.technology.sky130.sram_compiler"

vlsi/tutorial.mk

@@ -1,10 +1,8 @@
 #########################################################################################
 # makefile variables for Hammer tutorials
 #########################################################################################
-# tutorial ?= none
+tutorial ?= none
-tutorial ?= sky130-openroad
+EXTRA_CONFS ?=
-
-extra ?=
 
 # TODO: eventually have asap7 commercial/openroad tutorial flavors
 ifeq ($(tutorial),asap7)
@@ -12,7 +10,7 @@ ifeq ($(tutorial),asap7)
     CONFIG            ?= TinyRocketConfig
     TOOLS_CONF        ?= example-tools.yml
     TECH_CONF         ?= example-asap7.yml
-    INPUT_CONFS       ?= $(EXTRA_CONFS) $(TOOLS_CONF) $(TECH_CONF)
+    DESIGN_CONFS      ?=
     VLSI_OBJ_DIR      ?= build-asap7-commercial
 endif
 
@@ -21,9 +19,9 @@ ifeq ($(tutorial),sky130-commercial)
     CONFIG            ?= TinyRocketConfig
     TOOLS_CONF        ?= example-tools.yml
     TECH_CONF         ?= example-sky130.yml
-    DESIGN_CONF       ?= example-designs/sky130-commercial.yml
+    DESIGN_CONFS      ?= example-designs/sky130-commercial.yml \
-    EXTRA_CONFS       ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, )
+                        $(if $(filter $(VLSI_TOP),Rocket), \
-    INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
+                            example-designs/sky130-rocket.yml, )
     VLSI_OBJ_DIR      ?= build-sky130-commercial
 endif
 
@@ -32,12 +30,14 @@ ifeq ($(tutorial),sky130-openroad)
     CONFIG            ?= TinyRocketConfig
     TOOLS_CONF        ?= example-openroad.yml
     TECH_CONF         ?= example-sky130.yml
-    DESIGN_CONF       ?= example-designs/sky130-openroad.yml
+    DESIGN_CONFS      ?= example-designs/sky130-openroad.yml \
-    EXTRA_CONFS       ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, )
+                        $(if $(filter $(VLSI_TOP),Rocket), \
-    INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
+                            example-designs/sky130-rocket.yml) \
+                        $(if $(filter $(VLSI_TOP),RocketTile), \
+                            example-designs/sky130-openroad-rockettile.yml, )
     VLSI_OBJ_DIR      ?= build-sky130-openroad
     # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.
     ENABLE_YOSYS_FLOW  = 1
 endif
 
-HAMMER_EXTRA_ARGS      ?= -p $(TOOLS_CONF) -p $(TECH_CONF) -p $(DESIGN_CONF) $(extra)
+INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)