Merge remote-tracking branch 'origin/main' into bump-verilator

2023-03-14 14:20:10 -07:00
parent 95349755b5 6149edb101
commit dc0c6e62f1
23 changed files with 1044 additions and 1606 deletions
--- a/vlsi/example-asap7.yml
+++ b/vlsi/example-asap7.yml
@@ -37,54 +37,47 @@ vlsi.inputs.placement_constraints:
      right: 0
      top: 0
      bottom: 0
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
    type: hardmacro
    x: 550
    y: 25
    orientation: "r0"
    top_layer: "M4"
    master: "SRAM1RW4096x8"
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1"
    type: hardmacro
    x: 550
    y: 270
    orientation: "r0"
    top_layer: "M4"
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2"
    type: hardmacro
    x: 675
    y: 25
    orientation: "r0"
    top_layer: "M4"
    master: "SRAM1RW4096x8"
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3"
    type: hardmacro
    x: 675
    y: 270
    orientation: "r0"
    top_layer: "M4"
    master: "SRAM1RW4096x8"
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
    type: hardmacro
    x: 125
    y: 150
    orientation: "my"
    top_layer: "M4"
    master: "SRAM1RW64x21"
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
    type: hardmacro
    x: 0
    y: 25
    orientation: "my"
    top_layer: "M4"
    master: "SRAM1RW1024x32"
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
-    type: hardmacro
-    x: 0
-    y: 260
-    orientation: "my"
-    top_layer: "M4"
-    master: "SRAM1RW1024x37"

 # Pin placement constraints
 vlsi.inputs.pin_mode: generated
--- a/vlsi/example-designs/sky130-commercial.yml
+++ b/vlsi/example-designs/sky130-commercial.yml
@@ -2,149 +2,18 @@

 # Specify clock signals
 vlsi.inputs.clocks: [
-  {name: "clock_clock", period: "5ns", uncertainty: "1ns"}
+  {name: "clock_clock", period: "30ns", uncertainty: "2ns"}
 ]

-# Power Straps
-par.power_straps_mode: generate
-par.generate_power_straps_method: by_tracks
-par.blockage_spacing: 40.0
-par.blockage_spacing_top_layer: met4
-par.generate_power_straps_options:
-  by_tracks:
-    strap_layers:
-      - met4
-      - met5
-    pin_layers:
-      - met5
-    blockage_spacing_met2: 4.0
-    blockage_spacing_met4: 2.0
-    track_width: 3
-    track_width_met5: 1
-    track_spacing: 5
-    track_start: 10
-    track_start_met5: 1
-    power_utilization: 0.1
-    power_utilization_met4: 0.1
-    power_utilization_met5: 0.1
-
 # Placement Constraints
-vlsi.inputs.placement_constraints:
-  - path: "ChipTop"
-    type: toplevel
-    x: 0
-    y: 0
-    width: 4000
-    height: 2500
-    margins:
-      left: 0
-      right: 0
-      top: 0
-      bottom: 0
-
-  # Place data cache SRAM instances
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
-    type: hardmacro
-    x: 50
-    y: 100
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
-    type: hardmacro
-    x: 50
-    y: 700
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0"
-    type: hardmacro
-    x: 50
-    y: 1300
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0"
-    type: hardmacro
-    x: 50
-    y: 1900
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0"
-    type: hardmacro
-    x: 1000
-    y: 1900
-    orientation: r0
-
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0"
-    type: hardmacro
-    x: 1000
-    y: 1300
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0"
-    type: hardmacro
-    x: 1000
-    y: 700
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0"
-    type: hardmacro
-    x: 1000
-    y: 100
-    orientation: r0
-
-  # Place instruction cache SRAM instances
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
-    type: hardmacro
-    x: 3250
-    y: 100
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0"
-    type: hardmacro
-    x: 3250
-    y: 700
-    orientation: r0
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
-    type: hardmacro
-    x: 3450
-    y: 1300
-    orientation: r0
-
-  # Place L2 TLB SRAM instances
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
-    type: hardmacro
-    x: 2000
-    y: 1300
-    orientation: "r0"
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1"
-    type: hardmacro
-    x: 2000
-    y: 1900
-    orientation: "r0"
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2"
-    type: hardmacro
-    x: 2750
-    y: 1300
-    orientation: "r0"
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3"
-    type: hardmacro
-    x: 2750
-    y: 1900
-    orientation: "r0"
-
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4"
-    type: hardmacro
-    x: 3460
-    y: 1900
-    orientation: "r0"
-
-# Pin placement constraints
-vlsi.inputs.pin_mode: generated
-vlsi.inputs.pin.generate_mode: semi_auto
-vlsi.inputs.pin.assignments: [
-  {pins: "*", layers: ["met2", "met4"], side: "bottom"}
-]
+# If overriding the placement constraints in example-sky130.yml,
+# ensure one of the toplevel margin sides corresponding with the power pin metal layers
+# is set to 0 so that Innovus actually creates those pins (otherwise LVS will fail).
+# For example, in example-sky130.yml we set 
+#   par.generate_power_straps_options.by_tracks.pin_layers: 'met5'  # horizontal layer
+# therefore we must also set:
+#   vlsi.inputs.placement_constraints:
+#     - path: "ChipTop"
+#       ...
+#       margins:
+#         right: 0  # or left: 0
--- a/vlsi/example-designs/sky130-openroad-rockettile.yml
+++ b/vlsi/example-designs/sky130-openroad-rockettile.yml
@@ -0,0 +1,60 @@
+# Override configurations in ../example-sky130.yml and example-designs
+
+# Specify clock signals
+# Rocket/RocketTile names clock signal "clock" instead of "clock_clock"
+vlsi.inputs.clocks: [
+  {name: "clock", period: "30ns", uncertainty: "3ns"}
+]
+
+# Placement Constraints
+# Placement Constraints
+vlsi.inputs.placement_constraints:
+  - path: "RocketTile"
+    type: toplevel
+    x: 0
+    y: 0
+    width: 4000
+    height: 3000
+    margins:
+      left: 10
+      right: 0
+      top: 10
+      bottom: 10
+
+  # Place SRAM memory instances
+  # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
+  # data cache
+  - path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 50
+    orientation: r90
+  - path: "RocketTile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 450
+    orientation: r90
+  - path: "RocketTile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 850
+    orientation: r90
+  - path: "RocketTile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 1250
+    orientation: r90
+ 
+  # tag array
+  - path: "RocketTile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 1600
+    orientation: r90
+
+  # instruction cache
+  - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 2100
+    orientation: r90
--- a/vlsi/example-designs/sky130-openroad.yml
+++ b/vlsi/example-designs/sky130-openroad.yml
@@ -3,9 +3,42 @@
 # Specify clock signals
 # Relax the clock period for OpenROAD to meet timing
 vlsi.inputs.clocks: [
-  {name: "clock_clock", period: "30ns", uncertainty: "1ns"}
+  {name: "clock_clock", period: "50ns", uncertainty: "2ns"}
 ]

+# Flow parameters that yield a routable design with reasonable timing
+par.openroad:
+  timing_driven: true  # set to false to drastically speed up runs
+  create_archive_mode: none
+
+  write_reports: true  # set to false to slightly speed up runs
+
+  floorplan_mode: generate
+
+  macro_placement.halo: [50, 50]
+
+  global_placement.timing_driven: true
+  global_placement.routability_driven: true
+
+  global_placement.placement_padding: 6
+  detailed_placement.placement_padding: 4
+  clock_tree.placement_padding: 2
+  clock_tree_resize.placement_padding: 0
+
+  clock_tree_resize.setup_margin: 0.0
+  clock_tree_resize.hold_margin: 0.20
+  global_route_resize.hold_margin: 0.60
+  clock_tree_resize.hold_max_buffer_percent: 80  
+
+  global_placement.routing_adjustment: 0.5
+  global_route.routing_adjustment: 0.3
+  global_route_resize.routing_adjustment: 0.2
+
+# DRC/LVS configuration
+drc.magic.generate_only: true
+lvs.netgen.generate_only: true
+
+
 # Placement Constraints
 vlsi.inputs.placement_constraints:
  - path: "ChipTop"
@@ -13,78 +46,47 @@ vlsi.inputs.placement_constraints:
    x: 0
    y: 0
    width: 4000
-    height: 2500
+    height: 3000
    margins:
      left: 10
-      right: 10
+      right: 0
      top: 10
      bottom: 10

- # Place data cache SRAM instances
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_0"
+  # Place SRAM memory instances
+  # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
+  # data cache
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
    type: hardmacro
    x: 50
-    y: 100
-    orientation: r0
-
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_0"
+    y: 50
+    orientation: r90
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
    type: hardmacro
    x: 50
-    y: 700
-    orientation: r0
-
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_0"
+    y: 450
+    orientation: r90
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
    type: hardmacro
    x: 50
-    y: 1300
-    orientation: r0
-
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_0"
+    y: 850
+    orientation: r90
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
    type: hardmacro
    x: 50
-    y: 1900
-    orientation: r0
-
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_4_0"
+    y: 1250
+    orientation: r90
+ 
+  # tag array
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
    type: hardmacro
-    x: 1000
-    y: 1900
-    orientation: r0
+    x: 50
+    y: 1600
+    orientation: r90

-
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_5_0"
+  # instruction cache
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
    type: hardmacro
-    x: 1000
-    y: 1300
-    orientation: r0
-
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_6_0"
-    type: hardmacro
-    x: 1000
-    y: 700
-    orientation: r0
-
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_7_0"
-    type: hardmacro
-    x: 1000
-    y: 100
-    orientation: r0
-
-  # Place instruction cache SRAM instances
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_0_0"
-    type: hardmacro
-    x: 3250
-    y: 100
-    orientation: r0
-
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_1_0"
-    type: hardmacro
-    x: 3250
-    y: 700
-    orientation: r0
-
-  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.tag_array.tag_array_ext.mem_0_0"
-    type: hardmacro
-    x: 3450
-    y: 1300
-    orientation: r0
+    x: 50
+    y: 2100
+    orientation: r90
--- a/vlsi/example-sky130.yml
+++ b/vlsi/example-sky130.yml
@@ -7,7 +7,7 @@ vlsi.core.max_threads: 12
 # Technology paths
 technology.sky130:
  sky130A: "/path/to/sky130A"
-  openram_lib: "/path/to/sky130_sram_macros"
+  sram22_sky130_macros: "/path/to/sram22_sky130_macros"

  # this key is OPTIONAL, no NDA files will be used if it does not point to a valid path
  sky130_nda: "/path/to/skywater-src-nda"
@@ -20,31 +20,55 @@ vlsi.inputs.power_spec_type: "cpf"

 # Specify clock signals
 vlsi.inputs.clocks: [
-  {name: "clock_clock", period: "10ns", uncertainty: "1ns"}
+  {name: "clock_clock", period: "20ns", uncertainty: "1ns"}
 ]

 # Generate Make include to aid in flow
 vlsi.core.build_system: make

+
 # Placement Constraints
 vlsi.inputs.placement_constraints:
  - path: "ChipTop"
    type: toplevel
    x: 0
    y: 0
-    width: 3500
-    height: 2500
+    width: 4000
+    height: 3000
    margins:
      left: 10
-      right: 10
+      right: 0
      top: 10
      bottom: 10

+  # Place SRAM memory instances
+    # data cache
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 50
+    orientation: r90
+
+  # tag array
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 1600
+    orientation: r90
+
+  # instruction cache
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 2100
+    orientation: r90
+
+
 # Power Straps
 par.power_straps_mode: generate
 par.generate_power_straps_method: by_tracks
-par.blockage_spacing: 40.0
-par.blockage_spacing_top_layer: met4
+par.blockage_spacing: 2.0
+par.blockage_spacing_top_layer: met3
 par.generate_power_straps_options:
  by_tracks:
    strap_layers:
@@ -63,6 +87,7 @@ par.generate_power_straps_options:
    power_utilization_met4: 0.1
    power_utilization_met5: 0.1

+
 # Pin placement constraints
 vlsi.inputs.pin_mode: generated
 vlsi.inputs.pin.generate_mode: semi_auto
@@ -70,5 +95,6 @@ vlsi.inputs.pin.assignments: [
  {pins: "*", layers: ["met2", "met4"], side: "bottom"}
 ]

+
 # SRAM Compiler compiler options
 vlsi.core.sram_generator_tool: "hammer.technology.sky130.sram_compiler"
--- a/vlsi/hammer-cadence-plugins
+++ b/vlsi/hammer-cadence-plugins
--- a/vlsi/tutorial.mk
+++ b/vlsi/tutorial.mk
@@ -1,10 +1,8 @@
 #########################################################################################
 # makefile variables for Hammer tutorials
 #########################################################################################
-# tutorial ?= none
-tutorial ?= sky130-openroad
-
-extra ?=
+tutorial ?= none
+EXTRA_CONFS ?=

 # TODO: eventually have asap7 commercial/openroad tutorial flavors
 ifeq ($(tutorial),asap7)
@@ -12,7 +10,7 @@ ifeq ($(tutorial),asap7)
    CONFIG            ?= TinyRocketConfig
    TOOLS_CONF        ?= example-tools.yml
    TECH_CONF         ?= example-asap7.yml
-    INPUT_CONFS       ?= $(EXTRA_CONFS) $(TOOLS_CONF) $(TECH_CONF)
+    DESIGN_CONFS      ?=
    VLSI_OBJ_DIR      ?= build-asap7-commercial
 endif

@@ -21,9 +19,9 @@ ifeq ($(tutorial),sky130-commercial)
    CONFIG            ?= TinyRocketConfig
    TOOLS_CONF        ?= example-tools.yml
    TECH_CONF         ?= example-sky130.yml
-    DESIGN_CONF       ?= example-designs/sky130-commercial.yml
-    EXTRA_CONFS       ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, )
-    INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
+    DESIGN_CONFS      ?= example-designs/sky130-commercial.yml \
+                        $(if $(filter $(VLSI_TOP),Rocket), \
+                            example-designs/sky130-rocket.yml, )
    VLSI_OBJ_DIR      ?= build-sky130-commercial
 endif

@@ -32,12 +30,14 @@ ifeq ($(tutorial),sky130-openroad)
    CONFIG            ?= TinyRocketConfig
    TOOLS_CONF        ?= example-openroad.yml
    TECH_CONF         ?= example-sky130.yml
-    DESIGN_CONF       ?= example-designs/sky130-openroad.yml
-    EXTRA_CONFS       ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, )
-    INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
+    DESIGN_CONFS      ?= example-designs/sky130-openroad.yml \
+                        $(if $(filter $(VLSI_TOP),Rocket), \
+                            example-designs/sky130-rocket.yml) \
+                        $(if $(filter $(VLSI_TOP),RocketTile), \
+                            example-designs/sky130-openroad-rockettile.yml, )
    VLSI_OBJ_DIR      ?= build-sky130-openroad
    # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.
    ENABLE_YOSYS_FLOW  = 1
 endif

-HAMMER_EXTRA_ARGS      ?= -p $(TOOLS_CONF) -p $(TECH_CONF) -p $(DESIGN_CONF) $(extra)
+INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)