From dc04c0cc8c0e446a283c8e5328d0ae3a56c11223 Mon Sep 17 00:00:00 2001
From: Harrison Liew <harrisonliew@gmail.com>
Date: Mon, 2 Sep 2019 23:27:48 -0700
Subject: [PATCH] margins for M2 DRCs

---
 vlsi/example.yml | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/vlsi/example.yml b/vlsi/example.yml
index 1c92731e..7e434cb6 100644
--- a/vlsi/example.yml
+++ b/vlsi/example.yml
@@ -22,8 +22,9 @@ vlsi.inputs.mmmc_corners: [
 ]
 
 # Specify clock signals
+# ASAP7 bug: period value should actually be in ps
 vlsi.inputs.clocks: [
-  {name: "clock", period: "20ns", uncertainty: "0.1ns"}
+  {name: "clock", period: "1000ns", uncertainty: "0.1ns"}
 ]
 
 # Generate Make include to aid in flow 
@@ -59,17 +60,17 @@ vlsi.inputs.placement_constraints:
     type: "toplevel"
     x: 0
     y: 0
-    width: 500
-    height: 500
+    width: 300
+    height: 300
     margins:
-      left: 0
-      right: 0
-      top: 0
-      bottom: 0
+      left: 10
+      right: 10
+      top: 10
+      bottom: 10
   - path: "Sha3AccelwBB/dco"
     type: "hardmacro"
-    x: 400
-    y: 400
+    x: 100
+    y: 100
     width: 32
     height: 32
     orientation: "r0"