diff --git a/.github/actions/cleanup-conda/action.yml b/.github/actions/cleanup-conda/action.yml index 3b0fdf88..7958b0a4 100644 --- a/.github/actions/cleanup-conda/action.yml +++ b/.github/actions/cleanup-conda/action.yml @@ -15,7 +15,7 @@ runs: conda env remove -n $env done fi - IS_NUMBER_REGEX='[0-9]+$' + IS_NUMBER_REGEX='^[0-9]+$' conda env list | awk '{print $1}' | tail -n +4 | while read envname; do ENV_DATE=$(echo $envname | sed "s/cy-[[:digit:]]\+-\(.*\)-\(riscv\|esp\)-tools/\1/") if ! [[ $ENV_DATE =~ $IS_NUMBER_REGEX ]]; then diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index b0f16636..fe1de2bf 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -45,7 +45,7 @@ search () { done } -submodules=("cva6" "boom" "ibex" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress") +submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress") dir="generators" branches=("master" "main" "dev") search diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 0b5502e6..a0a59052 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -33,7 +33,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache # key value store to get the build groups declare -A grouping grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone" -grouping["group-peripherals"]="chipyard-dmirocket chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals" +grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike" grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels" grouping["group-constellation"]="chipyard-constellation" grouping["group-tracegen"]="tracegen tracegen-boom" @@ -50,13 +50,15 @@ mapping["chipyard-digitaltop"]=" TOP=DigitalTop" mapping["chipyard-manymmioaccels"]=" CONFIG=ManyMMIOAcceleratorRocketConfig" mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig" mapping["chipyard-boom"]=" CONFIG=MediumBoomCosimConfig" -mapping["chipyard-spike"]=" CONFIG=SpikeFastUARTConfig EXTRA_SIM_FLAGS='+spike-ipc=10'" +mapping["chipyard-dmiboom"]=" CONFIG=dmiMediumBoomCosimConfig" +mapping["chipyard-spike"]=" CONFIG=SpikeConfig EXTRA_SIM_FLAGS='+spike-ipc=10'" mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig" mapping["chipyard-cva6"]=" CONFIG=CVA6Config" mapping["chipyard-ibex"]=" CONFIG=IbexConfig" mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'" mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'" +mapping["chipyard-chiplike"]=" CONFIG=ChipLikeQuadRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog" mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog" mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog" mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config" diff --git a/.github/scripts/remote-do-rtl-build.sh b/.github/scripts/remote-do-rtl-build.sh index 445c1c31..06b47ba2 100755 --- a/.github/scripts/remote-do-rtl-build.sh +++ b/.github/scripts/remote-do-rtl-build.sh @@ -16,8 +16,6 @@ source $SCRIPT_DIR/defaults.sh cd $REMOTE_CHIPYARD_DIR ./scripts/init-submodules-no-riscv-tools.sh --force -./scripts/init-fpga.sh - # Constellation can run without espresso, but this improves # elaboration time drastically diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index bf9f2585..d08614d7 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -33,11 +33,16 @@ case $1 in run_bmark ${mapping[$1]} ;; chipyard-dmirocket) - run_bmark ${mapping[$1]} + $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000 + make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch ;; chipyard-boom) run_bmark ${mapping[$1]} ;; + chipyard-dmiboom) + $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000 + make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch + ;; chipyard-spike) run_bmark ${mapping[$1]} ;; diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index c3e77e8b..d357637c 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -390,6 +390,35 @@ jobs: ########################################################################## + chipyard-spike-gemmini-run-tests: + name: chipyard-spike-gemmini-run-tests + needs: prepare-chipyard-accels # technically doesn't depend on RTL but should be after the build.sh for Gemmini + runs-on: ferry + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v3 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Build Gemmini FireMarshal + run: | + conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools + cd ${{ github.workspace }} && ./scripts/init-submodules-no-riscv-tools.sh --force + cd ${{ github.workspace }} && source ./scripts/fix-open-files.sh + git submodule update --init software/firemarshal && cd software/firemarshal && ./init-submodules.sh + cd ${{ github.workspace }}/generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d build gemmini-smoke.json + - name: Running Gemmini FireMarshal smoke test + run: | + conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools + cd ${{ github.workspace }}/generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d launch -s gemmini-smoke.json + chipyard-rocket-run-tests: name: chipyard-rocket-run-tests needs: prepare-chipyard-cores @@ -574,6 +603,29 @@ jobs: group-key: "group-peripherals" project-key: "chipyard-dmirocket" + chipyard-dmiboom-run-tests: + name: chipyard-dmiboom-run-tests + needs: prepare-chipyard-peripherals + runs-on: self-hosted + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v3 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Run tests + uses: ./.github/actions/run-tests + with: + group-key: "group-peripherals" + project-key: "chipyard-dmiboom" + chipyard-spiflashwrite-run-tests: name: chipyard-spiflashwrite-run-tests needs: prepare-chipyard-peripherals @@ -915,6 +967,7 @@ jobs: chipyard-cva6-run-tests, chipyard-ibex-run-tests, chipyard-sodor-run-tests, + chipyard-dmiboom-run-tests, chipyard-dmirocket-run-tests, chipyard-spiflashwrite-run-tests, chipyard-manyperipherals-run-tests, diff --git a/.gitmodules b/.gitmodules index b4beb696..5a3eb6fc 100644 --- a/.gitmodules +++ b/.gitmodules @@ -73,9 +73,6 @@ [submodule "fpga/fpga-shells"] path = fpga/fpga-shells url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git -[submodule "tools/api-config-chipsalliance"] - path = tools/api-config-chipsalliance - url = https://github.com/chipsalliance/api-config-chipsalliance.git [submodule "tools/rocket-dsp-utils"] path = tools/rocket-dsp-utils url = https://github.com/ucb-bar/rocket-dsp-utils @@ -121,3 +118,9 @@ [submodule "generators/mempress"] path = generators/mempress url = https://github.com/ucb-bar/mempress.git +[submodule "tools/cde"] + path = tools/cde + url = https://github.com/chipsalliance/cde.git +[submodule "software/embench/embench-iot"] + path = software/embench/embench-iot + url = https://github.com/embench/embench-iot.git diff --git a/CHANGELOG.md b/CHANGELOG.md index 3644fa29..8e7ed003 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,34 @@ This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/ +## [1.9.1] - 2023-04-21 + +Various fixes for Linux boot, More Chip/bringup examples, Chisel 3.5.6 bump + +### Added +* QoL improvement to IOBinders + custom ChipTop example by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1399 +* PLL integration example + FlatChipTop/TestHarness by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1427 +* Bump TestChipIp to improve default serial_tl behavior by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1435 +* Bump testchipip to standardize TL serdesser bundle params by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1446 +* HarnessBinder asserts to catch bad clock generation by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1460 + +### Changed +* New Scala-based Config Finder by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1424 +* Bump to latest rocket-chip/chisel3.5.6 by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1411 +* Resolve merge conflicts in chisel3.5.6 bump by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1430 +* bump testchipip by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1434 +* ADD: improve Makefile in tests/, add explicit arch flags by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1439 +* Various submodule bumps by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1448 +* Support not instantiating tile reset/clock contorl features by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1459 + +### Fixed +* Various improvements and fixes by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1420 +* Ensure conda cleanup regex properly filters out non-numeric chars by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1425 +* Fix ChipLikeQuadRocketConfig crossing by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1436 +* Uniquify module names that are common to Top & Model by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1442 +* Support for no-bootROM systems by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1458 +* Support for no-UART systems by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1457 + ## [1.9.0] - 2023-03-23 Faster FIRRTL build support work CIRCT. New software support for RISC-V GCC12 and Linux 6.2. Various bumps and fixes of all submodules. diff --git a/README.md b/README.md index a21b142e..91aa07ef 100644 --- a/README.md +++ b/README.md @@ -2,9 +2,6 @@ # Chipyard Framework [![Test](https://github.com/ucb-bar/chipyard/actions/workflows/chipyard-run-tests.yml/badge.svg)](https://github.com/ucb-bar/chipyard/actions) -| We're running the First FireSim and Chipyard User/Developer Workshop at ASPLOS 2023 on March 26, 2023! This workshop will feature a full-day of submitted talks from users and developers in the FireSim and Chipyard community. Learn more and **submit your work** on the [2023 Workshop Page](https://fires.im/workshop-2023/)! | -|-----| - ## Quick Links * **Stable Documentation**: https://chipyard.readthedocs.io/ diff --git a/build.sbt b/build.sbt index 05a442fb..6f72940a 100644 --- a/build.sbt +++ b/build.sbt @@ -82,7 +82,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => new Group(test.name, Seq(test), SubProcess(options)) } toSeq -val chiselVersion = "3.5.5" +val chiselVersion = "3.5.6" lazy val chiselSettings = Seq( libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion, @@ -118,11 +118,8 @@ lazy val rocketMacros = (project in rocketChipDir / "macros") ) ) -lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/build-rules/sbt") - .settings(commonSettings) - lazy val rocketchip = freshProject("rocketchip", rocketChipDir) - .dependsOn(hardfloat, rocketMacros, rocketConfig) + .dependsOn(hardfloat, rocketMacros, cde) .settings(commonSettings) .settings(chiselSettings) .settings( @@ -158,7 +155,12 @@ lazy val chipyard = (project in file("generators/chipyard")) gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, constellation, mempress) .settings(libraryDependencies ++= rocketLibDeps.value) - .settings(commonSettings) + .settings( + libraryDependencies ++= Seq( + "org.reflections" % "reflections" % "0.10.2" + ) + ) + .settings(commonSettings) lazy val mempress = (project in file("generators/mempress")) .dependsOn(rocketchip, midasTargetUtils) @@ -254,16 +256,12 @@ lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) "org.scalacheck" %% "scalacheck" % "1.14.3" % "test", )) -lazy val `api-config-chipsalliance` = freshProject("api-config-chipsalliance", file("./tools/api-config-chipsalliance")) - .settings( - commonSettings, - libraryDependencies ++= Seq( - "org.scalatest" %% "scalatest" % "3.0.+" % "test", - "org.scalacheck" %% "scalacheck" % "1.14.3" % "test", - )) +lazy val cde = (project in file("tools/cde")) + .settings(commonSettings) + .settings(Compile / scalaSource := baseDirectory.value / "cde/src/chipsalliance/rocketchip") lazy val `rocket-dsp-utils` = freshProject("rocket-dsp-utils", file("./tools/rocket-dsp-utils")) - .dependsOn(rocketchip, `api-config-chipsalliance`, dsptools) + .dependsOn(rocketchip, cde, dsptools) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) diff --git a/common.mk b/common.mk index 6934df73..94d41055 100644 --- a/common.mk +++ b/common.mk @@ -48,7 +48,7 @@ HELP_COMMANDS += \ " firrtl = generate intermediate firrtl files from chisel elaboration" \ " run-tests = run all assembly and benchmark tests" \ " launch-sbt = start sbt terminal" \ - +" find-config-fragments = list all config. fragments" ######################################################################################### # include additional subproject make fragments @@ -239,32 +239,28 @@ $(SFC_MFC_TARGETS) &: $(BTL_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler # DOC include end: FirrtlCompiler -$(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILELIST) &: $(MFC_MODEL_HRCHY_JSON) $(MFC_FILELIST) $(MFC_BB_MODS_FILELIST) - $(base_dir)/scripts/split-module-files.py \ +$(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILELIST) $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) &: $(MFC_MODEL_HRCHY_JSON) $(MFC_TOP_HRCHY_JSON) $(MFC_FILELIST) $(MFC_BB_MODS_FILELIST) + $(base_dir)/scripts/uniquify-module-names.py \ --model-hier-json $(MFC_MODEL_HRCHY_JSON) \ + --top-hier-json $(MFC_TOP_HRCHY_JSON) \ + --in-all-filelist $(MFC_FILELIST) \ --dut $(TOP) \ + --model $(MODEL) \ + --target-dir $(GEN_COLLATERAL_DIR) \ --out-dut-filelist $(TOP_MODS_FILELIST) \ --out-model-filelist $(MODEL_MODS_FILELIST) \ - --in-all-filelist $(MFC_FILELIST) \ - --target-dir $(GEN_COLLATERAL_DIR) + --out-model-hier-json $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) \ + --gcpath $(GEN_COLLATERAL_DIR) $(SED) -e 's;^;$(GEN_COLLATERAL_DIR)/;' $(MFC_BB_MODS_FILELIST) > $(BB_MODS_FILELIST) $(SED) -i 's/\.\///' $(TOP_MODS_FILELIST) $(SED) -i 's/\.\///' $(MODEL_MODS_FILELIST) $(SED) -i 's/\.\///' $(BB_MODS_FILELIST) sort -u $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(BB_MODS_FILELIST) > $(ALL_MODS_FILELIST) -$(TOP_BB_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) &: $(BB_MODS_FILELIST) $(MFC_TOP_HRCHY_JSON) $(FINAL_ANNO_FILE) - $(base_dir)/scripts/split-bb-files.py \ - --in-bb-f $(BB_MODS_FILELIST) \ - --in-top-hrchy-json $(MFC_TOP_HRCHY_JSON) \ - --in-anno-json $(FINAL_ANNO_FILE) \ - --out-top-bb-f $(TOP_BB_MODS_FILELIST) \ - --out-model-bb-f $(MODEL_BB_MODS_FILELIST) - -$(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JSON) +$(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) $(base_dir)/scripts/split-mems-conf.py \ --in-smems-conf $(MFC_SMEMS_CONF) \ - --in-model-hrchy-json $(MFC_MODEL_HRCHY_JSON) \ + --in-model-hrchy-json $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) \ --dut-module-name $(TOP) \ --model-module-name $(MODEL) \ --out-dut-smems-conf $(TOP_SMEMS_CONF) \ @@ -284,7 +280,7 @@ $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(BTL_CLASSPATH_TARGETS) $(MODEL_SMEMS # note: {MODEL,TOP}_BB_MODS_FILELIST is added as a req. so that the files get generated, # however it is really unneeded since ALL_MODS_FILELIST includes all BB files ######################################################################################## -$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE) $(TOP_BB_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) +$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE) $(BB_MODS_FILELIST) sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' > $@ echo "$(TOP_SMEMS_FILE)" >> $@ echo "$(MODEL_SMEMS_FILE)" >> $@ @@ -304,6 +300,11 @@ check-binary: ifeq (,$(BINARY)) $(error BINARY variable is not set. Set it to the simulation binary) endif +ifneq (none,$(BINARY)) +ifeq ("$(wildcard $(BINARY))","") + $(error BINARY=$(BINARY) not found) +endif +endif # allow you to override sim prereq ifeq (,$(BREAK_SIM_PREREQ)) @@ -321,34 +322,23 @@ run-binary-fast: $(SIM_PREREQ) check-binary | $(output_dir) # run simulator with as much debug info as possible run-binary-debug: $(SIM_DEBUG_PREREQ) check-binary | $(output_dir) +ifneq (none,$(BINARY)) + riscv64-unknown-elf-objdump -D $(BINARY) > $(sim_out_name).dump +endif (set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) run-fast: run-asm-tests-fast run-bmark-tests-fast ######################################################################################### -# helper rules to run simulator with fast loadmem via hex files +# helper rules to run simulator with fast loadmem +# LEGACY - use LOADMEM=1 instead ######################################################################################### -$(binary_hex): $(firstword $(BINARY)) | $(output_dir) - $(base_dir)/scripts/smartelf2hex.sh $(firstword $(BINARY)) > $(binary_hex) - -run-binary-hex: check-binary -run-binary-hex: $(SIM_PREREQ) $(binary_hex) | $(output_dir) run-binary-hex: run-binary -run-binary-hex: override LOADMEM_ADDR = 80000000 -run-binary-hex: override LOADMEM = $(binary_hex) -run-binary-hex: override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) -run-binary-debug-hex: check-binary -run-binary-debug-hex: $(SIM_DEBUG_REREQ) $(binary_hex) | $(output_dir) +run-binary-hex: override SIM_FLAGS += +loadmem=$(BINARY) run-binary-debug-hex: run-binary-debug -run-binary-debug-hex: override LOADMEM_ADDR = 80000000 -run-binary-debug-hex: override LOADMEM = $(binary_hex) -run-binary-debug-hex: override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) -run-binary-fast-hex: check-binary -run-binary-fast-hex: $(SIM_PREREQ) $(binary_hex) | $(output_dir) +run-binary-debug-hex: override SIM_FLAGS += +loadmem=$(BINARY) run-binary-fast-hex: run-binary-fast -run-binary-fast-hex: override LOADMEM_ADDR = 80000000 -run-binary-fast-hex: override LOADMEM = $(binary_hex) -run-binary-fast-hex: override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) +run-binary-fast-hex: override SIM_FLAGS += +loadmem=$(BINARY) ######################################################################################### # run assembly/benchmarks rules @@ -398,13 +388,9 @@ define \n endef -CONFIG_FRAG_LEVELS ?= 3 .PHONY: find-config-fragments -find-config-fragments: private IN_F := $(shell mktemp -d -t cy-XXXXXXXX)/scala_files.f -find-config-fragments: $(SCALA_SOURCES) - @$(foreach file,$(SCALA_SOURCES),echo $(file) >> $(IN_F)${\n}) - $(base_dir)/scripts/config-finder.py -l $(CONFIG_FRAG_LEVELS) $(IN_F) - @rm -rf $(dir $(IN_F)) +find-config-fragments: + $(call run_scala_main,chipyard,chipyard.ConfigFinder,) .PHONY: help help: diff --git a/conda-reqs/chipyard.yaml b/conda-reqs/chipyard.yaml index 59c5de51..d1d9eab9 100644 --- a/conda-reqs/chipyard.yaml +++ b/conda-reqs/chipyard.yaml @@ -89,7 +89,7 @@ dependencies: - graphviz - expect - dtc - - verilator==4.226 + - verilator==5.008 - screen - elfutils - libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock @@ -103,7 +103,7 @@ dependencies: - sty - open_pdks.sky130a - pip: - - hammer-vlsi[asap7]==1.1.0 + - hammer-vlsi[asap7]==1.1.1 # doc requirements - sphinx @@ -131,7 +131,7 @@ dependencies: - pytest-mock - moto - mypy - - s3fs + - s3fs==0.4.2 - aiohttp - pip: - sure diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml index 6c22731e..4899b455 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml @@ -9,7 +9,7 @@ # To update a single package to the latest version compatible with the version constraints in the source: # conda-lock lock --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml --update PACKAGE # To re-solve the entire environment, e.g. after changing a version constraint in the source file: -# conda-lock -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml +# conda-lock -f /scratch/abejgonza/cy/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml metadata: channels: - url: ucb-bar @@ -21,12 +21,12 @@ metadata: - url: nodefaults used_env_vars: [] content_hash: - linux-64: cee2f923f616452b736c4314db2e791c5402803fdf7a7e344bb8233950f19b67 + linux-64: 86382a6fa6e58883c85e482f6c209ab347df1461d7c5706f28b95813412dfe94 platforms: - linux-64 sources: - - /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml - - /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/esp-tools.yaml + - /scratch/abejgonza/cy/conda-reqs/chipyard.yaml + - /scratch/abejgonza/cy/conda-reqs/esp-tools.yaml package: - category: main dependencies: {} @@ -42,13 +42,13 @@ package: - category: main dependencies: {} hash: - md5: a581b4a89191b6c1d6a16488a9cffbfc - sha256: 695e67ae4bc22f9e0be5f54b1948a8f2b678f4da920fa2082a249dd5a88f440e + md5: f6ce7955b53ae1ca83144adb3be9c600 + sha256: 546e4eb1cbd822a66b363ec3fbdcc4fcc53853bcab57674cb46b8f3209b856f2 manager: conda name: _sysroot_linux-64_curr_repodata_hack optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h5bd9786_13.tar.bz2 + url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h69a702a_13.conda version: '3' - category: main dependencies: {} @@ -64,14 +64,14 @@ package: - category: main dependencies: {} hash: - md5: ff9f73d45c4a07d6f424495288a26080 - sha256: 8f6c81b0637771ae0ea73dc03a6d30bec3326ba3927f2a7b91931aa2d59b1789 + md5: f5c65075fc34438d5b456c7f3f5ab695 + sha256: 0cf1bb3d0bfc5519b60af2c360fa4888fb838e1476b1e0f65b9dbc48b45c7345 manager: conda name: ca-certificates optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/ca-certificates-2022.12.7-ha878542_0.conda - version: 2022.12.7 + url: https://conda.anaconda.org/conda-forge/linux-64/ca-certificates-2023.5.7-hbcca054_0.conda + version: 2023.5.7 - category: main dependencies: {} hash: @@ -185,14 +185,14 @@ package: - category: main dependencies: {} hash: - md5: 7697d37e29669a14b053e82fad22a16b - sha256: ac993fa2774b90befcd6aba55b1c08853b2fa3b818753094c09bebd35fc55532 + md5: 0299e410bfb4300540bdc0012a7985ef + sha256: 8572efb7092c72fe7b73d2a0f1e5e27159a8edea0371e1bef533bcb7d85b19c6 manager: conda name: open_pdks.sky130a optional: false platform: linux-64 - url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.402_1_g12df12e-20230225_164303.tar.bz2 - version: 1.0.402_1_g12df12e + url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.406_0_g0c37b7c-20230412_103222.tar.bz2 + version: 1.0.406_0_g0c37b7c - category: main dependencies: {} hash: @@ -207,14 +207,14 @@ package: - category: main dependencies: {} hash: - md5: 51fc4fcfb19f5d95ffc8c339db5068e8 - sha256: 0bfae0b9962bc0dbf79048f9175b913ed4f53c4310d06708dc7acbb290ad82f6 + md5: 939e3e74d8be4dac89ce83b20de2492a + sha256: 0449138224adfa125b220154408419ec37c06b0b49f63c5954724325903ecf55 manager: conda name: tzdata optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2022g-h191b570_0.conda - version: 2022g + url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2023c-h71feb2d_0.conda + version: 2023c - category: main dependencies: font-ttf-dejavu-sans-mono: '' @@ -394,14 +394,14 @@ package: dependencies: libgcc-ng: '>=12' hash: - md5: 80968e6760b2448f739cd32b1324d07d - sha256: c8b52559c1867ad59510c9479a15581cbfda0a7857a33ff2fce03a76a0775cfb + md5: 2975fe44881f8dce5c3759b53abf11d1 + sha256: 1c65245dc63a3f5a57040074c61baa2ae9dcb401753503712401867b02c6dcab manager: conda name: coreutils optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/coreutils-9.2-h0b41bf4_0.conda - version: '9.2' + url: https://conda.anaconda.org/conda-forge/linux-64/coreutils-9.3-h0b41bf4_0.conda + version: '9.3' - category: main dependencies: libgcc-ng: '>=7.3.0' @@ -426,19 +426,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/ucb-bar/linux-64/dromajo-1.0.0-0_h1234567_g6a6e34e.tar.bz2 version: 1.0.0 -- category: main - dependencies: - libgcc-ng: '>=12' - libstdcxx-ng: '>=12' - hash: - md5: c4fbad8d4bddeb3c085f18cbf97fbfad - sha256: b44db0b92ae926b3fbbcd57c179fceb64fa11a9f9d09082e03be58b74dcad832 - manager: conda - name: expat - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/expat-2.5.0-h27087fc_0.tar.bz2 - version: 2.5.0 - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -528,29 +515,17 @@ package: version: '1.12' - category: main dependencies: - libgcc-ng: '>=10.3.0' - libstdcxx-ng: '>=10.3.0' + libgcc-ng: '>=12' + libstdcxx-ng: '>=12' hash: - md5: 87473a15119779e021c314249d4b4aed - sha256: 1d7950f3be4637ab915d886304e57731d39a41ab705ffc95c4681655c459374a + md5: 7c8d20d847bb45f56bd941578fcfa146 + sha256: e44cc00eec068e7f7a6dd117ba17bf5d57658729b7b841945546f82505138292 manager: conda name: icu optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/icu-70.1-h27087fc_0.tar.bz2 - version: '70.1' -- category: main - dependencies: - libgcc-ng: '>=12' - hash: - md5: c7a069243e1fbe9a556ed2ec030e6407 - sha256: 8f73194d09c9ea4a7e2b3562766b8d72125cc147b62c7cf83393e3a3bbfd581b - manager: conda - name: jpeg - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/jpeg-9e-h0b41bf4_3.conda - version: 9e + url: https://conda.anaconda.org/conda-forge/linux-64/icu-72.1-hcb278e6_0.conda + version: '72.1' - category: main dependencies: libgcc-ng: '>=10.3.0' @@ -592,14 +567,14 @@ package: dependencies: libgcc-ng: '>=12' hash: - md5: 5cc781fd91968b11a8a7fdbee0982676 - sha256: f9983a8ea03531f2c14bce76c870ca325c0fddf0c4e872bff1f78bc52624179c + md5: 6aa9c9de5542ecb07fdda9ca626252d8 + sha256: 949d84ceea543802c1e085b2aa58f1d6cb5dd8cec5a9abaaf4e8ac65d6094b3a manager: conda name: libdeflate optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libdeflate-1.17-h0b41bf4_0.conda - version: '1.17' + url: https://conda.anaconda.org/conda-forge/linux-64/libdeflate-1.18-h0b41bf4_0.conda + version: '1.18' - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -612,6 +587,18 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libev-4.33-h516909a_1.tar.bz2 version: '4.33' +- category: main + dependencies: + libgcc-ng: '>=12' + hash: + md5: 6305a3dd2752c76335295da4e581f2fd + sha256: 74c98a563777ae2ad71f1f74d458a8ab043cee4a513467c159ccf159d0e461f3 + manager: conda + name: libexpat + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/libexpat-2.5.0-hcb278e6_1.conda + version: 2.5.0 - category: main dependencies: libgcc-ng: '>=12' @@ -648,6 +635,18 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libiconv-1.17-h166bdaf_0.tar.bz2 version: '1.17' +- category: main + dependencies: + libgcc-ng: '>=12' + hash: + md5: 1edd9e67bdb90d78cea97733ff6b54e6 + sha256: b19de7bda34eac4fa931be11fa8d7640cdf1441dfd51c91786586a4a4c64c92f + manager: conda + name: libjpeg-turbo + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/libjpeg-turbo-2.1.5.1-h0b41bf4_0.conda + version: 2.1.5.1 - category: main dependencies: libgcc-ng: '>=9.4.0' @@ -736,16 +735,16 @@ package: version: 0.9.10 - category: main dependencies: - libgcc-ng: '>=9.3.0' + libgcc-ng: '>=12' hash: - md5: 772d69f030955d9646d3d0eaf21d859d - sha256: 54f118845498353c936826f8da79b5377d23032bcac8c4a02de2019e26c3f6b3 + md5: 40b61aab5c7ba9ff276c41cfffe6b80b + sha256: 787eb542f055a2b3de553614b25f09eefb0a0931b0c87dbcce6efdfd92f04f18 manager: conda name: libuuid optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libuuid-2.32.1-h7f98852_1000.tar.bz2 - version: 2.32.1 + url: https://conda.anaconda.org/conda-forge/linux-64/libuuid-2.38.1-h0b41bf4_0.conda + version: 2.38.1 - category: main dependencies: libgcc-ng: '>=12' @@ -762,14 +761,14 @@ package: dependencies: libgcc-ng: '>=12' hash: - md5: ac2ccf7323d21f2994e4d1f5da664f37 - sha256: 221f2e138dd264b7394b88f08884d93825d38800a51415059e813c02467abfd1 + md5: 0d4a7508d8c6c65314f2b9c1f56ad408 + sha256: ac3e073ea77803da71eb77e7fcef07defb345bda95eee3327c73ddf85b5714da manager: conda name: libwebp-base optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-base-1.2.4-h166bdaf_0.tar.bz2 - version: 1.2.4 + url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-base-1.3.0-h0b41bf4_0.conda + version: 1.3.0 - category: main dependencies: libgcc-ng: '>=12' @@ -872,13 +871,13 @@ package: ca-certificates: '' libgcc-ng: '>=12' hash: - md5: 2d833be81a21128e317325a01326d36f - sha256: d378afcec34b86fef4da3ebd622b3e614cb3f71e54b6a5a10adb1d23745ecc72 + md5: 8f24d371ed9efb3f0b0de383fb81d51c + sha256: 24bf6cf8f741c28a8d10f51c917f378694d4a98a38ab4372629932cd6c94e9e8 manager: conda name: openssl optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/openssl-3.1.0-h0b41bf4_0.conda + url: https://conda.anaconda.org/conda-forge/linux-64/openssl-3.1.0-hd590300_3.conda version: 3.1.0 - category: main dependencies: @@ -954,15 +953,15 @@ package: version: '6.0' - category: main dependencies: - libgcc-ng: '>=7.3.0' + libgcc-ng: '>=12' hash: - md5: 2e5f1a8199794b21c9472c1a7f27e21a - sha256: a3ee6c02932fbee32babe39fa6bda9f781d6dc17122d2a90e62ff2b6866a5de8 + md5: 76d6bc123c1c75bf034c412856fcc935 + sha256: e94d0d5f75a5f58165ad8ac64a25df851c77ec6e9bf626c16807dcbd740226c8 manager: conda name: which optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/which-2.21-h516909a_0.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/which-2.21-h0b41bf4_1.conda version: '2.21' - category: main dependencies: @@ -1135,6 +1134,19 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/dtc-1.6.1-h166bdaf_2.tar.bz2 version: 1.6.1 +- category: main + dependencies: + libexpat: 2.5.0 hcb278e6_1 + libgcc-ng: '>=12' + hash: + md5: 8b9b5aca60558d02ddaa09d599e55920 + sha256: 36dfeb4375059b3bba75ce9b38c29c69fd257342a79e6cf20e9f25c1523f785f + manager: conda + name: expat + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/expat-2.5.0-hcb278e6_1.conda + version: 2.5.0 - category: main dependencies: gettext: '' @@ -1334,14 +1346,14 @@ package: libgcc-ng: '>=12' libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: 2e5f9a37d487e1019fd4d8113adb2f9f - sha256: 6008a0b914bd1a3510a3dba38eada93aa0349ebca3a21e5fa276833c8205bf49 + md5: 1d002bf709048f8021c32abfd0e0d395 + sha256: bb2a8ddb26e74f2cedc36825fc6f95d45f19e1912a1a6c75847952d92fc16215 manager: conda name: libsqlite optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libsqlite-3.40.0-h753d276_0.tar.bz2 - version: 3.40.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libsqlite-3.41.2-h2797004_1.conda + version: 3.41.2 - category: main dependencies: libgcc-ng: '>=12' @@ -1373,20 +1385,20 @@ package: version: '1.13' - category: main dependencies: - icu: '>=70.1,<71.0a0' + icu: '>=72.1,<73.0a0' libgcc-ng: '>=12' libiconv: '>=1.17,<2.0a0' libzlib: '>=1.2.13,<1.3.0a0' xz: '>=5.2.6,<6.0a0' hash: - md5: bb808b654bdc3c783deaf107a2ffb503 - sha256: d4170f1fe356768758b13a51db123f990bff81b0eae0d5a0ba11c7ca6b9536f4 + md5: 241845899caff54ac1d2b3102ad988cf + sha256: 624b6e29e23a51353cff2aff7364c42b831139afd131d239e79f60aea4dae887 manager: conda name: libxml2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libxml2-2.10.3-hca2bb57_4.conda - version: 2.10.3 + url: https://conda.anaconda.org/conda-forge/linux-64/libxml2-2.10.4-hfdac1af_0.conda + version: 2.10.4 - category: main dependencies: libgcc-ng: '>=7.3.0' @@ -1472,14 +1484,14 @@ package: libgcc-ng: '>=12' ncurses: '>=6.3,<7.0a0' hash: - md5: db2ebbe2943aae81ed051a6a9af8e0fa - sha256: f5f383193bdbe01c41cb0d6f99fec68e820875e842e6e8b392dbe1a9b6c43ed8 + md5: 47d31b792659ce70f470b5c82fdfb7a4 + sha256: 5435cf39d039387fbdc977b0a762357ea909a7694d9528ab40f005e9208744d7 manager: conda name: readline optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/readline-8.1.2-h0f457ee_0.tar.bz2 - version: 8.1.2 + url: https://conda.anaconda.org/conda-forge/linux-64/readline-8.2-h8228510_1.conda + version: '8.2' - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -1589,17 +1601,17 @@ package: version: '2.71' - category: main dependencies: - libgcc-ng: '>=10.3.0' - readline: '>=8.1,<9.0a0' + libgcc-ng: '>=12' + readline: '>=8.2,<9.0a0' hash: - md5: 54d1a374b75f14ecc58aea8c4236c0c3 - sha256: 6415903ad8774fc0f1bf5b156ae0b6f9988427a0f14bb35467c5938f05fe8707 + md5: 23b559a791d63ba4f51906763eb6bc53 + sha256: a7b2ea50068d86ac6e3749f76b118b15947d3f5ce48535eb5ab2ff7e22659c49 manager: conda name: bash optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/bash-5.1.16-hd863ed2_0.tar.bz2 - version: 5.1.16 + url: https://conda.anaconda.org/conda-forge/linux-64/bash-5.2.15-hfbf034d_0.conda + version: 5.2.15 - category: main dependencies: flex: '' @@ -1685,13 +1697,13 @@ package: dependencies: gcc_impl_linux-64: 12.2.0.* hash: - md5: b4d86475bd1a21d139ea78770f606471 - sha256: 3cfb989723f8e115d35553c2b1d899b0f4185fc0551a996b9ff4037083a36432 + md5: ec93d13e0fe8514f65842120dbae1b16 + sha256: 5478f5b7672b6c2d5b644aaa9fe18fbb1468ca6ea9cea1b0f0a2254459438e24 manager: conda name: gcc optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gcc-12.2.0-h26027b1_11.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/gcc-12.2.0-h26027b1_13.conda version: 12.2.0 - category: main dependencies: @@ -1782,14 +1794,14 @@ package: libzlib: '>=1.2.13,<1.3.0a0' pcre2: '>=10.40,<10.41.0a0' hash: - md5: ed5349aa96776e00b34eccecf4a948fe - sha256: 3cbad3d63cff2dd9ac1dc9cce54fd3d657f3aff53df41bfe5bae9d760562a5af + md5: db1d4a1dfc04f3eab50d97551850759a + sha256: e0d54ffe98b7471cfc95f043bf3921412843c05ba5f1f10ceeac5edb328ac928 manager: conda name: libglib optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libglib-2.74.1-h606061b_1.tar.bz2 - version: 2.74.1 + url: https://conda.anaconda.org/conda-forge/linux-64/libglib-2.76.2-hebfc3b9_0.conda + version: 2.76.2 - category: main dependencies: libblas: 3.9.0 16_linux64_openblas @@ -1806,37 +1818,37 @@ package: dependencies: libgcc-ng: '>=12' libstdcxx-ng: '>=12' - libxml2: '>=2.10.3,<2.11.0a0' + libxml2: '>=2.10.4,<2.11.0a0' libzlib: '>=1.2.13,<1.3.0a0' zstd: '>=1.5.2,<1.6.0a0' hash: - md5: 17d91085ccf5934ce652cb448d0cb65a - sha256: f649fac60cb122bf0d85c4955725d94c353fdbd768bcd44f0444979b363cc9ab + md5: 3d942f062d7656168bb42b3439bdfede + sha256: c52c239b583a1b2d03bdc641afd8cbab0499b0a46ea55b40e1dbed112283a772 manager: conda - name: libllvm15 + name: libllvm16 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libllvm15-15.0.7-hadd5161_1.conda - version: 15.0.7 + url: https://conda.anaconda.org/conda-forge/linux-64/libllvm16-16.0.3-hbf9e925_1.conda + version: 16.0.3 - category: main dependencies: - jpeg: '>=9e,<10a' lerc: '>=4.0.0,<5.0a0' - libdeflate: '>=1.17,<1.18.0a0' + libdeflate: '>=1.18,<1.19.0a0' libgcc-ng: '>=12' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libstdcxx-ng: '>=12' - libwebp-base: '>=1.2.4,<2.0a0' + libwebp-base: '>=1.3.0,<2.0a0' libzlib: '>=1.2.13,<1.3.0a0' xz: '>=5.2.6,<6.0a0' zstd: '>=1.5.2,<1.6.0a0' hash: - md5: 2e648a34072eb39d7c4fc2a9981c5f0c - sha256: e3e18d91fb282b61288d4fd2574dfa31f7ae90ef2737f96722fb6ad3257862ee + md5: 4e5ee4b062c21519efbee7e2ae608748 + sha256: caacb23e1b95fbdd8115be69228f9c82068ed87bf57f055027e31d093ae6a1a2 manager: conda name: libtiff optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libtiff-4.5.0-h6adf6a1_2.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libtiff-4.5.0-ha587672_6.conda version: 4.5.0 - category: main dependencies: @@ -1917,19 +1929,19 @@ package: - category: main dependencies: libgcc-ng: '>=12' - libsqlite: 3.40.0 h753d276_0 + libsqlite: 3.41.2 h2797004_1 libzlib: '>=1.2.13,<1.3.0a0' ncurses: '>=6.3,<7.0a0' - readline: '>=8.1.2,<9.0a0' + readline: '>=8.2,<9.0a0' hash: - md5: bb11803129cbbb53ed56f9506ff74145 - sha256: baf0e77938e5215653aa6609ff154cb94aeb0a08083ff8dec2d3ba8dd62263e9 + md5: c8771266cc289756099c04e597209862 + sha256: 2674e5b0888799ad055bdbc79e2257d67f52b0c11f4c174d4deff4b69874cf45 manager: conda name: sqlite optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/sqlite-3.40.0-h4ff8645_0.tar.bz2 - version: 3.40.0 + url: https://conda.anaconda.org/conda-forge/linux-64/sqlite-3.41.2-h2c6b66d_1.conda + version: 3.41.2 - category: main dependencies: libgcc-ng: '>=9.4.0' @@ -1988,16 +2000,16 @@ package: version: 1.4.4 - category: main dependencies: - python: '>=3.6' + python: '>=3.7' hash: - md5: b3c15cb1d45fd10bc6f652bbc51e023a - sha256: 8dbc6de55113ea67a64f0be5d16ba939d1b58a25dbd9a5cc62b571cef24ef85c + md5: 0b3460f5bf4ae27dfd72fdcccc9667a9 + sha256: 18aad01518cb08e4eff18e507e14ebf6c522d89ef53ca267c48080933c4435f7 manager: conda name: argcomplete optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.0.2-pyhd8ed1ab_0.conda - version: 3.0.2 + url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.0.8-pyhd8ed1ab_0.conda + version: 3.0.8 - category: main dependencies: libgcc-ng: '>=12' @@ -2014,16 +2026,28 @@ package: version: 2.38.0 - category: main dependencies: - python: '>=3.5' + python: '>=3.7' hash: - md5: 8b76db7818a4e401ed4486c4c1635cd9 - sha256: 3a58d4a4933fa8735471c782d35326ab78e0bcfce84756408515f82a94e4dec4 + md5: 3edfead7cedd1ab4400a6c588f3e75f8 + sha256: 063639cd568f5c7a557b0fb1cc27f098598c0d8ff869088bfeb82934674f8821 manager: conda name: attrs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/attrs-22.2.0-pyh71513ae_0.conda - version: 22.2.0 + url: https://conda.anaconda.org/conda-forge/noarch/attrs-23.1.0-pyh71513ae_1.conda + version: 23.1.0 +- category: main + dependencies: + python: '>=3.7' + hash: + md5: 2fb79ec81bad9492b6d59a06b3b647a4 + sha256: b6f32491536823e47cf6eb4717dd341385600a2b901235028dedc629a77aeb82 + manager: conda + name: blinker + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/blinker-1.6.2-pyhd8ed1ab_0.conda + version: 1.6.2 - category: main dependencies: brotli-bin: 1.0.9 h166bdaf_8 @@ -2055,14 +2079,14 @@ package: dependencies: python: '>=3.7' hash: - md5: fb9addc3db06e56abe03e0e9f21a63e6 - sha256: 5e22af4776700200fab2c1df41a2188ab9cfe90a50c4f388592bb978562c88ec + md5: 5d1b71c942b8421285934dad1d891ebc + sha256: f839a6e04d94069f90dd85337ea9108f058dc76771bb469a413f32bb1ba0b256 manager: conda name: certifi optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/certifi-2022.12.7-pyhd8ed1ab_0.conda - version: 2022.12.7 + url: https://conda.anaconda.org/conda-forge/noarch/certifi-2023.5.7-pyhd8ed1ab_0.conda + version: 2023.5.7 - category: main dependencies: python: '>=3.6.1' @@ -2089,16 +2113,16 @@ package: version: 2.1.1 - category: main dependencies: - __unix: '' - python: '>=3.8' + python: '>=3.9,<3.10.0a0' + python_abi: 3.9.* *_cp39 hash: - md5: 20e4087407c7cb04a40817114b333dbf - sha256: 23676470b591b100393bb0f6c46fe10624dcbefc696a6a9f42932ed8816ef0ea + md5: 3613ff4128b3e565d048106196206929 + sha256: 21c425ecc4e6f4ec97aab1285b22ad629c75d2efb62f89cd6d9618ab6a2e606c manager: conda name: click optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/click-8.1.3-unix_pyhd8ed1ab_2.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/click-8.1.3-py39hf3d152e_1.tar.bz2 version: 8.1.3 - category: main dependencies: @@ -2220,14 +2244,14 @@ package: dependencies: python: '>=3.7' hash: - md5: 6f90f1dc834447823b11d155726fcb37 - sha256: 6a6901f20c5b4d81aebd25a0645b3578ebb6a323f9fd7e87ee05ecbcfe19069e + md5: 650f18a56f366dbf419c15b543592c2d + sha256: 68db3a6280d6786be76f2c7c6cf41dd878c5d1a24f5de10f7f0af82c6fcfade6 manager: conda name: filelock optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/filelock-3.10.0-pyhd8ed1ab_0.conda - version: 3.10.0 + url: https://conda.anaconda.org/conda-forge/noarch/filelock-3.12.0-pyhd8ed1ab_0.conda + version: 3.12.0 - category: main dependencies: expat: '>=2.5.0,<3.0a0' @@ -2262,29 +2286,30 @@ package: dependencies: python: '>=3.8' hash: - md5: 0db48a2f5a68e28e5af8d3df276f2255 - sha256: dfcee90620d13f4f667664620191d780c79ec7e9ba9908cd771d24a1361e0cc9 + md5: 20edd290b319aa0eff3e9055375756dc + sha256: cbb5c77c0217cda9bf4f4240158de11822a099a6eaa05ba626e822819a54f46d manager: conda name: fsspec optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/fsspec-2023.3.0-pyhd8ed1ab_1.conda - version: 2023.3.0 + url: https://conda.anaconda.org/conda-forge/noarch/fsspec-2023.5.0-pyh1a96a4e_0.conda + version: 2023.5.0 - category: main dependencies: - jpeg: '>=9e,<10a' libgcc-ng: '>=12' libglib: '>=2.74.1,<3.0a0' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libpng: '>=1.6.39,<1.7.0a0' libtiff: '>=4.5.0,<4.6.0a0' + libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: 1a109126a43003d65b39c1cad656bc9b - sha256: a27f49d85e0a730374cc77606e9484b23b0f3edf32df1994b6d7ff5dd44aef92 + md5: ee8220db21db8094998005990418fe5b + sha256: 7acc699871310e9a89aaa7e90de9ac949e2fa649232c8a8dfcafa67e8f36a266 manager: conda name: gdk-pixbuf optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gdk-pixbuf-2.42.10-h05c8ddd_0.conda + url: https://conda.anaconda.org/conda-forge/linux-64/gdk-pixbuf-2.42.10-h6b639ba_2.conda version: 2.42.10 - category: main dependencies: @@ -2322,13 +2347,13 @@ package: gcc: 12.2.0.* gxx_impl_linux-64: 12.2.0.* hash: - md5: 2b54322e0dbb1345d64913e8b20b7d7c - sha256: f6c390055f2846d6013160c41dece0973daf577c5f1aaa73ff5dcf597b35d0ec + md5: de605ff437f3fdc010f1b529642339f1 + sha256: 58bc0a7ff843c4ac2fd53b1370d266d635b59cf8d1d6f165cc26cf1f5324c9f8 manager: conda name: gxx optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gxx-12.2.0-h26027b1_11.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/gxx-12.2.0-h26027b1_13.conda version: 12.2.0 - category: main dependencies: @@ -2456,48 +2481,46 @@ package: version: 1.4.4 - category: main dependencies: - jpeg: '>=9e,<10a' libgcc-ng: '>=12' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libtiff: '>=4.5.0,<4.6.0a0' hash: - md5: aa8840cdf17ef0c6084d1e24abc7a28b - sha256: 443e926b585528112ec6aa4d85bf087722914ed8d85a2f75ae47c023c55c4238 + md5: 980d8aca0bc23ca73fa8caa3e7c84c28 + sha256: 0d88e0e7f8dbf8f01788e21dd63dd49b89433ce7dfd10f53839441396f6481cd manager: conda name: lcms2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/lcms2-2.15-hfd0df8a_0.conda + url: https://conda.anaconda.org/conda-forge/linux-64/lcms2-2.15-haa2dc70_1.conda version: '2.15' - category: main dependencies: libgcc-ng: '>=12' - libllvm15: '>=15.0.7,<15.1.0a0' + libllvm16: '>=16.0.3,<16.1.0a0' libstdcxx-ng: '>=12' - libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: 276ec1f956a520363016f909ec166f65 - sha256: 48c0820ba1fe5701d11a5b7967a2c93d73607741a20e511214ece7fec7b9dc7f + md5: 205aca93c1bc4a0bc663dd787c224025 + sha256: 66e0e925088acbc1306c814ca8441e61dd2f2a2ff93ff752b914939b87864d24 manager: conda - name: libclang-cpp15 + name: libclang-cpp16 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libclang-cpp15-15.0.7-default_had23c3d_1.conda - version: 15.0.7 + url: https://conda.anaconda.org/conda-forge/linux-64/libclang-cpp16-16.0.3-default_h83cc7fd_0.conda + version: 16.0.3 - category: main dependencies: libgcc-ng: '>=12' - libllvm15: '>=15.0.7,<15.1.0a0' + libllvm16: '>=16.0.3,<16.1.0a0' libstdcxx-ng: '>=12' - libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: a3a0f7a6f0885f5e1e0ec691566afb77 - sha256: e48481c37d02aefeddcfac20d48cf13b838c5f7b9018300fa7eac404d30f3d7f + md5: e0f95087543b73c7bc2689f0aeb86a6d + sha256: 40c7a6ebfe181b3683fa4c0a378ff25eca1a77d68c35578b9c237dd58c4d458d manager: conda name: libclang13 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libclang13-15.0.7-default_h3e3d535_1.conda - version: 15.0.7 + url: https://conda.anaconda.org/conda-forge/linux-64/libclang13-16.0.3-default_hd781213_0.conda + version: 16.0.3 - category: main dependencies: krb5: '>=1.20.1,<1.21.0a0' @@ -2559,20 +2582,20 @@ package: - category: main dependencies: giflib: '>=5.2.1,<5.3.0a0' - jpeg: '>=9e,<10a' libgcc-ng: '>=12' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libpng: '>=1.6.39,<1.7.0a0' libtiff: '>=4.5.0,<4.6.0a0' - libwebp-base: '>=1.2.4,<2.0a0' + libwebp-base: '>=1.3.0,<2.0a0' hash: - md5: 77003f63d1763c1e6569a02c1742c9f4 - sha256: 43d563a16fe9db32b7d0be8d89968005f21139e9285dfe1fbfe9ae6647f1cc9f + md5: 9cfd7ad6e1539ca1ad172083586b3301 + sha256: 461fe2c0279309c21f206f114f3bd6592e906ef6f8cc181b2e28482941b8b925 manager: conda name: libwebp optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-1.2.4-h1daa5a0_1.conda - version: 1.2.4 + url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-1.3.0-hb47c5f0_0.conda + version: 1.3.0 - category: main dependencies: python: '' @@ -2686,14 +2709,14 @@ package: python: '>=3.9,<3.10.0a0' python_abi: 3.9.* *_cp39 hash: - md5: 757070dc7cc33003254888808cd34f1e - sha256: c0418aa18f4fd37d3ac786058bfa29cca0b5b8eca95a2e0ae2fdd13aefc81ad6 + md5: 8626d6d5169950ce4b99b082667773f7 + sha256: c8fac78b5292c279449e4ccba03661dd75f9d39b0f5d40b8bf55c3fcd89f64ce manager: conda name: numpy optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/numpy-1.24.2-py39h7360e5f_0.conda - version: 1.24.2 + url: https://conda.anaconda.org/conda-forge/linux-64/numpy-1.24.3-py39h6183b62_0.conda + version: 1.24.3 - category: main dependencies: libgcc-ng: '>=12' @@ -2714,14 +2737,14 @@ package: dependencies: python: '>=3.7' hash: - md5: 1ff2e3ca41f0ce16afec7190db28288b - sha256: 00288f5e5e841711e8b8fef1f1242c858d8ef99ccbe5d7e0df4789d5d8d40645 + md5: 91cda59e66e1e4afe9476f8ef98f5c30 + sha256: ded536a96a00d45a693dbc2971bb688248324dadd129eddda2100e177583d768 manager: conda name: packaging optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/packaging-23.0-pyhd8ed1ab_0.conda - version: '23.0' + url: https://conda.anaconda.org/conda-forge/noarch/packaging-23.1-pyhd8ed1ab_0.conda + version: '23.1' - category: main dependencies: python: '>=2.7' @@ -2748,15 +2771,16 @@ package: version: 1.9.6 - category: main dependencies: - python: '>=3.8' + python: '>=3.9,<3.10.0a0' + python_abi: 3.9.* *_cp39 hash: - md5: 7d301a0d25f424d96175f810935f0da9 - sha256: c25e1757e4e90638bb1e778aba3ee5f3c01fae9752e3c3929f9be7d367f6c7f3 + md5: d86903c57fe229d9dd8878a6dd9d149f + sha256: abf2d34464c6255d35703e3c9477475e3e6e353ca8675990596d2477cdbc5b52 manager: conda name: pluggy optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pluggy-1.0.0-pyhd8ed1ab_5.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/pluggy-1.0.0-py39hf3d152e_4.tar.bz2 version: 1.0.0 - category: main dependencies: @@ -2777,14 +2801,14 @@ package: python: '>=3.9,<3.10.0a0' python_abi: 3.9.* *_cp39 hash: - md5: 12184951da572828fb986b06ffb63eed - sha256: 515cf2cfc0504eb5758fa9ddfabc1dcbd7182da7650828aac97c9eee35597c84 + md5: 1d54d3a75c3192ab7655d9c3d16809f1 + sha256: 846894b31bf26061a9e83b03b10fe46f49fcf1ffc5fb1c7ed79a61706a57004b manager: conda name: psutil optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/psutil-5.9.4-py39hb9d737c_0.tar.bz2 - version: 5.9.4 + url: https://conda.anaconda.org/conda-forge/linux-64/psutil-5.9.5-py39h72bdee0_0.conda + version: 5.9.5 - category: main dependencies: python: '' @@ -2823,18 +2847,30 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/pycparser-2.21-pyhd8ed1ab_0.tar.bz2 version: '2.21' +- category: main + dependencies: + python: '>=3.7' + hash: + md5: d316679235612869eba305aa7d41d9bf + sha256: 1bddeb54863c77ed5613b535a3e06a3a16b55786301a5e28c9bf011656bda686 + manager: conda + name: pygments + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/pygments-2.15.1-pyhd8ed1ab_0.conda + version: 2.15.1 - category: main dependencies: python: '>=3.6' hash: - md5: 56d08bbebf5b3719ca2b1688fcfd98a4 - sha256: 177ce344fc9668cc1e7daa637ef375f6765e60fbb52e83a5744a0513751200aa + md5: 99e28be5a278e2319834d7dc99e7bfdd + sha256: f3a64306fa0f405f10f4108d7ff42043d6fd393f940f9e98e395a3756687fc98 manager: conda name: pyjwt optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pyjwt-2.6.0-pyhd8ed1ab_0.tar.bz2 - version: 2.6.0 + url: https://conda.anaconda.org/conda-forge/noarch/pyjwt-2.7.0-pyhd8ed1ab_0.conda + version: 2.7.0 - category: main dependencies: python: '>=3.3' @@ -2875,29 +2911,41 @@ package: version: 0.19.3 - category: main dependencies: - __unix: '' - python: '>=3.8' + python: '>=3.9,<3.10.0a0' + python_abi: 3.9.* *_cp39 hash: - md5: 2a7de29fb590ca14b5243c4c812c8025 - sha256: a42f826e958a8d22e65b3394f437af7332610e43ee313393d1cf143f0a2d274b + md5: d34b97a2386932b97c7cb80916a673e7 + sha256: 42d46baeab725d3c70d22a4258549e9f0f1a72b740166cd9c3b394c4369cb306 manager: conda name: pysocks optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pysocks-1.7.1-pyha2e5f31_6.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/pysocks-1.7.1-py39hf3d152e_5.tar.bz2 version: 1.7.1 - category: main dependencies: python: '>=3.6' hash: - md5: f59d49a7b464901cf714b9e7984d01a2 - sha256: 93cfc7a92099e26b0575a343da4a667b52371cc38e4dee4ee264dc041ef77bac + md5: 2590495f608a63625e165915fb4e2e34 + sha256: 0108888507014fb24573c31e4deceb61c99e63d37776dddcadd7c89b2ecae0b6 + manager: conda + name: python-tzdata + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/python-tzdata-2023.3-pyhd8ed1ab_0.conda + version: '2023.3' +- category: main + dependencies: + python: '>=3.6' + hash: + md5: d3076b483092a435832603243567bc31 + sha256: e4999484f21763ca4b8f92c95b22cb6d1edc1b61d0a2bb073ee2bd11f39401b9 manager: conda name: pytz optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pytz-2022.7.1-pyhd8ed1ab_0.conda - version: 2022.7.1 + url: https://conda.anaconda.org/conda-forge/noarch/pytz-2023.3-pyhd8ed1ab_0.conda + version: '2023.3' - category: main dependencies: __unix: '' @@ -2959,14 +3007,14 @@ package: dependencies: python: '>=3.7' hash: - md5: e18ed61c37145bb9b48d1d98801960f7 - sha256: a5c48b1fc7c89c5c937475e9434a63af7ce2e591f8e51afd56e3b2e232a9989d + md5: 3b68bc43ec6baa48f7354a446267eefe + sha256: 3ac44771fce01f19218bcdf3992e24984748048db69889a9df65abcc6a10e29b manager: conda name: setuptools optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/setuptools-67.6.0-pyhd8ed1ab_0.conda - version: 67.6.0 + url: https://conda.anaconda.org/conda-forge/noarch/setuptools-67.7.2-pyhd8ed1ab_0.conda + version: 67.7.2 - category: main dependencies: python: '' @@ -3099,6 +3147,18 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/tomli-2.0.1-pyhd8ed1ab_0.tar.bz2 version: 2.0.1 +- category: main + dependencies: + python: '>=3.7' + hash: + md5: 75838e8556166263a82038b51d01d5f1 + sha256: 3002e87338a98ba501fbf53981f8267b2def2548265a3622d403d06747872ccd + manager: conda + name: tomlkit + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/tomlkit-0.11.8-pyha770c72_0.conda + version: 0.11.8 - category: main dependencies: python: '>=3.5' @@ -3117,62 +3177,50 @@ package: python: '>=3.9,<3.10.0a0' python_abi: 3.9.* *_cp39 hash: - md5: 8a7d309b08cff6386fe384aa10dd3748 - sha256: 67c3eef0531caf75a81945844288f363cd3b7b029829bd91ed0994bf6b231f34 + md5: c69c42faf110456735b6147190d5f12f + sha256: ef9b63cb061b8dcc2eb4b2f11440f91ca9330d09aa6914325b5160d22d968e1c manager: conda name: tornado optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/tornado-6.2-py39hb9d737c_1.tar.bz2 - version: '6.2' + url: https://conda.anaconda.org/conda-forge/linux-64/tornado-6.3-py39h72bdee0_0.conda + version: '6.3' - category: main dependencies: python: '>=3.6' hash: - md5: a4d6202101f04b76d545530728e696bf - sha256: 8e490e1d390be0ab59b538199b4cedec027c68ebaa3add554a6316a79d5a1dbe + md5: 2010a97e7298197221abc6295790ff62 + sha256: 5fb56cd0652e7cffc1141c66b09644f1dde588ef6dddcb47849a62d7b0186846 manager: conda name: types-pytz optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/types-pytz-2022.7.1.2-pyhd8ed1ab_0.conda - version: 2022.7.1.2 + url: https://conda.anaconda.org/conda-forge/noarch/types-pytz-2023.3.0.0-pyhd8ed1ab_0.conda + version: 2023.3.0.0 - category: main dependencies: python: '>=3.6' hash: - md5: d398b385822d9425fb21c6c8f89dbc9e - sha256: 32233b8d558c118b9d856c6b7e52499c36b9f867bbf76b5c8b7edfb7655230cf + md5: 0c0c5edec27d8284bf75023737f74823 + sha256: 10290d04934693214ea9a3caaefac35c3fdfc72094ffa8b0f063141bef469bbe manager: conda name: types-pyyaml optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/types-pyyaml-6.0.12.8-pyhd8ed1ab_0.conda - version: 6.0.12.8 + url: https://conda.anaconda.org/conda-forge/noarch/types-pyyaml-6.0.12.9-pyhd8ed1ab_0.conda + version: 6.0.12.9 - category: main dependencies: python: '>=3.6' hash: - md5: 617bb6391b4b676f9b062aff31ef978d - sha256: 17f157579b6f0e9c2ef56e3d9c74eef625717865f8503101317cedc69f059b46 + md5: 8b7a7a28f8a274b98f0387c13c56c94c + sha256: e07d313a9c7aa2dfe425ca5a3bdc65cd015a8819cda8e576edb3b3a47535da1a manager: conda name: types-urllib3 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/types-urllib3-1.26.25.8-pyhd8ed1ab_0.conda - version: 1.26.25.8 -- category: main - dependencies: - python: '>=3' - hash: - md5: e6573ac68718f17b9d4f5c8eda3190f2 - sha256: ec1cfe0b7dc55a22223562cad799e0b16d122dab611c9923b6068d27a784ba2f - manager: conda - name: typing - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/typing-3.10.0.0-pyhd8ed1ab_0.tar.bz2 - version: 3.10.0.0 + url: https://conda.anaconda.org/conda-forge/noarch/types-urllib3-1.26.25.12-pyhd8ed1ab_0.conda + version: 1.26.25.12 - category: main dependencies: python: '>=3.7' @@ -3205,36 +3253,19 @@ package: gxx_impl_linux-64: '' libgcc-ng: '>=12' libstdcxx-ng: '>=12' - libzlib: '>=1.2.12,<1.3.0a0' + libzlib: '>=1.2.13,<1.3.0a0' make: '' perl: '' + python: '' hash: - md5: 41af6df1758bae89161daf268566384e - sha256: e2f2302d69c0d6928d95a1c699b5ef0b14e0243e78495734962c78136d2e6b9f + md5: efb0e7909f1a41159856e688e216bd26 + sha256: c24f5fc704ee3c0737456e7a4b8f75114b25a51812c6f801a22ed43652e0b211 manager: conda name: verilator optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/verilator-4.226-he0ac6c6_1.tar.bz2 - version: '4.226' -- category: main - dependencies: - gettext: '>=0.21.1,<1.0a0' - libgcc-ng: '>=12' - libstdcxx-ng: '>=12' - ncurses: '>=6.3,<7.0a0' - perl: '>=5.32.1,<5.33.0a0 *_perl5' - python: '>=3.9,<3.10.0a0' - python_abi: 3.9.* *_cp39 - hash: - md5: 8f23fe6252f0db61a467fc68235a6c6c - sha256: 1ff7b1aa32d188658e797ba09579afc9712ef00a5b10700ebc10d57155dcd299 - manager: conda - name: vim - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/vim-9.0.0814-py39pl5321h20e6244_0.tar.bz2 - version: 9.0.0814 + url: https://conda.anaconda.org/conda-forge/linux-64/verilator-5.008-h514fc35_1.conda + version: '5.008' - category: main dependencies: python: '' @@ -3259,18 +3290,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/websocket-client-1.5.1-pyhd8ed1ab_0.conda version: 1.5.1 -- category: main - dependencies: - python: '>=3.7' - hash: - md5: 6dfc61103f2c33a6c875b93d82875c10 - sha256: 3e08e7a72a01fa53e4d2e2dedde32b3300dc9d12c91d7b5248d458ecfa0bd439 - manager: conda - name: werkzeug - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/werkzeug-2.1.2-pyhd8ed1ab_1.tar.bz2 - version: 2.1.2 - category: main dependencies: python: '>=3.7' @@ -3351,6 +3370,23 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libxrender-0.9.10-h7f98852_1003.tar.bz2 version: 0.9.10 +- category: main + dependencies: + libgcc-ng: '>=9.3.0' + xorg-kbproto: '' + xorg-libice: 1.0.* + xorg-libsm: 1.2.* + xorg-libx11: '>=1.7.0,<2.0a0' + xorg-xproto: '' + hash: + md5: 60d6eec5273f1c9af096c10c268912e3 + sha256: 25bfc4d86df3498b88aac2f02ecf65e739bf99a687805c31a635df6f2e60a163 + manager: conda + name: xorg-libxt + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libxt-1.2.1-h7f98852_2.tar.bz2 + version: 1.2.1 - category: main dependencies: python: '>=3.7' @@ -3363,19 +3399,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/zipp-3.15.0-pyhd8ed1ab_0.conda version: 3.15.0 -- category: main - dependencies: - python: '>=3.6' - typing_extensions: '>=4.0' - hash: - md5: 59c40397276a286241c65faec5e1be3c - sha256: be2dbd6710438fa48b83bf06841091227276ae545d145dfe5cb5149c6484e951 - manager: conda - name: aioitertools - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/aioitertools-0.11.0-pyhd8ed1ab_0.tar.bz2 - version: 0.11.0 - category: main dependencies: frozenlist: '>=1.1.0' @@ -3404,30 +3427,30 @@ package: version: 2.12.1 - category: main dependencies: - fontconfig: '>=2.13.96,<3.0a0' + fontconfig: '>=2.14.2,<3.0a0' fonts-conda-ecosystem: '' freetype: '>=2.12.1,<3.0a0' - icu: '>=70.1,<71.0a0' + icu: '>=72.1,<73.0a0' libgcc-ng: '>=12' - libglib: '>=2.72.1,<3.0a0' - libpng: '>=1.6.38,<1.7.0a0' + libglib: '>=2.74.1,<3.0a0' + libpng: '>=1.6.39,<1.7.0a0' libxcb: '>=1.13,<1.14.0a0' - libzlib: '>=1.2.12,<1.3.0a0' + libzlib: '>=1.2.13,<1.3.0a0' pixman: '>=0.40.0,<1.0a0' xorg-libice: '' xorg-libsm: '' - xorg-libx11: '' - xorg-libxext: '' + xorg-libx11: '>=1.8.4,<2.0a0' + xorg-libxext: '>=1.3.4,<2.0a0' xorg-libxrender: '' - zlib: '>=1.2.12,<1.3.0a0' + zlib: '' hash: - md5: d1a88f3ed5b52e1024b80d4bcd26a7a0 - sha256: f062cf56e6e50d3ad4b425ebb3765ca9138c6ebc52e6a42d1377de8bc8d954f6 + md5: 0c944213e40c9e4aa32292776b9c6903 + sha256: 0be3064cb30e3e69a47370abae85b2780cd81fbca00cbd17076d40c0f6302fdb manager: conda name: cairo optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/cairo-1.16.0-ha61ee94_1014.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/cairo-1.16.0-h35add3b_1015.conda version: 1.16.0 - category: main dependencies: @@ -3447,20 +3470,19 @@ package: version: 1.15.1 - category: main dependencies: - libclang-cpp15: '>=15.0.7,<15.1.0a0' + libclang-cpp16: '>=16.0.3,<16.1.0a0' libgcc-ng: '>=12' - libllvm15: '>=15.0.7,<15.1.0a0' + libllvm16: '>=16.0.3,<16.1.0a0' libstdcxx-ng: '>=12' - libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: d2fcc7c0381194ca6fcb38a6d06255b8 - sha256: eee53b98b40099c9289a732f6c915f9c80714d8a7a8a977f921c0782c6f5200f + md5: 14a18f87f492a905cee3d833eae4e86b + sha256: 0896316dbdcd3dca118c61127b2d79cc0c0bdb08f869cff9f35fe2c5a4673555 manager: conda - name: clang-format-15 + name: clang-format-16 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/clang-format-15-15.0.7-default_had23c3d_1.conda - version: 15.0.7 + url: https://conda.anaconda.org/conda-forge/linux-64/clang-format-16-16.0.3-default_h83cc7fd_0.conda + version: 16.0.3 - category: main dependencies: click: '' @@ -3491,8 +3513,9 @@ package: - category: main dependencies: bzip2: '>=1.0.8,<2.0a0' - expat: '>=2.5.0,<3.0a0' - libcurl: '>=7.88.1,<8.0a0' + expat: '' + libcurl: '>=7.88.1,<9.0a0' + libexpat: '>=2.5.0,<3.0a0' libgcc-ng: '>=12' libstdcxx-ng: '>=12' libuv: '' @@ -3503,14 +3526,14 @@ package: zlib: '' zstd: '>=1.5.2,<1.6.0a0' hash: - md5: 02142080aee43c8ef90db543ffbc13dd - sha256: cbd17c0375a021b7de854e0841f3f1b28b1359bc52bdc0ba5aabaee0f65a0b7d + md5: 6edec767268ad8451d27bb65f38c7ea4 + sha256: 3bb9d7c35d5297d85516769eb0517c83f7fc2ed7ab944a8c028871bb375bed51 manager: conda name: cmake optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/cmake-3.26.0-h077f3f9_0.conda - version: 3.26.0 + url: https://conda.anaconda.org/conda-forge/linux-64/cmake-3.26.3-h077f3f9_0.conda + version: 3.26.3 - category: main dependencies: libgcc-ng: '>=12' @@ -3563,7 +3586,7 @@ package: dependencies: bzip2: '>=1.0.8,<2.0a0' libarchive: '>=3.5.2,<3.6.0a0' - libcurl: '>=7.82.0,<8.0a0' + libcurl: '>=7.82.0,<9.0a0' libgcc-ng: '>=10.3.0' libmicrohttpd: '>=0.9.75,<0.10.0a0' libstdcxx-ng: '>=10.3.0' @@ -3589,14 +3612,14 @@ package: python_abi: 3.9.* *_cp39 unicodedata2: '>=14.0.0' hash: - md5: f87853cd6f76c4b8014b41fa522e5bda - sha256: 2c9ca5aba1d6d038b60f77b73e533e81feee882cd4f22e99bdaa77fd7bfcc7cc + md5: 9232b3b2cc83a304c8210a092e8ba4a5 + sha256: 08b6feeebcdd6ccb61cdb794eec806be7765dc4d601d4ec051aea721fa439aa4 manager: conda name: fonttools optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/fonttools-4.39.2-py39h72bdee0_0.conda - version: 4.39.2 + url: https://conda.anaconda.org/conda-forge/linux-64/fonttools-4.39.3-py39h72bdee0_0.conda + version: 4.39.3 - category: main dependencies: python: '>=3.4' @@ -3642,14 +3665,14 @@ package: python: '>=3.8' zipp: '>=0.5' hash: - md5: 30b3127c385ca2ed5ef87f3d53d466bc - sha256: 4fe127138487a2aa171862407605f0cd601d005f85e0eee7f38c770b407e4145 + md5: f91a5d5175fb7ff2a91952ec7da59cb9 + sha256: 33d49065756a73fbb92277c756fa00a41891408528eb90ae05ff3367a401ae6e manager: conda name: importlib-metadata optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-6.1.0-pyha770c72_0.conda - version: 6.1.0 + url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-6.6.0-pyha770c72_0.conda + version: 6.6.0 - category: main dependencies: python: '>=3.7' @@ -3715,45 +3738,29 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/junit-xml-1.9-pyh9f0ad1d_0.tar.bz2 version: '1.9' -- category: main - dependencies: - libclang13: 15.0.7 default_h3e3d535_1 - libgcc-ng: '>=12' - libllvm15: '>=15.0.7,<15.1.0a0' - libstdcxx-ng: '>=12' - libzlib: '>=1.2.13,<1.3.0a0' - hash: - md5: 36c65ed73b7c92589bd9562ef8a6023d - sha256: eba3ed760c72c992a04d86455556ecb90c0e1e3688defcac44b28a848d71651c - manager: conda - name: libclang - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libclang-15.0.7-default_had23c3d_1.conda - version: 15.0.7 - category: main dependencies: expat: '>=2.5.0,<3.0a0' - fontconfig: '>=2.14.1,<3.0a0' + fontconfig: '>=2.14.2,<3.0a0' fonts-conda-ecosystem: '' freetype: '>=2.12.1,<3.0a0' - icu: '>=70.1,<71.0a0' - jpeg: '>=9e,<10a' + icu: '>=72.1,<73.0a0' libgcc-ng: '>=12' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libpng: '>=1.6.39,<1.7.0a0' libtiff: '>=4.5.0,<4.6.0a0' libwebp: '' - libwebp-base: '>=1.2.4,<2.0a0' + libwebp-base: '>=1.3.0,<2.0a0' libzlib: '>=1.2.13,<1.3.0a0' zlib: '' hash: - md5: 82ef57611ace65b59db35a9687264572 - sha256: 6674781023188deeda7752e5dc429a54fd1639c9d61cbb25296cbbb55367884a + md5: ef06bee47510a7f5db3c2297a51d6ce2 + sha256: 6335db21afc72f86cf4ee0298acde3af950087db2b24df3d28a81c7d24574244 manager: conda name: libgd optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libgd-2.3.3-h5aea950_4.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libgd-2.3.3-hfa28ad5_6.conda version: 2.3.3 - category: main dependencies: @@ -3780,14 +3787,14 @@ package: tomli: '>=1.1.0' typing_extensions: '>=3.10' hash: - md5: e25a18721970f7bb80a0d602ef3c72ad - sha256: 1ff6a68e7c511e2bb70b51466134706e33a322a3ef2544c7adc3524bd51624f1 + md5: 340cfe1633c018c5abf0099d7c307ab4 + sha256: 682fd2b43cf9bb66813d44b70535684670c33ca4a44e6c0e76540c496cb632c5 manager: conda name: mypy optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/mypy-1.1.1-py39h72bdee0_0.conda - version: 1.1.1 + url: https://conda.anaconda.org/conda-forge/linux-64/mypy-1.2.0-py39h72bdee0_0.conda + version: 1.2.0 - category: main dependencies: python: 2.7|>=3.7 @@ -3804,11 +3811,11 @@ package: - category: main dependencies: freetype: '>=2.12.1,<3.0a0' - jpeg: '>=9e,<10a' - lcms2: '>=2.14,<3.0a0' + lcms2: '>=2.15,<3.0a0' libgcc-ng: '>=12' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libtiff: '>=4.5.0,<4.6.0a0' - libwebp-base: '>=1.2.4,<2.0a0' + libwebp-base: '>=1.3.0,<2.0a0' libxcb: '>=1.13,<1.14.0a0' libzlib: '>=1.2.13,<1.3.0a0' openjpeg: '>=2.5.0,<3.0a0' @@ -3816,60 +3823,28 @@ package: python_abi: 3.9.* *_cp39 tk: '>=8.6.12,<8.7.0a0' hash: - md5: d2f79132b9c8e416058a4cd84ef27b3d - sha256: 77348588ae7cc8034b63e8a71b6695ba22761e1c531678e724cf06a12be3d1e2 + md5: 7882f5dfc152b021e5cb98e2d01507f8 + sha256: 82a2926a9a39e72291e134778fb3da7371efcb67437897fd474aaad03d6db609 manager: conda name: pillow optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/pillow-9.4.0-py39h2320bf1_1.conda - version: 9.4.0 + url: https://conda.anaconda.org/conda-forge/linux-64/pillow-9.5.0-py39h7207d5c_0.conda + version: 9.5.0 - category: main dependencies: python: '>=3.7' setuptools: '' wheel: '' hash: - md5: 8025ca83b8ba5430b640b83917c2a6f7 - sha256: e1698cbf4964cd60a2885c0edbc654133cd0db5ac4cb568412250e577dbc42ad + md5: 7288da0d36821349cf1126e8670292df + sha256: 4fe1f47f6eac5b2635a622b6f985640bf835843c1d8d7ccbbae0f7d27cadec92 manager: conda name: pip optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pip-23.0.1-pyhd8ed1ab_0.conda - version: 23.0.1 -- category: main - dependencies: - python: '>=3.6' - setuptools: '' - hash: - md5: c78cd16b11cd6a295484bd6c8f24bea1 - sha256: e8710e24f60b6a97289468f47914e53610101755088bc237621cc1980edbfcd9 - manager: conda - name: pygments - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pygments-2.14.0-pyhd8ed1ab_0.conda - version: 2.14.0 -- category: main - dependencies: - attrs: '>=19.2.0' - colorama: '' - exceptiongroup: '' - iniconfig: '' - packaging: '' - pluggy: '>=0.12,<2.0' - python: '>=3.8' - tomli: '>=1.0.0' - hash: - md5: 60958b19354e0ec295b43f6ab5cfab86 - sha256: d074ef1e2ffc3334927c281e4b79aebfa8eefd2d1588c3830a45ba4bce3e6ea9 - manager: conda - name: pytest - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pytest-7.2.2-pyhd8ed1ab_0.conda - version: 7.2.2 + url: https://conda.anaconda.org/conda-forge/noarch/pip-23.1.2-pyhd8ed1ab_0.conda + version: 23.1.2 - category: main dependencies: python: '>=3.6' @@ -3923,27 +3898,14 @@ package: ruamel.yaml.clib: '>=0.1.2' setuptools: '' hash: - md5: b64be7a2bbc2acc61c1a2161512387c2 - sha256: 1dd205a1ab9897482804b5ef3f2a1cea44f01e831d1bcff439d1e0894ab0e4a9 + md5: 522b3d9f069af18d947bd43b57817ba0 + sha256: f1deff6ee893729e4c1b1005a60fea55907bbdbca2d3c88263ac65ff3ea25c55 manager: conda name: ruamel.yaml optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml-0.17.21-py39h72bdee0_3.conda - version: 0.17.21 -- category: main - dependencies: - python: '>=3.6' - typing: '>=3.6,<4.0' - hash: - md5: 471bf9e605820b59988e830382b8d654 - sha256: e8b3bc2203266636740ce10536ef951c52b53b43bfed3b938117547efc47e374 - manager: conda - name: tomlkit - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/tomlkit-0.11.6-pyha770c72_0.tar.bz2 - version: 0.11.6 + url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml-0.17.25-py39hd1e30aa_0.conda + version: 0.17.25 - category: main dependencies: colorama: '' @@ -3962,14 +3924,14 @@ package: python: '>=3.6' types-urllib3: <1.27 hash: - md5: 35221b6d2f75276b786fb53fac5c4c35 - sha256: 54b0949b6fcdbdc36474dd3403a926b55331de6c1ea543c1d87f444f7fa8702a + md5: 1ab2e9a47f24fac257f88956828f1956 + sha256: 19d2affb4d3fab4d1d60eb3748b2d80b9ff2983c9b196e74aae7a0dc03fe74d8 manager: conda name: types-requests optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/types-requests-2.28.11.15-pyhd8ed1ab_0.conda - version: 2.28.11.15 + url: https://conda.anaconda.org/conda-forge/noarch/types-requests-2.30.0.0-pyhd8ed1ab_0.conda + version: 2.30.0.0 - category: main dependencies: typing_extensions: 4.5.0 pyha770c72_0 @@ -3982,6 +3944,39 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/typing-extensions-4.5.0-hd8ed1ab_0.conda version: 4.5.0 +- category: main + dependencies: + gettext: '>=0.21.1,<1.0a0' + libgcc-ng: '>=12' + libstdcxx-ng: '>=12' + ncurses: '>=6.3,<7.0a0' + perl: '>=5.32.1,<5.33.0a0 *_perl5' + python: '>=3.9,<3.10.0a0' + python_abi: 3.9.* *_cp39 + xorg-libx11: '>=1.8.4,<2.0a0' + xorg-libxt: '' + hash: + md5: da1ade321e40a910685104d9120c8d5c + sha256: a8d77a8e2f416a94f74a4acfe3d92b7f6685a4aec6f5e700dbd209925fe859e7 + manager: conda + name: vim + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/vim-9.0.1425-py39pl5321hb4338c2_0.conda + version: 9.0.1425 +- category: main + dependencies: + markupsafe: '>=2.1.1' + python: '>=3.8' + hash: + md5: 23ddbe41ab0115bc0bfb75dcbf5de7cf + sha256: 2df1970270839b36e13a4ba7e4b393cfa95aa1d7438909aa8c3db14170ea207c + manager: conda + name: werkzeug + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/werkzeug-2.3.4-pyhd8ed1ab_0.conda + version: 2.3.4 - category: main dependencies: libgcc-ng: '>=9.3.0' @@ -4006,14 +4001,14 @@ package: python: '>=3.9,<3.10.0a0' python_abi: 3.9.* *_cp39 hash: - md5: fc75e67104cc1bdd6aa2a3b970b19f7f - sha256: 0fb71fdb26db6e49ad92a09ffd26c99145dc02eeb8e15e48fde4437b6237ea58 + md5: 38cd0735b2002777c765fa5b7f4217b5 + sha256: d9e48f222156d21817588a853efa63e84d5f2c5dedfb00df73a53857ef12ec26 manager: conda name: yarl optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/yarl-1.8.2-py39hb9d737c_0.conda - version: 1.8.2 + url: https://conda.anaconda.org/conda-forge/linux-64/yarl-1.9.1-py39hd1e30aa_0.conda + version: 1.9.1 - category: main dependencies: python: '>=3.6' @@ -4061,37 +4056,36 @@ package: version: 0.7.0 - category: main dependencies: - clang-format-15: 15.0.7 default_had23c3d_1 - libclang-cpp15: '>=15.0.7,<15.1.0a0' + clang-format-16: 16.0.3 default_h83cc7fd_0 + libclang-cpp16: '>=16.0.3,<16.1.0a0' libgcc-ng: '>=12' - libllvm15: '>=15.0.7,<15.1.0a0' + libllvm16: '>=16.0.3,<16.1.0a0' libstdcxx-ng: '>=12' - libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: 841d93c086f15b68916b3455711c2638 - sha256: 517c759576600decafd005b14f3df9660b525fdb85645a0c588ea979b62bdc5e + md5: a1f13606e670bdaaee724536218f5c40 + sha256: 5eb61124b6f96015aee46217f081953cb4efee9f9d39ac7c98e76d734f384693 manager: conda name: clang-format optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/clang-format-15.0.7-default_had23c3d_1.conda - version: 15.0.7 + url: https://conda.anaconda.org/conda-forge/linux-64/clang-format-16.0.3-default_h83cc7fd_0.conda + version: 16.0.3 - category: main dependencies: cffi: '>=1.12' libgcc-ng: '>=12' - openssl: '>=3.0.8,<4.0a0' + openssl: '>=3.1.0,<4.0a0' python: '>=3.9,<3.10.0a0' python_abi: 3.9.* *_cp39 hash: - md5: c492b565817a019f025c7d17b57ef479 - sha256: 66ae341f51f6832de23f0047ea9e23fdf2f7e5fcd72faa814b17a7497a096e07 + md5: ad5cb1777ae6847c4d60199fa90a674c + sha256: 379f168a099aa47dbe38261fbebca0dd39e422ac0666468dc81b5e32c326503e manager: conda name: cryptography optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/cryptography-39.0.2-py39h079d5ae_0.conda - version: 39.0.2 + url: https://conda.anaconda.org/conda-forge/linux-64/cryptography-40.0.2-py39h079d5ae_0.conda + version: 40.0.2 - category: main dependencies: cloudpickle: '' @@ -4108,41 +4102,42 @@ package: version: 0.36.0 - category: main dependencies: - click: '>=8.0' + blinker: '>=1.6.2' + click: '>=8.1.3' importlib-metadata: '>=3.6.0' - itsdangerous: '>=2.0' - jinja2: '>=3.0' - python: '>=3.7' - werkzeug: '>=2.0' + itsdangerous: '>=2.1.2' + jinja2: '>=3.1.2' + python: '>=3.8' + werkzeug: '>=2.3.3' hash: - md5: 4b95b1c750d6d737905cdb447f097b9c - sha256: de8f2eb0b86e28b672839ae4ad0032eda30e09fee28a19b79159b35673f25a42 + md5: 816d75d4c0f2e41b5765d17498c57a2e + sha256: f93246be286f2d0f93e85c4f08f9ce48f3eed875a79225e2ea119e70c0237421 manager: conda name: flask optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/flask-2.1.3-pyhd8ed1ab_0.tar.bz2 - version: 2.1.3 + url: https://conda.anaconda.org/conda-forge/noarch/flask-2.3.2-pyhd8ed1ab_0.conda + version: 2.3.2 - category: main dependencies: curl: '' - expat: '>=2.5.0,<3.0a0' gettext: '' + libexpat: '>=2.5.0,<3.0a0' libgcc-ng: '>=12' libiconv: '>=1.17,<2.0a0' libzlib: '>=1.2.13,<1.3.0a0' - openssl: '>=3.0.8,<4.0a0' + openssl: '>=3.1.0,<4.0a0' pcre2: '>=10.40,<10.41.0a0' perl: 5.* hash: - md5: 70fd89375d9b5ca90c15dcf3662b1b42 - sha256: fba1e93848c20e29d205726142fb37ad7e2be785699f98aac348524080354f6d + md5: 0cb5ff348eb4c201b3b920eff851675d + sha256: 528c9fdaf799b38611276d6f676da6018da2aaf93fb5b0328c00923909e99432 manager: conda name: git optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/git-2.40.0-pl5321h693f4a3_0.conda - version: 2.40.0 + url: https://conda.anaconda.org/conda-forge/linux-64/git-2.40.1-pl5321h86e50cf_0.conda + version: 2.40.1 - category: main dependencies: gitdb: '>=4.0.1,<5' @@ -4162,18 +4157,18 @@ package: cairo: '>=1.16.0,<2.0a0' freetype: '>=2.12.1,<3.0a0' graphite2: '' - icu: '>=70.1,<71.0a0' + icu: '>=72.1,<73.0a0' libgcc-ng: '>=12' libglib: '>=2.74.1,<3.0a0' libstdcxx-ng: '>=12' hash: - md5: 448fe40d2fed88ccf4d9ded37cbb2b38 - sha256: f300fcb390253d6d63346ee71e56f82bc830783d1682ac933fe9ac86f39da942 + md5: 73d2c2d25fdcec40c24929bab9f44831 + sha256: d4bf8a3e23478efefe39ac2d965f44b55cee4058277f2ad7478384e7973fc97f manager: conda name: harfbuzz optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/harfbuzz-6.0.0-h8e241bc_0.conda + url: https://conda.anaconda.org/conda-forge/linux-64/harfbuzz-6.0.0-h3ff4399_1.conda version: 6.0.0 - category: main dependencies: @@ -4190,16 +4185,16 @@ package: version: 5.12.0 - category: main dependencies: - importlib-metadata: '>=6.1.0,<6.1.1.0a0' + importlib-metadata: '>=6.6.0,<6.6.1.0a0' hash: - md5: 90bab1d97fdb6bb40c8e00207bf222dc - sha256: 80a10ad1bacf5bb85d497fd3e5629f5805b6e90ad8c8b923daa3e36729e7429a + md5: 3cbc9615f10a3d471532b83e4250b971 + sha256: 5de35d3c019d8a36e0a0deeb04a62689837bd68234a0a73a3355b860b442eca4 manager: conda name: importlib_metadata optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/importlib_metadata-6.1.0-hd8ed1ab_0.conda - version: 6.1.0 + url: https://conda.anaconda.org/conda-forge/noarch/importlib_metadata-6.6.0-hd8ed1ab_0.conda + version: 6.6.0 - category: main dependencies: attrs: '>=17.4.0' @@ -4234,20 +4229,21 @@ package: dependencies: libgcc-ng: '>=12' libstdcxx-ng: '>=12' - numpy: '>=1.20.3,<2.0a0' + numpy: '>=1.21.6,<2.0a0' python: '>=3.9,<3.10.0a0' python-dateutil: '>=2.8.1' + python-tzdata: '>=2022a' python_abi: 3.9.* *_cp39 pytz: '>=2020.1' hash: - md5: 3ea96adbbc2a66fa45178102a9cfbecc - sha256: a71fb9584f2b58e260fa565d5f27af763f21ed2afeede79e7d848620691bd765 + md5: 85bc4d45cd98f84af0c00435fff23f67 + sha256: 49c114195ed92a7e36244259f747c87a42382629548ce40e6d9ea5b3e5570840 manager: conda name: pandas optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/pandas-1.5.3-py39h2ad29b5_0.conda - version: 1.5.3 + url: https://conda.anaconda.org/conda-forge/linux-64/pandas-2.0.1-py39h40cae4c_1.conda + version: 2.0.1 - category: main dependencies: pip: '' @@ -4264,16 +4260,16 @@ package: - category: main dependencies: python: '>=3.7' - typing-extensions: '>=4.4' + typing-extensions: '>=4.5' hash: - md5: 1d1a27f637808c76dd83e3f469aa6f7e - sha256: 5875ef7f4b079fe080c10287b13843860bc69a42e457729a8c5dc32cb3563e92 + md5: 6c36f1c42dd0069b7f23acc74f19be46 + sha256: e6d247b9a645ac6a2e4909cbe9cfad5cf9ba1a2f4352fee7aac3acb640371a54 manager: conda name: platformdirs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/platformdirs-3.1.1-pyhd8ed1ab_0.conda - version: 3.1.1 + url: https://conda.anaconda.org/conda-forge/noarch/platformdirs-3.5.0-pyhd8ed1ab_0.conda + version: 3.5.0 - category: main dependencies: libgcc-ng: '>=12' @@ -4281,14 +4277,14 @@ package: python_abi: 3.9.* *_cp39 typing-extensions: '>=4.2.0' hash: - md5: f9528d54782423f164ae187be76ead28 - sha256: b18342ce213c8f4482eeca7c34944dd904e62e063a5783089203d3fa907b9ab0 + md5: d189943289498d75a39922d5b25bd77e + sha256: 401a02c0fcecd4ad2eaafa8f69eabef4873bec09963c277c0473596f8c3cae46 manager: conda name: pydantic optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/pydantic-1.10.6-py39h72bdee0_0.conda - version: 1.10.6 + url: https://conda.anaconda.org/conda-forge/linux-64/pydantic-1.10.7-py39h72bdee0_0.conda + version: 1.10.7 - category: main dependencies: cffi: '>=1.4.1' @@ -4308,43 +4304,36 @@ package: version: 1.5.0 - category: main dependencies: - pytest: '>=3.6.0' - python: '' + colorama: '' + exceptiongroup: '' + importlib-metadata: '>=0.12' + iniconfig: '' + packaging: '' + pluggy: '>=0.12,<2.0' + python: '>=3.8' + tomli: '>=1.0.0' hash: - md5: b6764e23dece9f9cda0469af044fafeb - sha256: bdb25a7daf3efb7255b1a19d7b5d41d7d4d96bc647b8e5f7407ec4dd9e384257 + md5: 547c7de697ec99b494a28ddde185b5a4 + sha256: 42f89db577266b9dc195d09189b92f3af3354fb50c98b1f996c580322dffa8b5 manager: conda - name: pytest-dependency + name: pytest optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pytest-dependency-0.5.1-pyh9f0ad1d_0.tar.bz2 - version: 0.5.1 -- category: main - dependencies: - pytest: '>=5.0' - python: '>=3.7' - hash: - md5: db93caa9fe182f0cd20291aeb22f57ac - sha256: 87bb8edc9976403237a0e6c3bd7b2224c346c95e4c7345971f411aef21593450 - manager: conda - name: pytest-mock - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pytest-mock-3.10.0-pyhd8ed1ab_0.tar.bz2 - version: 3.10.0 + url: https://conda.anaconda.org/conda-forge/noarch/pytest-7.3.1-pyhd8ed1ab_0.conda + version: 7.3.1 - category: main dependencies: pip: '' python: '>=3.7,<4.0' hash: - md5: 25923bf9620c56f8bc0d4923d870edd8 - sha256: 3f8be46ba1cbd8533d25eba1a5b32062bb9231b16e308bbbc92b5e32177cbdad + md5: 8462b4f53fa7d7dc057a26d589ec71de + sha256: dc2928817ff89e3628f82f3cedd4369c84d7079d04493b33dc67e4288d1de35d manager: conda name: types-awscrt optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/types-awscrt-0.16.13-pyhd8ed1ab_0.conda - version: 0.16.13 + url: https://conda.anaconda.org/conda-forge/noarch/types-awscrt-0.16.17-pyhd8ed1ab_0.conda + version: 0.16.17 - category: main dependencies: cffi: '' @@ -4421,32 +4410,31 @@ package: types-awscrt: '' typing_extensions: '' hash: - md5: 96971bc5cc944a1743fdde0634e55480 - sha256: fee2b0596dd34a70081d745e06f9302dd06fb56dd366e51a302f93c9764126d9 + md5: 01961f718d29cabd188e863a61d8fd81 + sha256: 1fc8f40eb33d7e38590d88d847fb39329628c31269c8a2e5aaab7d51cc5b501f manager: conda name: botocore-stubs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.29.94-pyhd8ed1ab_0.conda - version: 1.29.94 + url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.29.129-pyhd8ed1ab_0.conda + version: 1.29.129 - category: main dependencies: - clang-format: 15.0.7 default_had23c3d_1 - libclang: '>=15.0.7,<15.1.0a0' - libclang-cpp15: '>=15.0.7,<15.1.0a0' + clang-format: 16.0.3 default_h83cc7fd_0 + libclang-cpp16: '>=16.0.3,<16.1.0a0' + libclang13: '>=16.0.3' libgcc-ng: '>=12' - libllvm15: '>=15.0.7,<15.1.0a0' + libllvm16: '>=16.0.3,<16.1.0a0' libstdcxx-ng: '>=12' - libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: c23e2b0154fb2eb92442fa8ecbcf571c - sha256: d9931c1ce5907073de0269666881309cc896267723f38ef269101bd211e49062 + md5: ceedc73b354682b0d63d61d654ebcd33 + sha256: b5ea9bef3e3316c34bfbde0a3a50cb53a2bf2db89221c9b145d37fc1e5c89576 manager: conda name: clang-tools optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/clang-tools-15.0.7-default_had23c3d_1.conda - version: 15.0.7 + url: https://conda.anaconda.org/conda-forge/linux-64/clang-tools-16.0.3-default_h83cc7fd_0.conda + version: 16.0.3 - category: main dependencies: python: '>=3.7' @@ -4479,14 +4467,14 @@ package: python: '>=3.6' ukkonen: '' hash: - md5: b5ada314668cded097e08fea86262317 - sha256: 88bcba64d462867b5759e29784cf24685e1e49fffea75452b94d438d6bd9587c + md5: a4085ab0562d5081a9333435837b538a + sha256: 4027103c59220a68b41aed056d2ce89d46e4971033d259293ca07198a8a81fdc manager: conda name: identify optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/identify-2.5.21-pyhd8ed1ab_0.conda - version: 2.5.21 + url: https://conda.anaconda.org/conda-forge/noarch/identify-2.5.24-pyhd8ed1ab_0.conda + version: 2.5.24 - category: main dependencies: importlib_metadata: '' @@ -4558,31 +4546,31 @@ package: - category: main dependencies: alsa-lib: '>=1.2.8,<1.2.9.0a0' - fontconfig: '>=2.14.1,<3.0a0' + fontconfig: '>=2.14.2,<3.0a0' fonts-conda-ecosystem: '' freetype: '>=2.12.1,<3.0a0' giflib: '>=5.2.1,<5.3.0a0' harfbuzz: '>=6.0.0,<7.0a0' - jpeg: '>=9e,<10a' - lcms2: '>=2.14,<3.0a0' + lcms2: '>=2.15,<3.0a0' libcups: '>=2.3.3,<2.4.0a0' libgcc-ng: '>=12' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libpng: '>=1.6.39,<1.7.0a0' libstdcxx-ng: '>=12' libzlib: '>=1.2.13,<1.3.0a0' - xorg-libx11: '' - xorg-libxext: '' + xorg-libx11: '>=1.8.4,<2.0a0' + xorg-libxext: '>=1.3.4,<2.0a0' xorg-libxi: '' xorg-libxrender: '' xorg-libxtst: '' hash: - md5: 71a5dfe4a375fc43497cdc6f4aedff9d - sha256: baa527e6b59572e00e68c2362e1771f7741f3f062dac7a8c6365a97f48c04413 + md5: 33527b036cd6d369be12fd772cdd49e4 + sha256: 221de13214f051654177dd331c019a889ab1bbe3b2cf30d5cf17596378740359 manager: conda name: openjdk optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/openjdk-17.0.3-h58dac75_5.conda + url: https://conda.anaconda.org/conda-forge/linux-64/openjdk-17.0.3-h4335b31_6.conda version: 17.0.3 - category: main dependencies: @@ -4621,17 +4609,43 @@ package: version: 3.1.0 - category: main dependencies: - cryptography: '>=38.0.0,<40' + cryptography: '>=38.0.0,<41' python: '>=3.6' hash: - md5: d41957700e83bbb925928764cb7f8878 - sha256: adbf8951f22bfa950b9e24394df1ef1d2b2d7dfb194d91c7f42bc11900695785 + md5: 0b34aa3ab7e7ccb1765a03dd9ed29938 + sha256: 458428cb867f70f2af2a4ed59d382291ea3eb3f10490196070a15d1d71d5432a manager: conda name: pyopenssl optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pyopenssl-23.0.0-pyhd8ed1ab_0.conda - version: 23.0.0 + url: https://conda.anaconda.org/conda-forge/noarch/pyopenssl-23.1.1-pyhd8ed1ab_0.conda + version: 23.1.1 +- category: main + dependencies: + pytest: '>=3.6.0' + python: '' + hash: + md5: b6764e23dece9f9cda0469af044fafeb + sha256: bdb25a7daf3efb7255b1a19d7b5d41d7d4d96bc647b8e5f7407ec4dd9e384257 + manager: conda + name: pytest-dependency + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/pytest-dependency-0.5.1-pyh9f0ad1d_0.tar.bz2 + version: 0.5.1 +- category: main + dependencies: + pytest: '>=5.0' + python: '>=3.7' + hash: + md5: db93caa9fe182f0cd20291aeb22f57ac + sha256: 87bb8edc9976403237a0e6c3bd7b2224c346c95e4c7345971f411aef21593450 + manager: conda + name: pytest-mock + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/pytest-mock-3.10.0-pyhd8ed1ab_0.tar.bz2 + version: 3.10.0 - category: main dependencies: cryptography: '' @@ -4695,19 +4709,18 @@ package: - category: main dependencies: distlib: <1,>=0.3.6 - filelock: <4,>=3.4.1 - importlib-metadata: '>=4.8.3' - platformdirs: <4,>=2.4 - python: '>=3.7' + filelock: <4,>=3.11 + platformdirs: <4,>=3.2 + python: '>=3.8' hash: - md5: cb9a711f7c9f3074fe522e5a34481e60 - sha256: 28540cdda9279d7daeb8f2deec6f1128869ba90742a966e488b692e8083c5349 + md5: a920e114c4c2ced2280e266da65ab5e6 + sha256: 13d667887ea08b6d1fe2eb09d2d737f9af7343735d3bfa5ffaa3f67eec8eaff7 manager: conda name: virtualenv optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.21.0-pyhd8ed1ab_0.conda - version: 20.21.0 + url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.23.0-pyhd8ed1ab_0.conda + version: 20.23.0 - category: main dependencies: conda-package-streaming: '>=0.7.0' @@ -4773,22 +4786,22 @@ package: version: 23.13.1 - category: main dependencies: - cairo: '>=1.16.0,<2.0.0a0' - gdk-pixbuf: '>=2.42.8,<3.0a0' - gettext: '>=0.19.8.1,<1.0a0' + cairo: '>=1.16.0,<2.0a0' + gdk-pixbuf: '>=2.42.10,<3.0a0' + gettext: '>=0.21.1,<1.0a0' libgcc-ng: '>=12' - libglib: '>=2.70.2,<3.0a0' - libxml2: '>=2.9.14,<2.11.0a0' - pango: '>=1.50.7,<1.51.0a0' + libglib: '>=2.76.1,<3.0a0' + libxml2: '>=2.10.4,<2.11.0a0' + pango: '>=1.50.14,<2.0a0' hash: - md5: 921e53675ed5ea352f022b79abab076a - sha256: 9b81f3854660e902a417e8194b43ed2f5d2a082227df28ba6804c68ac7c16aa0 + md5: 1ec4fab6eb4af1db9056b94265fe19cf + sha256: 6449497e50d2343c6caf73ad9c74f82341e0c22aca3d6f333869e0a069d0c472 manager: conda name: librsvg optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/librsvg-2.54.4-h7abd40a_0.tar.bz2 - version: 2.54.4 + url: https://conda.anaconda.org/conda-forge/linux-64/librsvg-2.56.0-h5cef280_0.conda + version: 2.56.0 - category: main dependencies: jsonschema: '>=3.2.0,<5.0.0' @@ -4814,14 +4827,14 @@ package: pyyaml: '>=5.1' virtualenv: '>=20.10.0' hash: - md5: 9a160452d1d88a9f10c373888f93586b - sha256: 91e104de6854e07a580603a7affb1a6e77823e9d4246486ecfd47d3978839212 + md5: c3ad8d291556452edb6c301c91f330ed + sha256: db90abf2c06c8bace41c491e2af445d06178fa8c9111e0e2ae4738866cb929ef manager: conda name: pre-commit optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.2.0-pyha770c72_0.conda - version: 3.2.0 + url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.3.1-pyha770c72_0.conda + version: 3.3.1 - category: main dependencies: __unix: '' @@ -4860,89 +4873,74 @@ package: python-dateutil: '>=2.1,<3.0.0' urllib3: '>=1.25.4,<1.27' hash: - md5: 3faabd8720a81a91566e6c01bf7bbacb - sha256: c677cba87c7027ccf264574a87130bf44f69be008315d2a840ae6cfaa61b7e44 + md5: 7da51e7dabbb80ebe3064e9343e8e818 + sha256: 1806dfc46c9f4b51ff56575025e7e5491ee630a6be5997dd1536009585da4c4c manager: conda name: botocore optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.27.59-pyhd8ed1ab_0.tar.bz2 - version: 1.27.59 + url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.29.131-pyhd8ed1ab_0.conda + version: 1.29.131 - category: main dependencies: cairo: '>=1.16.0,<2.0a0' - expat: '>=2.5.0,<3.0a0' - fontconfig: '>=2.14.1,<3.0a0' + expat: '' + fontconfig: '>=2.14.2,<3.0a0' fonts-conda-ecosystem: '' freetype: '>=2.12.1,<3.0a0' gdk-pixbuf: '>=2.42.10,<3.0a0' gtk2: '' gts: '>=0.7.6,<0.8.0a0' + libexpat: '>=2.5.0,<3.0a0' libgcc-ng: '>=12' libgd: '>=2.3.3,<2.4.0a0' - libglib: '>=2.74.1,<3.0a0' - librsvg: '>=2.54.4,<3.0a0' + libglib: '>=2.76.2,<3.0a0' + librsvg: '>=2.56.0,<3.0a0' libstdcxx-ng: '>=12' libtool: '' - libwebp-base: '>=1.2.4,<2.0a0' + libwebp-base: '>=1.3.0,<2.0a0' libzlib: '>=1.2.13,<1.3.0a0' - pango: '>=1.50.12,<2.0a0' + pango: '>=1.50.14,<2.0a0' zlib: '' hash: - md5: e7ecda996c443142a0e9c379f3b28e48 - sha256: cecaa9e6dce7f2df042768d9a794f0126565a30384fcd59879e107d760bed7f1 + md5: 597e2d0e1c6bc2e4457714ff479fe142 + sha256: 4bfb42de2d28406666ef6729169cae3f49c216c5ebd9f34afa40223755e2aaf8 manager: conda name: graphviz optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/graphviz-7.1.0-h2e5815a_0.conda - version: 7.1.0 + url: https://conda.anaconda.org/conda-forge/linux-64/graphviz-8.0.5-h28d9a01_0.conda + version: 8.0.5 - category: main dependencies: certifi: '>=2017.4.17' - charset-normalizer: '>=2,<3' + charset-normalizer: '>=2,<4' idna: '>=2.5,<4' - python: '>=3.7,<4.0' + python: '>=3.7' urllib3: '>=1.21.1,<1.27' hash: - md5: 11d178fc55199482ee48d6812ea83983 - sha256: 22c081b4cdd023a514400413f50efdf2c378f56f2a5ea9d65666aacf4696490a + md5: 5fa992d972fbccfc069161805122cb8d + sha256: bd06a6603104050fc9c4fd9bf3de7b28bbb6b9ce4b33130519d8611488213f67 manager: conda name: requests optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/requests-2.28.2-pyhd8ed1ab_0.conda - version: 2.28.2 -- category: main - dependencies: - aiohttp: '>=3.3.1' - aioitertools: '>=0.5.1' - botocore: '>=1.27.59,<1.27.60' - python: '>=3.6' - wrapt: '>=1.10.10' - hash: - md5: a3f48ea10883a5df371b895008b1ca4b - sha256: 76068553358b26c9c03be992cbe982a369d1e015a53700f092db92c784ce98a9 - manager: conda - name: aiobotocore - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/aiobotocore-2.4.2-pyhd8ed1ab_0.conda - version: 2.4.2 + url: https://conda.anaconda.org/conda-forge/noarch/requests-2.29.0-pyhd8ed1ab_0.conda + version: 2.29.0 - category: main dependencies: botocore: '>=1.11.3' python: '>=3.4' wrapt: '' hash: - md5: 2f18ecd9ec078c10f7086ad7ee05289b - sha256: ab3afec58f5368351efac43e813e62f944d41bd879c99e45ad49910aac666447 + md5: a9f8851a7aad0fa6ec843b1beb95decf + sha256: ad37f3f8a6653fb91354716adec29dfb9f5917b7aa06d77f33af8ea7947eb116 manager: conda name: aws-xray-sdk optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/aws-xray-sdk-2.11.0-pyhd8ed1ab_0.tar.bz2 - version: 2.11.0 + url: https://conda.anaconda.org/conda-forge/noarch/aws-xray-sdk-2.12.0-pyhd8ed1ab_0.conda + version: 2.12.0 - category: main dependencies: python: '>=3.6' @@ -4950,14 +4948,14 @@ package: six: '>=1.11.0' typing-extensions: '>=4.0.1' hash: - md5: e49892b87d27fce696b7118a27558fae - sha256: bb995e74396dc34da1a1f9931f40949979913c7b2802c51c799a604edbb45516 + md5: f4d871cde207029fbd3059fc4ad76af9 + sha256: 85884ae07cd171b577dba67059b633df5c6ad0a8fff8222de4bf77530426aea6 manager: conda name: azure-core optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/azure-core-1.26.3-pyhd8ed1ab_0.conda - version: 1.26.3 + url: https://conda.anaconda.org/conda-forge/noarch/azure-core-1.26.4-pyhd8ed1ab_0.conda + version: 1.26.4 - category: main dependencies: msgpack-python: '>=0.5.2' @@ -5004,14 +5002,14 @@ package: urllib3: '>=1.26.0' websocket-client: '>=0.32.0' hash: - md5: 8b0d1b5227ce39053aa69c3ff18417ec - sha256: 45e16e6f7e4105c71c1494ca523b01e676349a25ee1f8114a6c10bbdd8549d50 + md5: 543336c6aa9516cfb29c51d5c162b177 + sha256: 5e01e15e20ee573c99b530633a0d5c71fd515e4ac6d2f5f5f57baece8b915cc3 manager: conda name: docker-py optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/docker-py-6.0.0-pyhd8ed1ab_0.tar.bz2 - version: 6.0.0 + url: https://conda.anaconda.org/conda-forge/noarch/docker-py-6.1.0-pyhd8ed1ab_0.conda + version: 6.1.0 - category: main dependencies: appdirs: '' @@ -5030,19 +5028,19 @@ package: version: 1.4.3 - category: main dependencies: - cryptography: '>=0.6,<41' + cryptography: '>=0.6,<43' pyjwt: '>=1.0.0,<3' python: '>=3.6' requests: '>=2.0.0,<3' hash: - md5: 9304c2492b162934f748d061be0042e8 - sha256: a516cdfa79d90f678507c986da24d5d9979083d90337eeaa17fdd7f3d2e1a976 + md5: 24c290ee3278fd9a33b00cd1f8d1db0f + sha256: 7f4cc4d6383263ad9cc69dc83bb5dd5d4a309ebe53f117e1d14ffd76f31939de manager: conda name: msal optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/msal-1.21.0-pyhd8ed1ab_0.conda - version: 1.21.0 + url: https://conda.anaconda.org/conda-forge/noarch/msal-1.22.0-pyhd8ed1ab_0.conda + version: 1.22.0 - category: main dependencies: graphviz: '>=2.46.1' @@ -5075,14 +5073,14 @@ package: botocore: '>=1.12.36,<2.0a.0' python: '>=3.7' hash: - md5: 900e74d8547fbea3af028937df28ed77 - sha256: 0e459ed32b00e96b62c2ab7e2dba0135c73fd980120fe1a7bd49901f2d50760f + md5: b19a857ac845097e9c823c9f4d35f80e + sha256: 99512bf4f4e297cc7565c94eee8ccc908411f836b341668e2b5d064273e21762 manager: conda name: s3transfer optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/s3transfer-0.6.0-pyhd8ed1ab_0.tar.bz2 - version: 0.6.0 + url: https://conda.anaconda.org/conda-forge/noarch/s3transfer-0.6.1-pyhd8ed1ab_0.conda + version: 0.6.1 - category: main dependencies: alabaster: '>=0.7,<0.8' @@ -5114,7 +5112,7 @@ package: version: 5.1.1 - category: main dependencies: - botocore: 1.27.59 + botocore: 1.29.131 colorama: '>=0.2.5,<0.4.5' docutils: '>=0.10,<0.17' python: '>=3.9,<3.10.0a0' @@ -5123,29 +5121,29 @@ package: rsa: '>=3.1.2,<4.8' s3transfer: '>=0.6.0,<0.7.0' hash: - md5: fa62dd9ed5d234c493ff14914d43f332 - sha256: 61483c628f9751a038d5634ce8ba2ed7ab484ffad50a7e7da13c2e3b30f93eae + md5: 06f90a852ccad1f28aefe0216299b50a + sha256: e26260e3439d5a1b350fe9b244230c0ed2356a4ee873ddbb59a1f2cfa839b627 manager: conda name: awscli optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.25.60-py39hf3d152e_0.tar.bz2 - version: 1.25.60 + url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.27.131-py39hf3d152e_0.conda + version: 1.27.131 - category: main dependencies: - botocore: '>=1.27.59,<1.28.0' + botocore: '>=1.29.131,<1.30.0' jmespath: '>=0.7.1,<2.0.0' python: '>=3.7' s3transfer: '>=0.6.0,<0.7.0' hash: - md5: ffb13a0a5fc8e17ce396f4dfcdf5dab5 - sha256: 89fd09bdc9d9a608387fd80b19fd084f26309d7857bd9a3957216a718f58b3de + md5: f51fe6d09662dc8ec9672be8567b7430 + sha256: 888fa362ba6db8b881a200539c1cc4379379ec1937168e5e475245fa1a3544c7 manager: conda name: boto3 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.24.59-pyhd8ed1ab_0.tar.bz2 - version: 1.24.59 + url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.26.131-pyhd8ed1ab_0.conda + version: 1.26.131 - category: main dependencies: cachecontrol: 0.12.11 pyhd8ed1ab_1 @@ -5167,13 +5165,13 @@ package: networkx: '' python: '>=3.6' hash: - md5: f47b4fbd862cc05b914d2e4862df72a1 - sha256: 3a7f989bdcb5a6a284d092745892f8f27d15b348a02b95229d258899d418fd82 + md5: 184216409957e082712d750862782903 + sha256: 54e9cf114ca4eaeda91b5bb11a09d4391ba4be8a4fb2911259fc7dc2ec636054 manager: conda name: conda-tree optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/conda-tree-1.1.0-pyhd8ed1ab_0.conda + url: https://conda.anaconda.org/conda-forge/noarch/conda-tree-1.1.0-pyhd8ed1ab_2.conda version: 1.1.0 - category: main dependencies: @@ -5206,21 +5204,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/msal_extensions-1.0.0-pyhd8ed1ab_0.tar.bz2 version: 1.0.0 -- category: main - dependencies: - aiobotocore: '>=2.4.2,<2.4.3' - aiohttp: '' - fsspec: 2023.3.0 - python: '>=3.8' - hash: - md5: 53b2e3e80df2a18eb74d53729b9464f2 - sha256: 2737102a9d3d538dccf22fc32e32e2ec608d69c2a002a1f137091b9611bf5d6e - manager: conda - name: s3fs - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/s3fs-2023.3.0-pyhd8ed1ab_0.conda - version: 2023.3.0 - category: main dependencies: livereload: '>=2.3.0' @@ -5286,14 +5269,14 @@ package: python: '' typing_extensions: '' hash: - md5: 009fa15810ae5d376e1bd29ab93c1081 - sha256: 380426f97ae074ad86a1b52bb106e1f10e868bc8b7c575bea6ea5ac7725bc84d + md5: da03042814034e36f0938058b7b218fb + sha256: d18385d39e4af117b99cbd931cb68cbd33582949a837ae4e6453964ecc64d80a manager: conda name: boto3-stubs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.95-pyhd8ed1ab_0.conda - version: 1.26.95 + url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.130-pyhd8ed1ab_0.conda + version: 1.26.130 - category: main dependencies: cachecontrol-with-filecache: '>=0.12.9' @@ -5334,28 +5317,42 @@ package: python: '>=3.6' typing-extensions: '' hash: - md5: 0c79de238c80f668f5a4e85a2ca1dced - sha256: 348b0bdb9d9fcfdfc24c43ea93a29e2c5aba7f8d0e5570517e965c758c380419 + md5: adb30ee4ef9f506b62f732c8a78d250b + sha256: 281ba68f92f05626bf37df32156abbf62e6ed963ab40b2205277a066391cc06f manager: conda name: mypy-boto3-s3 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.26.62-pyhd8ed1ab_0.conda - version: 1.26.62 + url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.26.127-pyhd8ed1ab_0.conda + version: 1.26.127 - category: main dependencies: boto3: '' python: '>=3.6' typing-extensions: '' hash: - md5: a0ead2e95ffa5942c419234c15463344 - sha256: 7e7bb339939a50d9e682c01938062d2d4e1157a7b034d7f91e44e11d98c0d05d + md5: 35a0dc87b7ff0abd9e3012bea164f439 + sha256: 706be4a8f070af47d29e18315c3053977315c1c58479ecfebb2443d3a72edf87 manager: conda name: mypy_boto3_ec2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.26.91-pyhd8ed1ab_0.conda - version: 1.26.91 + url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.26.129-pyhd8ed1ab_0.conda + version: 1.26.129 +- category: main + dependencies: + boto3: '' + fsspec: '>=0.6.0' + python: '>=3.5' + hash: + md5: ead328eb12f01d88706126ba061e7a69 + sha256: 7a4cb574ff7edf773e5e4c396733dcb08ffcfd6e4f8b27e5b84b35fd4666ef5b + manager: conda + name: s3fs + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/s3fs-0.4.2-py_0.tar.bz2 + version: 0.4.2 - category: main dependencies: docutils: <0.19 @@ -5396,18 +5393,18 @@ package: aws-xray-sdk: '!=0.96,>=0.93' boto3: '>=1.9.201' botocore: '>=1.12.201' - cfn-lint: '>=0.4.0' + cfn-lint: '>=0.40.0' cryptography: '>=3.3.1' docker-py: '>=2.5.1' - flask: '' + flask: '!=2.2.0,!=2.2.1' flask_cors: '' graphql-core: '' idna: '>=2.5,<4' importlib_metadata: '' jinja2: '>=2.10.1' jsondiff: '>=1.1.2' - openapi-spec-validator: '' - pyparsing: '' + openapi-spec-validator: '>=0.2.8' + pyparsing: '>=3.0.7' python: '>=3.3' python-dateutil: '>=2.1,<3.0.0' python-jose: '>=3.1.0,<4.0.0' @@ -5417,27 +5414,27 @@ package: responses: '>=0.9.0' setuptools: '' sshpubkeys: '>=3.1.0' - werkzeug: <2.2.0,>=0.5 + werkzeug: '>=0.5,!=2.2.0,!=2.2.1' xmltodict: '' hash: - md5: 702e5d281f691be1bec2f23d1f24fee8 - sha256: 5f7094094ef361b135068b12facdf34c18d2b285c4bd87a935ab1c7e633990ee + md5: 89dfb6776dcc992a100cafd0c612b7fb + sha256: f5de61e07e99798c0f73947fae9f947a4eb7aeff7adc04e78b9a9a3ef2ddc780 manager: conda name: moto optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.5-pyhd8ed1ab_0.conda - version: 4.1.5 + url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.9-pyhd8ed1ab_0.conda + version: 4.1.9 - category: main dependencies: {} hash: - sha256: c41cfb1e99ba5d341fbcc5308836e7d7c9786d302f995b2c271ce2144dece9eb + sha256: 0e0bc5ba78b8db3667ad636d964eb963dc97a59f04c6f6214c5f0e4a8f726c56 manager: pip name: mock optional: false platform: linux-64 - url: https://files.pythonhosted.org/packages/e6/88/8a05e7ad0bb823246b2add3d2e97f990c41c71a40762c8db77a4bd78eedf/mock-5.0.1-py3-none-any.whl - version: 5.0.1 + url: https://files.pythonhosted.org/packages/27/6f/fbb16f260a7107ee98871d83f6793d88c4311b7189b10ef239da0b2181db/mock-5.0.2-py3-none-any.whl + version: 5.0.2 - dependencies: {} hash: sha256: 40527857252b61eacd1d9af500c3337ba8deb8fc298940291486c465c8b46ec0 @@ -5480,15 +5477,17 @@ package: platform: linux-64 url: https://files.pythonhosted.org/packages/9f/53/1ac75eab589149b1e02e38185ecebf09e1b805fc3fdeadbc16d1a2b7d208/paramiko_ng-2.8.10-py2.py3-none-any.whl version: 2.8.10 -- dependencies: - ruamel.yaml.clib: '>=0.2.6' +- category: main + dependencies: + ruamel.yaml.clib: '>=0.2.7' hash: - sha256: 742b35d3d665023981bd6d16b3d24248ce5df75fdb4e2924e93a05c1f8b61ca7 + sha256: 25d0ee82a0a9a6f44683dcf8c282340def4074a4562f3a24f55695bb254c1693 manager: pip name: ruamel.yaml + optional: false platform: linux-64 - url: https://files.pythonhosted.org/packages/9e/cb/938214ac358fbef7058343b3765c79a1b7ed0c366f7f992ce7ff38335652/ruamel.yaml-0.17.21-py3-none-any.whl - version: 0.17.21 + url: https://files.pythonhosted.org/packages/23/33/dbc62343de0cf92e0f9c15bc0a287bdaea0953f1cadca0480c78d5ac6641/ruamel.yaml-0.17.26-py3-none-any.whl + version: 0.17.26 - category: main dependencies: mock: '*' @@ -5521,13 +5520,13 @@ package: pyyaml: '>=6.0,<7.0' ruamel.yaml: '>=0.17.21,<0.18.0' hash: - sha256: 638a6b8c3e631f85f235acf02d3bef35a0a6d7da2ec9fef17420d5dd2ce66678 + sha256: f4fb4dd5f7fac1f2206a25d0949024046fe8f855198e8edbd5206fa9d58ab05f manager: pip name: hammer-vlsi optional: false platform: linux-64 - url: https://files.pythonhosted.org/packages/53/39/18367e6fb4f20e9ae4fb3097f7b80704ff5cccf62980ea2871ba1d817a74/hammer_vlsi-1.1.0-py3-none-any.whl - version: 1.1.0 + url: https://files.pythonhosted.org/packages/0a/da/1897421311c6332655e2f73d02d8c914ecb724198a1988aacd8f4c61ae6e/hammer_vlsi-1.1.1-py3-none-any.whl + version: 1.1.1 - category: main dependencies: asttokens: '>=2,<3' diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml index ca4c96d2..22681575 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml @@ -9,7 +9,7 @@ # To update a single package to the latest version compatible with the version constraints in the source: # conda-lock lock --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE # To re-solve the entire environment, e.g. after changing a version constraint in the source file: -# conda-lock -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml -f /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml +# conda-lock -f /scratch/abejgonza/cy/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml metadata: channels: - url: ucb-bar @@ -21,12 +21,12 @@ metadata: - url: nodefaults used_env_vars: [] content_hash: - linux-64: 1a7b0ae002798a28682d700644302284790c06503a7d3d04caa019aa74da7123 + linux-64: 92c3e7798f0b770b5c7c3ccb9bb821f7aca74819a9dba397e47d752af976b25f platforms: - linux-64 sources: - - /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/chipyard.yaml - - /bwrcq/C/harrisonliew/chipyard-new-hammer/conda-reqs/riscv-tools.yaml + - /scratch/abejgonza/cy/conda-reqs/chipyard.yaml + - /scratch/abejgonza/cy/conda-reqs/riscv-tools.yaml package: - category: main dependencies: {} @@ -42,13 +42,13 @@ package: - category: main dependencies: {} hash: - md5: a581b4a89191b6c1d6a16488a9cffbfc - sha256: 695e67ae4bc22f9e0be5f54b1948a8f2b678f4da920fa2082a249dd5a88f440e + md5: f6ce7955b53ae1ca83144adb3be9c600 + sha256: 546e4eb1cbd822a66b363ec3fbdcc4fcc53853bcab57674cb46b8f3209b856f2 manager: conda name: _sysroot_linux-64_curr_repodata_hack optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h5bd9786_13.tar.bz2 + url: https://conda.anaconda.org/conda-forge/noarch/_sysroot_linux-64_curr_repodata_hack-3-h69a702a_13.conda version: '3' - category: main dependencies: {} @@ -64,14 +64,14 @@ package: - category: main dependencies: {} hash: - md5: ff9f73d45c4a07d6f424495288a26080 - sha256: 8f6c81b0637771ae0ea73dc03a6d30bec3326ba3927f2a7b91931aa2d59b1789 + md5: f5c65075fc34438d5b456c7f3f5ab695 + sha256: 0cf1bb3d0bfc5519b60af2c360fa4888fb838e1476b1e0f65b9dbc48b45c7345 manager: conda name: ca-certificates optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/ca-certificates-2022.12.7-ha878542_0.conda - version: 2022.12.7 + url: https://conda.anaconda.org/conda-forge/linux-64/ca-certificates-2023.5.7-hbcca054_0.conda + version: 2023.5.7 - category: main dependencies: {} hash: @@ -185,14 +185,14 @@ package: - category: main dependencies: {} hash: - md5: 7697d37e29669a14b053e82fad22a16b - sha256: ac993fa2774b90befcd6aba55b1c08853b2fa3b818753094c09bebd35fc55532 + md5: 0299e410bfb4300540bdc0012a7985ef + sha256: 8572efb7092c72fe7b73d2a0f1e5e27159a8edea0371e1bef533bcb7d85b19c6 manager: conda name: open_pdks.sky130a optional: false platform: linux-64 - url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.402_1_g12df12e-20230225_164303.tar.bz2 - version: 1.0.402_1_g12df12e + url: https://conda.anaconda.org/litex-hub/noarch/open_pdks.sky130a-1.0.406_0_g0c37b7c-20230412_103222.tar.bz2 + version: 1.0.406_0_g0c37b7c - category: main dependencies: {} hash: @@ -207,14 +207,14 @@ package: - category: main dependencies: {} hash: - md5: 51fc4fcfb19f5d95ffc8c339db5068e8 - sha256: 0bfae0b9962bc0dbf79048f9175b913ed4f53c4310d06708dc7acbb290ad82f6 + md5: 939e3e74d8be4dac89ce83b20de2492a + sha256: 0449138224adfa125b220154408419ec37c06b0b49f63c5954724325903ecf55 manager: conda name: tzdata optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2022g-h191b570_0.conda - version: 2022g + url: https://conda.anaconda.org/conda-forge/noarch/tzdata-2023c-h71feb2d_0.conda + version: 2023c - category: main dependencies: font-ttf-dejavu-sans-mono: '' @@ -394,14 +394,14 @@ package: dependencies: libgcc-ng: '>=12' hash: - md5: 80968e6760b2448f739cd32b1324d07d - sha256: c8b52559c1867ad59510c9479a15581cbfda0a7857a33ff2fce03a76a0775cfb + md5: 2975fe44881f8dce5c3759b53abf11d1 + sha256: 1c65245dc63a3f5a57040074c61baa2ae9dcb401753503712401867b02c6dcab manager: conda name: coreutils optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/coreutils-9.2-h0b41bf4_0.conda - version: '9.2' + url: https://conda.anaconda.org/conda-forge/linux-64/coreutils-9.3-h0b41bf4_0.conda + version: '9.3' - category: main dependencies: libgcc-ng: '>=7.3.0' @@ -426,19 +426,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/ucb-bar/linux-64/dromajo-1.0.0-0_h1234567_g6a6e34e.tar.bz2 version: 1.0.0 -- category: main - dependencies: - libgcc-ng: '>=12' - libstdcxx-ng: '>=12' - hash: - md5: c4fbad8d4bddeb3c085f18cbf97fbfad - sha256: b44db0b92ae926b3fbbcd57c179fceb64fa11a9f9d09082e03be58b74dcad832 - manager: conda - name: expat - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/expat-2.5.0-h27087fc_0.tar.bz2 - version: 2.5.0 - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -528,29 +515,17 @@ package: version: '1.12' - category: main dependencies: - libgcc-ng: '>=10.3.0' - libstdcxx-ng: '>=10.3.0' + libgcc-ng: '>=12' + libstdcxx-ng: '>=12' hash: - md5: 87473a15119779e021c314249d4b4aed - sha256: 1d7950f3be4637ab915d886304e57731d39a41ab705ffc95c4681655c459374a + md5: 7c8d20d847bb45f56bd941578fcfa146 + sha256: e44cc00eec068e7f7a6dd117ba17bf5d57658729b7b841945546f82505138292 manager: conda name: icu optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/icu-70.1-h27087fc_0.tar.bz2 - version: '70.1' -- category: main - dependencies: - libgcc-ng: '>=12' - hash: - md5: c7a069243e1fbe9a556ed2ec030e6407 - sha256: 8f73194d09c9ea4a7e2b3562766b8d72125cc147b62c7cf83393e3a3bbfd581b - manager: conda - name: jpeg - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/jpeg-9e-h0b41bf4_3.conda - version: 9e + url: https://conda.anaconda.org/conda-forge/linux-64/icu-72.1-hcb278e6_0.conda + version: '72.1' - category: main dependencies: libgcc-ng: '>=10.3.0' @@ -592,14 +567,14 @@ package: dependencies: libgcc-ng: '>=12' hash: - md5: 5cc781fd91968b11a8a7fdbee0982676 - sha256: f9983a8ea03531f2c14bce76c870ca325c0fddf0c4e872bff1f78bc52624179c + md5: 6aa9c9de5542ecb07fdda9ca626252d8 + sha256: 949d84ceea543802c1e085b2aa58f1d6cb5dd8cec5a9abaaf4e8ac65d6094b3a manager: conda name: libdeflate optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libdeflate-1.17-h0b41bf4_0.conda - version: '1.17' + url: https://conda.anaconda.org/conda-forge/linux-64/libdeflate-1.18-h0b41bf4_0.conda + version: '1.18' - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -612,6 +587,18 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libev-4.33-h516909a_1.tar.bz2 version: '4.33' +- category: main + dependencies: + libgcc-ng: '>=12' + hash: + md5: 6305a3dd2752c76335295da4e581f2fd + sha256: 74c98a563777ae2ad71f1f74d458a8ab043cee4a513467c159ccf159d0e461f3 + manager: conda + name: libexpat + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/libexpat-2.5.0-hcb278e6_1.conda + version: 2.5.0 - category: main dependencies: libgcc-ng: '>=12' @@ -648,6 +635,18 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libiconv-1.17-h166bdaf_0.tar.bz2 version: '1.17' +- category: main + dependencies: + libgcc-ng: '>=12' + hash: + md5: 1edd9e67bdb90d78cea97733ff6b54e6 + sha256: b19de7bda34eac4fa931be11fa8d7640cdf1441dfd51c91786586a4a4c64c92f + manager: conda + name: libjpeg-turbo + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/libjpeg-turbo-2.1.5.1-h0b41bf4_0.conda + version: 2.1.5.1 - category: main dependencies: libgcc-ng: '>=9.4.0' @@ -736,16 +735,16 @@ package: version: 0.9.10 - category: main dependencies: - libgcc-ng: '>=9.3.0' + libgcc-ng: '>=12' hash: - md5: 772d69f030955d9646d3d0eaf21d859d - sha256: 54f118845498353c936826f8da79b5377d23032bcac8c4a02de2019e26c3f6b3 + md5: 40b61aab5c7ba9ff276c41cfffe6b80b + sha256: 787eb542f055a2b3de553614b25f09eefb0a0931b0c87dbcce6efdfd92f04f18 manager: conda name: libuuid optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libuuid-2.32.1-h7f98852_1000.tar.bz2 - version: 2.32.1 + url: https://conda.anaconda.org/conda-forge/linux-64/libuuid-2.38.1-h0b41bf4_0.conda + version: 2.38.1 - category: main dependencies: libgcc-ng: '>=12' @@ -762,14 +761,14 @@ package: dependencies: libgcc-ng: '>=12' hash: - md5: ac2ccf7323d21f2994e4d1f5da664f37 - sha256: 221f2e138dd264b7394b88f08884d93825d38800a51415059e813c02467abfd1 + md5: 0d4a7508d8c6c65314f2b9c1f56ad408 + sha256: ac3e073ea77803da71eb77e7fcef07defb345bda95eee3327c73ddf85b5714da manager: conda name: libwebp-base optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-base-1.2.4-h166bdaf_0.tar.bz2 - version: 1.2.4 + url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-base-1.3.0-h0b41bf4_0.conda + version: 1.3.0 - category: main dependencies: libgcc-ng: '>=12' @@ -872,13 +871,13 @@ package: ca-certificates: '' libgcc-ng: '>=12' hash: - md5: 2d833be81a21128e317325a01326d36f - sha256: d378afcec34b86fef4da3ebd622b3e614cb3f71e54b6a5a10adb1d23745ecc72 + md5: 8f24d371ed9efb3f0b0de383fb81d51c + sha256: 24bf6cf8f741c28a8d10f51c917f378694d4a98a38ab4372629932cd6c94e9e8 manager: conda name: openssl optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/openssl-3.1.0-h0b41bf4_0.conda + url: https://conda.anaconda.org/conda-forge/linux-64/openssl-3.1.0-hd590300_3.conda version: 3.1.0 - category: main dependencies: @@ -954,15 +953,15 @@ package: version: '6.0' - category: main dependencies: - libgcc-ng: '>=7.3.0' + libgcc-ng: '>=12' hash: - md5: 2e5f1a8199794b21c9472c1a7f27e21a - sha256: a3ee6c02932fbee32babe39fa6bda9f781d6dc17122d2a90e62ff2b6866a5de8 + md5: 76d6bc123c1c75bf034c412856fcc935 + sha256: e94d0d5f75a5f58165ad8ac64a25df851c77ec6e9bf626c16807dcbd740226c8 manager: conda name: which optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/which-2.21-h516909a_0.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/which-2.21-h0b41bf4_1.conda version: '2.21' - category: main dependencies: @@ -1135,6 +1134,19 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/dtc-1.6.1-h166bdaf_2.tar.bz2 version: 1.6.1 +- category: main + dependencies: + libexpat: 2.5.0 hcb278e6_1 + libgcc-ng: '>=12' + hash: + md5: 8b9b5aca60558d02ddaa09d599e55920 + sha256: 36dfeb4375059b3bba75ce9b38c29c69fd257342a79e6cf20e9f25c1523f785f + manager: conda + name: expat + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/expat-2.5.0-hcb278e6_1.conda + version: 2.5.0 - category: main dependencies: gettext: '' @@ -1334,14 +1346,14 @@ package: libgcc-ng: '>=12' libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: 2e5f9a37d487e1019fd4d8113adb2f9f - sha256: 6008a0b914bd1a3510a3dba38eada93aa0349ebca3a21e5fa276833c8205bf49 + md5: 1d002bf709048f8021c32abfd0e0d395 + sha256: bb2a8ddb26e74f2cedc36825fc6f95d45f19e1912a1a6c75847952d92fc16215 manager: conda name: libsqlite optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libsqlite-3.40.0-h753d276_0.tar.bz2 - version: 3.40.0 + url: https://conda.anaconda.org/conda-forge/linux-64/libsqlite-3.41.2-h2797004_1.conda + version: 3.41.2 - category: main dependencies: libgcc-ng: '>=12' @@ -1373,20 +1385,20 @@ package: version: '1.13' - category: main dependencies: - icu: '>=70.1,<71.0a0' + icu: '>=72.1,<73.0a0' libgcc-ng: '>=12' libiconv: '>=1.17,<2.0a0' libzlib: '>=1.2.13,<1.3.0a0' xz: '>=5.2.6,<6.0a0' hash: - md5: bb808b654bdc3c783deaf107a2ffb503 - sha256: d4170f1fe356768758b13a51db123f990bff81b0eae0d5a0ba11c7ca6b9536f4 + md5: 241845899caff54ac1d2b3102ad988cf + sha256: 624b6e29e23a51353cff2aff7364c42b831139afd131d239e79f60aea4dae887 manager: conda name: libxml2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libxml2-2.10.3-hca2bb57_4.conda - version: 2.10.3 + url: https://conda.anaconda.org/conda-forge/linux-64/libxml2-2.10.4-hfdac1af_0.conda + version: 2.10.4 - category: main dependencies: libgcc-ng: '>=7.3.0' @@ -1472,14 +1484,14 @@ package: libgcc-ng: '>=12' ncurses: '>=6.3,<7.0a0' hash: - md5: db2ebbe2943aae81ed051a6a9af8e0fa - sha256: f5f383193bdbe01c41cb0d6f99fec68e820875e842e6e8b392dbe1a9b6c43ed8 + md5: 47d31b792659ce70f470b5c82fdfb7a4 + sha256: 5435cf39d039387fbdc977b0a762357ea909a7694d9528ab40f005e9208744d7 manager: conda name: readline optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/readline-8.1.2-h0f457ee_0.tar.bz2 - version: 8.1.2 + url: https://conda.anaconda.org/conda-forge/linux-64/readline-8.2-h8228510_1.conda + version: '8.2' - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -1589,17 +1601,17 @@ package: version: '2.71' - category: main dependencies: - libgcc-ng: '>=10.3.0' - readline: '>=8.1,<9.0a0' + libgcc-ng: '>=12' + readline: '>=8.2,<9.0a0' hash: - md5: 54d1a374b75f14ecc58aea8c4236c0c3 - sha256: 6415903ad8774fc0f1bf5b156ae0b6f9988427a0f14bb35467c5938f05fe8707 + md5: 23b559a791d63ba4f51906763eb6bc53 + sha256: a7b2ea50068d86ac6e3749f76b118b15947d3f5ce48535eb5ab2ff7e22659c49 manager: conda name: bash optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/bash-5.1.16-hd863ed2_0.tar.bz2 - version: 5.1.16 + url: https://conda.anaconda.org/conda-forge/linux-64/bash-5.2.15-hfbf034d_0.conda + version: 5.2.15 - category: main dependencies: flex: '' @@ -1685,13 +1697,13 @@ package: dependencies: gcc_impl_linux-64: 12.2.0.* hash: - md5: b4d86475bd1a21d139ea78770f606471 - sha256: 3cfb989723f8e115d35553c2b1d899b0f4185fc0551a996b9ff4037083a36432 + md5: ec93d13e0fe8514f65842120dbae1b16 + sha256: 5478f5b7672b6c2d5b644aaa9fe18fbb1468ca6ea9cea1b0f0a2254459438e24 manager: conda name: gcc optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gcc-12.2.0-h26027b1_11.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/gcc-12.2.0-h26027b1_13.conda version: 12.2.0 - category: main dependencies: @@ -1782,14 +1794,14 @@ package: libzlib: '>=1.2.13,<1.3.0a0' pcre2: '>=10.40,<10.41.0a0' hash: - md5: ed5349aa96776e00b34eccecf4a948fe - sha256: 3cbad3d63cff2dd9ac1dc9cce54fd3d657f3aff53df41bfe5bae9d760562a5af + md5: db1d4a1dfc04f3eab50d97551850759a + sha256: e0d54ffe98b7471cfc95f043bf3921412843c05ba5f1f10ceeac5edb328ac928 manager: conda name: libglib optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libglib-2.74.1-h606061b_1.tar.bz2 - version: 2.74.1 + url: https://conda.anaconda.org/conda-forge/linux-64/libglib-2.76.2-hebfc3b9_0.conda + version: 2.76.2 - category: main dependencies: libblas: 3.9.0 16_linux64_openblas @@ -1806,37 +1818,37 @@ package: dependencies: libgcc-ng: '>=12' libstdcxx-ng: '>=12' - libxml2: '>=2.10.3,<2.11.0a0' + libxml2: '>=2.10.4,<2.11.0a0' libzlib: '>=1.2.13,<1.3.0a0' zstd: '>=1.5.2,<1.6.0a0' hash: - md5: 17d91085ccf5934ce652cb448d0cb65a - sha256: f649fac60cb122bf0d85c4955725d94c353fdbd768bcd44f0444979b363cc9ab + md5: 3d942f062d7656168bb42b3439bdfede + sha256: c52c239b583a1b2d03bdc641afd8cbab0499b0a46ea55b40e1dbed112283a772 manager: conda - name: libllvm15 + name: libllvm16 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libllvm15-15.0.7-hadd5161_1.conda - version: 15.0.7 + url: https://conda.anaconda.org/conda-forge/linux-64/libllvm16-16.0.3-hbf9e925_1.conda + version: 16.0.3 - category: main dependencies: - jpeg: '>=9e,<10a' lerc: '>=4.0.0,<5.0a0' - libdeflate: '>=1.17,<1.18.0a0' + libdeflate: '>=1.18,<1.19.0a0' libgcc-ng: '>=12' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libstdcxx-ng: '>=12' - libwebp-base: '>=1.2.4,<2.0a0' + libwebp-base: '>=1.3.0,<2.0a0' libzlib: '>=1.2.13,<1.3.0a0' xz: '>=5.2.6,<6.0a0' zstd: '>=1.5.2,<1.6.0a0' hash: - md5: 2e648a34072eb39d7c4fc2a9981c5f0c - sha256: e3e18d91fb282b61288d4fd2574dfa31f7ae90ef2737f96722fb6ad3257862ee + md5: 4e5ee4b062c21519efbee7e2ae608748 + sha256: caacb23e1b95fbdd8115be69228f9c82068ed87bf57f055027e31d093ae6a1a2 manager: conda name: libtiff optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libtiff-4.5.0-h6adf6a1_2.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libtiff-4.5.0-ha587672_6.conda version: 4.5.0 - category: main dependencies: @@ -1881,20 +1893,20 @@ package: libuuid: '>=2.32.1,<3.0a0' libzlib: '>=1.2.13,<1.3.0a0' ncurses: '>=6.3,<7.0a0' - openssl: '>=3.0.7,<4.0a0' - readline: '>=8.1.2,<9.0a0' + openssl: '>=3.1.0,<4.0a0' + readline: '>=8.2,<9.0a0' tk: '>=8.6.12,<8.7.0a0' tzdata: '' xz: '>=5.2.6,<6.0a0' hash: - md5: 3cb3e91b3fe66baa68a12c85f39b9b40 - sha256: 073878d7cc9c7e25cf04983d02e6d44b531d47e0166258cbce964dd78bb716a9 + md5: de25afc7041c103c7f510c746bb63435 + sha256: 67748307da3fa057d17d4e991f3c60f87595a517b98f4b323a17b5f3dc287159 manager: conda name: python optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/python-3.10.9-he550d4f_0_cpython.conda - version: 3.10.9 + url: https://conda.anaconda.org/conda-forge/linux-64/python-3.10.10-he550d4f_0_cpython.conda + version: 3.10.10 - category: main dependencies: libgcc-ng: '>=12' @@ -1917,19 +1929,19 @@ package: - category: main dependencies: libgcc-ng: '>=12' - libsqlite: 3.40.0 h753d276_0 + libsqlite: 3.41.2 h2797004_1 libzlib: '>=1.2.13,<1.3.0a0' ncurses: '>=6.3,<7.0a0' - readline: '>=8.1.2,<9.0a0' + readline: '>=8.2,<9.0a0' hash: - md5: bb11803129cbbb53ed56f9506ff74145 - sha256: baf0e77938e5215653aa6609ff154cb94aeb0a08083ff8dec2d3ba8dd62263e9 + md5: c8771266cc289756099c04e597209862 + sha256: 2674e5b0888799ad055bdbc79e2257d67f52b0c11f4c174d4deff4b69874cf45 manager: conda name: sqlite optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/sqlite-3.40.0-h4ff8645_0.tar.bz2 - version: 3.40.0 + url: https://conda.anaconda.org/conda-forge/linux-64/sqlite-3.41.2-h2c6b66d_1.conda + version: 3.41.2 - category: main dependencies: libgcc-ng: '>=9.4.0' @@ -1988,16 +2000,16 @@ package: version: 1.4.4 - category: main dependencies: - python: '>=3.6' + python: '>=3.7' hash: - md5: b3c15cb1d45fd10bc6f652bbc51e023a - sha256: 8dbc6de55113ea67a64f0be5d16ba939d1b58a25dbd9a5cc62b571cef24ef85c + md5: 0b3460f5bf4ae27dfd72fdcccc9667a9 + sha256: 18aad01518cb08e4eff18e507e14ebf6c522d89ef53ca267c48080933c4435f7 manager: conda name: argcomplete optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.0.2-pyhd8ed1ab_0.conda - version: 3.0.2 + url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.0.8-pyhd8ed1ab_0.conda + version: 3.0.8 - category: main dependencies: libgcc-ng: '>=12' @@ -2014,16 +2026,28 @@ package: version: 2.38.0 - category: main dependencies: - python: '>=3.5' + python: '>=3.7' hash: - md5: 8b76db7818a4e401ed4486c4c1635cd9 - sha256: 3a58d4a4933fa8735471c782d35326ab78e0bcfce84756408515f82a94e4dec4 + md5: 3edfead7cedd1ab4400a6c588f3e75f8 + sha256: 063639cd568f5c7a557b0fb1cc27f098598c0d8ff869088bfeb82934674f8821 manager: conda name: attrs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/attrs-22.2.0-pyh71513ae_0.conda - version: 22.2.0 + url: https://conda.anaconda.org/conda-forge/noarch/attrs-23.1.0-pyh71513ae_1.conda + version: 23.1.0 +- category: main + dependencies: + python: '>=3.7' + hash: + md5: 2fb79ec81bad9492b6d59a06b3b647a4 + sha256: b6f32491536823e47cf6eb4717dd341385600a2b901235028dedc629a77aeb82 + manager: conda + name: blinker + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/blinker-1.6.2-pyhd8ed1ab_0.conda + version: 1.6.2 - category: main dependencies: brotli-bin: 1.0.9 h166bdaf_8 @@ -2055,14 +2079,14 @@ package: dependencies: python: '>=3.7' hash: - md5: fb9addc3db06e56abe03e0e9f21a63e6 - sha256: 5e22af4776700200fab2c1df41a2188ab9cfe90a50c4f388592bb978562c88ec + md5: 5d1b71c942b8421285934dad1d891ebc + sha256: f839a6e04d94069f90dd85337ea9108f058dc76771bb469a413f32bb1ba0b256 manager: conda name: certifi optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/certifi-2022.12.7-pyhd8ed1ab_0.conda - version: 2022.12.7 + url: https://conda.anaconda.org/conda-forge/noarch/certifi-2023.5.7-pyhd8ed1ab_0.conda + version: 2023.5.7 - category: main dependencies: python: '>=3.6.1' @@ -2089,16 +2113,16 @@ package: version: 2.1.1 - category: main dependencies: - __unix: '' - python: '>=3.8' + python: '>=3.10,<3.11.0a0' + python_abi: 3.10.* *_cp310 hash: - md5: 20e4087407c7cb04a40817114b333dbf - sha256: 23676470b591b100393bb0f6c46fe10624dcbefc696a6a9f42932ed8816ef0ea + md5: 9bb8d28c0899d583a062c17b15ee3e89 + sha256: 550b1266fed8a3bbfc2e7d5cbe646668aca5b5f1c3b4ac9a17ca2d215d06785a manager: conda name: click optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/click-8.1.3-unix_pyhd8ed1ab_2.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/click-8.1.3-py310hff52083_1.tar.bz2 version: 8.1.3 - category: main dependencies: @@ -2203,14 +2227,14 @@ package: dependencies: python: '>=3.7' hash: - md5: 6f90f1dc834447823b11d155726fcb37 - sha256: 6a6901f20c5b4d81aebd25a0645b3578ebb6a323f9fd7e87ee05ecbcfe19069e + md5: 650f18a56f366dbf419c15b543592c2d + sha256: 68db3a6280d6786be76f2c7c6cf41dd878c5d1a24f5de10f7f0af82c6fcfade6 manager: conda name: filelock optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/filelock-3.10.0-pyhd8ed1ab_0.conda - version: 3.10.0 + url: https://conda.anaconda.org/conda-forge/noarch/filelock-3.12.0-pyhd8ed1ab_0.conda + version: 3.12.0 - category: main dependencies: expat: '>=2.5.0,<3.0a0' @@ -2245,29 +2269,30 @@ package: dependencies: python: '>=3.8' hash: - md5: 0db48a2f5a68e28e5af8d3df276f2255 - sha256: dfcee90620d13f4f667664620191d780c79ec7e9ba9908cd771d24a1361e0cc9 + md5: 20edd290b319aa0eff3e9055375756dc + sha256: cbb5c77c0217cda9bf4f4240158de11822a099a6eaa05ba626e822819a54f46d manager: conda name: fsspec optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/fsspec-2023.3.0-pyhd8ed1ab_1.conda - version: 2023.3.0 + url: https://conda.anaconda.org/conda-forge/noarch/fsspec-2023.5.0-pyh1a96a4e_0.conda + version: 2023.5.0 - category: main dependencies: - jpeg: '>=9e,<10a' libgcc-ng: '>=12' libglib: '>=2.74.1,<3.0a0' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libpng: '>=1.6.39,<1.7.0a0' libtiff: '>=4.5.0,<4.6.0a0' + libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: 1a109126a43003d65b39c1cad656bc9b - sha256: a27f49d85e0a730374cc77606e9484b23b0f3edf32df1994b6d7ff5dd44aef92 + md5: ee8220db21db8094998005990418fe5b + sha256: 7acc699871310e9a89aaa7e90de9ac949e2fa649232c8a8dfcafa67e8f36a266 manager: conda name: gdk-pixbuf optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gdk-pixbuf-2.42.10-h05c8ddd_0.conda + url: https://conda.anaconda.org/conda-forge/linux-64/gdk-pixbuf-2.42.10-h6b639ba_2.conda version: 2.42.10 - category: main dependencies: @@ -2305,13 +2330,13 @@ package: gcc: 12.2.0.* gxx_impl_linux-64: 12.2.0.* hash: - md5: 2b54322e0dbb1345d64913e8b20b7d7c - sha256: f6c390055f2846d6013160c41dece0973daf577c5f1aaa73ff5dcf597b35d0ec + md5: de605ff437f3fdc010f1b529642339f1 + sha256: 58bc0a7ff843c4ac2fd53b1370d266d635b59cf8d1d6f165cc26cf1f5324c9f8 manager: conda name: gxx optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gxx-12.2.0-h26027b1_11.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/gxx-12.2.0-h26027b1_13.conda version: 12.2.0 - category: main dependencies: @@ -2439,48 +2464,46 @@ package: version: 1.4.4 - category: main dependencies: - jpeg: '>=9e,<10a' libgcc-ng: '>=12' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libtiff: '>=4.5.0,<4.6.0a0' hash: - md5: aa8840cdf17ef0c6084d1e24abc7a28b - sha256: 443e926b585528112ec6aa4d85bf087722914ed8d85a2f75ae47c023c55c4238 + md5: 980d8aca0bc23ca73fa8caa3e7c84c28 + sha256: 0d88e0e7f8dbf8f01788e21dd63dd49b89433ce7dfd10f53839441396f6481cd manager: conda name: lcms2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/lcms2-2.15-hfd0df8a_0.conda + url: https://conda.anaconda.org/conda-forge/linux-64/lcms2-2.15-haa2dc70_1.conda version: '2.15' - category: main dependencies: libgcc-ng: '>=12' - libllvm15: '>=15.0.7,<15.1.0a0' + libllvm16: '>=16.0.3,<16.1.0a0' libstdcxx-ng: '>=12' - libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: 276ec1f956a520363016f909ec166f65 - sha256: 48c0820ba1fe5701d11a5b7967a2c93d73607741a20e511214ece7fec7b9dc7f + md5: 205aca93c1bc4a0bc663dd787c224025 + sha256: 66e0e925088acbc1306c814ca8441e61dd2f2a2ff93ff752b914939b87864d24 manager: conda - name: libclang-cpp15 + name: libclang-cpp16 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libclang-cpp15-15.0.7-default_had23c3d_1.conda - version: 15.0.7 + url: https://conda.anaconda.org/conda-forge/linux-64/libclang-cpp16-16.0.3-default_h83cc7fd_0.conda + version: 16.0.3 - category: main dependencies: libgcc-ng: '>=12' - libllvm15: '>=15.0.7,<15.1.0a0' + libllvm16: '>=16.0.3,<16.1.0a0' libstdcxx-ng: '>=12' - libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: a3a0f7a6f0885f5e1e0ec691566afb77 - sha256: e48481c37d02aefeddcfac20d48cf13b838c5f7b9018300fa7eac404d30f3d7f + md5: e0f95087543b73c7bc2689f0aeb86a6d + sha256: 40c7a6ebfe181b3683fa4c0a378ff25eca1a77d68c35578b9c237dd58c4d458d manager: conda name: libclang13 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libclang13-15.0.7-default_h3e3d535_1.conda - version: 15.0.7 + url: https://conda.anaconda.org/conda-forge/linux-64/libclang13-16.0.3-default_hd781213_0.conda + version: 16.0.3 - category: main dependencies: krb5: '>=1.20.1,<1.21.0a0' @@ -2542,20 +2565,20 @@ package: - category: main dependencies: giflib: '>=5.2.1,<5.3.0a0' - jpeg: '>=9e,<10a' libgcc-ng: '>=12' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libpng: '>=1.6.39,<1.7.0a0' libtiff: '>=4.5.0,<4.6.0a0' - libwebp-base: '>=1.2.4,<2.0a0' + libwebp-base: '>=1.3.0,<2.0a0' hash: - md5: 77003f63d1763c1e6569a02c1742c9f4 - sha256: 43d563a16fe9db32b7d0be8d89968005f21139e9285dfe1fbfe9ae6647f1cc9f + md5: 9cfd7ad6e1539ca1ad172083586b3301 + sha256: 461fe2c0279309c21f206f114f3bd6592e906ef6f8cc181b2e28482941b8b925 manager: conda name: libwebp optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-1.2.4-h1daa5a0_1.conda - version: 1.2.4 + url: https://conda.anaconda.org/conda-forge/linux-64/libwebp-1.3.0-hb47c5f0_0.conda + version: 1.3.0 - category: main dependencies: python: '' @@ -2669,14 +2692,14 @@ package: python: '>=3.10,<3.11.0a0' python_abi: 3.10.* *_cp310 hash: - md5: b7085457309e206174b8e234d90a7605 - sha256: d2c58f7f9a0c023c5fe130ef781e0d77b3717cc5f78587fe97b9a57635e2a93d + md5: 844b150744d30f256d7937f3f60fcd2f + sha256: d531c8dcbecb2d47d26fcafce00dd244bfb4fdc787eddea40e61b5b57b0e5da2 manager: conda name: numpy optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/numpy-1.24.2-py310h8deb116_0.conda - version: 1.24.2 + url: https://conda.anaconda.org/conda-forge/linux-64/numpy-1.24.3-py310ha4c1d20_0.conda + version: 1.24.3 - category: main dependencies: libgcc-ng: '>=12' @@ -2697,14 +2720,14 @@ package: dependencies: python: '>=3.7' hash: - md5: 1ff2e3ca41f0ce16afec7190db28288b - sha256: 00288f5e5e841711e8b8fef1f1242c858d8ef99ccbe5d7e0df4789d5d8d40645 + md5: 91cda59e66e1e4afe9476f8ef98f5c30 + sha256: ded536a96a00d45a693dbc2971bb688248324dadd129eddda2100e177583d768 manager: conda name: packaging optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/packaging-23.0-pyhd8ed1ab_0.conda - version: '23.0' + url: https://conda.anaconda.org/conda-forge/noarch/packaging-23.1-pyhd8ed1ab_0.conda + version: '23.1' - category: main dependencies: python: '>=2.7' @@ -2731,15 +2754,16 @@ package: version: 1.9.6 - category: main dependencies: - python: '>=3.8' + python: '>=3.10,<3.11.0a0' + python_abi: 3.10.* *_cp310 hash: - md5: 7d301a0d25f424d96175f810935f0da9 - sha256: c25e1757e4e90638bb1e778aba3ee5f3c01fae9752e3c3929f9be7d367f6c7f3 + md5: 02e428ab589e3cefe070352c905cefec + sha256: 28967130059ac29a1298de5f4555c0ec6344ea56e32642c44f40c19d83f38162 manager: conda name: pluggy optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pluggy-1.0.0-pyhd8ed1ab_5.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/pluggy-1.0.0-py310hff52083_4.tar.bz2 version: 1.0.0 - category: main dependencies: @@ -2760,14 +2784,14 @@ package: python: '>=3.10,<3.11.0a0' python_abi: 3.10.* *_cp310 hash: - md5: c3c55664e9becc48e6a652e2b641961f - sha256: efaf186bc3be5074ff44a25372ec0f21564c0a8f9cd3ed3e8378389745999be5 + md5: b0f0a014fc04012c05f39df15fe270ce + sha256: 6864a95001b67413f7d06e35dc2ef0f13afb8c93cde8e826321453eac1bf1991 manager: conda name: psutil optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/psutil-5.9.4-py310h5764c6d_0.tar.bz2 - version: 5.9.4 + url: https://conda.anaconda.org/conda-forge/linux-64/psutil-5.9.5-py310h1fa729e_0.conda + version: 5.9.5 - category: main dependencies: python: '' @@ -2806,18 +2830,30 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/pycparser-2.21-pyhd8ed1ab_0.tar.bz2 version: '2.21' +- category: main + dependencies: + python: '>=3.7' + hash: + md5: d316679235612869eba305aa7d41d9bf + sha256: 1bddeb54863c77ed5613b535a3e06a3a16b55786301a5e28c9bf011656bda686 + manager: conda + name: pygments + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/pygments-2.15.1-pyhd8ed1ab_0.conda + version: 2.15.1 - category: main dependencies: python: '>=3.6' hash: - md5: 56d08bbebf5b3719ca2b1688fcfd98a4 - sha256: 177ce344fc9668cc1e7daa637ef375f6765e60fbb52e83a5744a0513751200aa + md5: 99e28be5a278e2319834d7dc99e7bfdd + sha256: f3a64306fa0f405f10f4108d7ff42043d6fd393f940f9e98e395a3756687fc98 manager: conda name: pyjwt optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pyjwt-2.6.0-pyhd8ed1ab_0.tar.bz2 - version: 2.6.0 + url: https://conda.anaconda.org/conda-forge/noarch/pyjwt-2.7.0-pyhd8ed1ab_0.conda + version: 2.7.0 - category: main dependencies: python: '>=3.3' @@ -2858,29 +2894,41 @@ package: version: 0.19.3 - category: main dependencies: - __unix: '' - python: '>=3.8' + python: '>=3.10,<3.11.0a0' + python_abi: 3.10.* *_cp310 hash: - md5: 2a7de29fb590ca14b5243c4c812c8025 - sha256: a42f826e958a8d22e65b3394f437af7332610e43ee313393d1cf143f0a2d274b + md5: 378f2260e871f3ea46c6fa58d9f05277 + sha256: cb6e4821234cee05acd1996cef88e40dfc2d5ab12cf12c5b1d6ed9118f7f41a7 manager: conda name: pysocks optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pysocks-1.7.1-pyha2e5f31_6.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/pysocks-1.7.1-py310hff52083_5.tar.bz2 version: 1.7.1 - category: main dependencies: python: '>=3.6' hash: - md5: f59d49a7b464901cf714b9e7984d01a2 - sha256: 93cfc7a92099e26b0575a343da4a667b52371cc38e4dee4ee264dc041ef77bac + md5: 2590495f608a63625e165915fb4e2e34 + sha256: 0108888507014fb24573c31e4deceb61c99e63d37776dddcadd7c89b2ecae0b6 + manager: conda + name: python-tzdata + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/python-tzdata-2023.3-pyhd8ed1ab_0.conda + version: '2023.3' +- category: main + dependencies: + python: '>=3.6' + hash: + md5: d3076b483092a435832603243567bc31 + sha256: e4999484f21763ca4b8f92c95b22cb6d1edc1b61d0a2bb073ee2bd11f39401b9 manager: conda name: pytz optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pytz-2022.7.1-pyhd8ed1ab_0.conda - version: 2022.7.1 + url: https://conda.anaconda.org/conda-forge/noarch/pytz-2023.3-pyhd8ed1ab_0.conda + version: '2023.3' - category: main dependencies: __unix: '' @@ -2961,14 +3009,14 @@ package: dependencies: python: '>=3.7' hash: - md5: e18ed61c37145bb9b48d1d98801960f7 - sha256: a5c48b1fc7c89c5c937475e9434a63af7ce2e591f8e51afd56e3b2e232a9989d + md5: 3b68bc43ec6baa48f7354a446267eefe + sha256: 3ac44771fce01f19218bcdf3992e24984748048db69889a9df65abcc6a10e29b manager: conda name: setuptools optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/setuptools-67.6.0-pyhd8ed1ab_0.conda - version: 67.6.0 + url: https://conda.anaconda.org/conda-forge/noarch/setuptools-67.7.2-pyhd8ed1ab_0.conda + version: 67.7.2 - category: main dependencies: python: '' @@ -3101,6 +3149,18 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/tomli-2.0.1-pyhd8ed1ab_0.tar.bz2 version: 2.0.1 +- category: main + dependencies: + python: '>=3.7' + hash: + md5: 75838e8556166263a82038b51d01d5f1 + sha256: 3002e87338a98ba501fbf53981f8267b2def2548265a3622d403d06747872ccd + manager: conda + name: tomlkit + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/tomlkit-0.11.8-pyha770c72_0.conda + version: 0.11.8 - category: main dependencies: python: '>=3.5' @@ -3119,62 +3179,50 @@ package: python: '>=3.10,<3.11.0a0' python_abi: 3.10.* *_cp310 hash: - md5: be4a201ac582c11d89ed7d15b3157cc3 - sha256: 7ca198ff3c4e9ab0a8c19fbd8dafe4ae7ff52dc12c24fa5abba88785269dc5d9 + md5: 7c08afb0f02d5673de8e4f6f535663a8 + sha256: b9c3eec0f102b04d893911be6761f13f653d02b12f55fd5a108959903fbac8ab manager: conda name: tornado optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/tornado-6.2-py310h5764c6d_1.tar.bz2 - version: '6.2' + url: https://conda.anaconda.org/conda-forge/linux-64/tornado-6.3-py310h1fa729e_0.conda + version: '6.3' - category: main dependencies: python: '>=3.6' hash: - md5: a4d6202101f04b76d545530728e696bf - sha256: 8e490e1d390be0ab59b538199b4cedec027c68ebaa3add554a6316a79d5a1dbe + md5: 2010a97e7298197221abc6295790ff62 + sha256: 5fb56cd0652e7cffc1141c66b09644f1dde588ef6dddcb47849a62d7b0186846 manager: conda name: types-pytz optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/types-pytz-2022.7.1.2-pyhd8ed1ab_0.conda - version: 2022.7.1.2 + url: https://conda.anaconda.org/conda-forge/noarch/types-pytz-2023.3.0.0-pyhd8ed1ab_0.conda + version: 2023.3.0.0 - category: main dependencies: python: '>=3.6' hash: - md5: d398b385822d9425fb21c6c8f89dbc9e - sha256: 32233b8d558c118b9d856c6b7e52499c36b9f867bbf76b5c8b7edfb7655230cf + md5: 0c0c5edec27d8284bf75023737f74823 + sha256: 10290d04934693214ea9a3caaefac35c3fdfc72094ffa8b0f063141bef469bbe manager: conda name: types-pyyaml optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/types-pyyaml-6.0.12.8-pyhd8ed1ab_0.conda - version: 6.0.12.8 + url: https://conda.anaconda.org/conda-forge/noarch/types-pyyaml-6.0.12.9-pyhd8ed1ab_0.conda + version: 6.0.12.9 - category: main dependencies: python: '>=3.6' hash: - md5: 617bb6391b4b676f9b062aff31ef978d - sha256: 17f157579b6f0e9c2ef56e3d9c74eef625717865f8503101317cedc69f059b46 + md5: 8b7a7a28f8a274b98f0387c13c56c94c + sha256: e07d313a9c7aa2dfe425ca5a3bdc65cd015a8819cda8e576edb3b3a47535da1a manager: conda name: types-urllib3 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/types-urllib3-1.26.25.8-pyhd8ed1ab_0.conda - version: 1.26.25.8 -- category: main - dependencies: - python: '>=3' - hash: - md5: e6573ac68718f17b9d4f5c8eda3190f2 - sha256: ec1cfe0b7dc55a22223562cad799e0b16d122dab611c9923b6068d27a784ba2f - manager: conda - name: typing - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/typing-3.10.0.0-pyhd8ed1ab_0.tar.bz2 - version: 3.10.0.0 + url: https://conda.anaconda.org/conda-forge/noarch/types-urllib3-1.26.25.12-pyhd8ed1ab_0.conda + version: 1.26.25.12 - category: main dependencies: python: '>=3.7' @@ -3207,36 +3255,19 @@ package: gxx_impl_linux-64: '' libgcc-ng: '>=12' libstdcxx-ng: '>=12' - libzlib: '>=1.2.12,<1.3.0a0' + libzlib: '>=1.2.13,<1.3.0a0' make: '' perl: '' + python: '' hash: - md5: 41af6df1758bae89161daf268566384e - sha256: e2f2302d69c0d6928d95a1c699b5ef0b14e0243e78495734962c78136d2e6b9f + md5: efb0e7909f1a41159856e688e216bd26 + sha256: c24f5fc704ee3c0737456e7a4b8f75114b25a51812c6f801a22ed43652e0b211 manager: conda name: verilator optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/verilator-4.226-he0ac6c6_1.tar.bz2 - version: '4.226' -- category: main - dependencies: - gettext: '>=0.21.1,<1.0a0' - libgcc-ng: '>=12' - libstdcxx-ng: '>=12' - ncurses: '>=6.3,<7.0a0' - perl: '>=5.32.1,<5.33.0a0 *_perl5' - python: '>=3.10,<3.11.0a0' - python_abi: 3.10.* *_cp310 - hash: - md5: 7cd55a1679e39c90e105c216d12af54b - sha256: fc189bde7d79ec70de87f176756b6cc04d9008c3e0de5d66f8832f7f9c85274c - manager: conda - name: vim - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/vim-9.0.0814-py310pl5321hade1898_0.tar.bz2 - version: 9.0.0814 + url: https://conda.anaconda.org/conda-forge/linux-64/verilator-5.008-h514fc35_1.conda + version: '5.008' - category: main dependencies: python: '' @@ -3261,18 +3292,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/websocket-client-1.5.1-pyhd8ed1ab_0.conda version: 1.5.1 -- category: main - dependencies: - python: '>=3.7' - hash: - md5: 6dfc61103f2c33a6c875b93d82875c10 - sha256: 3e08e7a72a01fa53e4d2e2dedde32b3300dc9d12c91d7b5248d458ecfa0bd439 - manager: conda - name: werkzeug - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/werkzeug-2.1.2-pyhd8ed1ab_1.tar.bz2 - version: 2.1.2 - category: main dependencies: python: '>=3.7' @@ -3353,6 +3372,23 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libxrender-0.9.10-h7f98852_1003.tar.bz2 version: 0.9.10 +- category: main + dependencies: + libgcc-ng: '>=9.3.0' + xorg-kbproto: '' + xorg-libice: 1.0.* + xorg-libsm: 1.2.* + xorg-libx11: '>=1.7.0,<2.0a0' + xorg-xproto: '' + hash: + md5: 60d6eec5273f1c9af096c10c268912e3 + sha256: 25bfc4d86df3498b88aac2f02ecf65e739bf99a687805c31a635df6f2e60a163 + manager: conda + name: xorg-libxt + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/xorg-libxt-1.2.1-h7f98852_2.tar.bz2 + version: 1.2.1 - category: main dependencies: python: '>=3.7' @@ -3365,19 +3401,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/zipp-3.15.0-pyhd8ed1ab_0.conda version: 3.15.0 -- category: main - dependencies: - python: '>=3.6' - typing_extensions: '>=4.0' - hash: - md5: 59c40397276a286241c65faec5e1be3c - sha256: be2dbd6710438fa48b83bf06841091227276ae545d145dfe5cb5149c6484e951 - manager: conda - name: aioitertools - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/aioitertools-0.11.0-pyhd8ed1ab_0.tar.bz2 - version: 0.11.0 - category: main dependencies: frozenlist: '>=1.1.0' @@ -3406,30 +3429,30 @@ package: version: 2.12.1 - category: main dependencies: - fontconfig: '>=2.13.96,<3.0a0' + fontconfig: '>=2.14.2,<3.0a0' fonts-conda-ecosystem: '' freetype: '>=2.12.1,<3.0a0' - icu: '>=70.1,<71.0a0' + icu: '>=72.1,<73.0a0' libgcc-ng: '>=12' - libglib: '>=2.72.1,<3.0a0' - libpng: '>=1.6.38,<1.7.0a0' + libglib: '>=2.74.1,<3.0a0' + libpng: '>=1.6.39,<1.7.0a0' libxcb: '>=1.13,<1.14.0a0' - libzlib: '>=1.2.12,<1.3.0a0' + libzlib: '>=1.2.13,<1.3.0a0' pixman: '>=0.40.0,<1.0a0' xorg-libice: '' xorg-libsm: '' - xorg-libx11: '' - xorg-libxext: '' + xorg-libx11: '>=1.8.4,<2.0a0' + xorg-libxext: '>=1.3.4,<2.0a0' xorg-libxrender: '' - zlib: '>=1.2.12,<1.3.0a0' + zlib: '' hash: - md5: d1a88f3ed5b52e1024b80d4bcd26a7a0 - sha256: f062cf56e6e50d3ad4b425ebb3765ca9138c6ebc52e6a42d1377de8bc8d954f6 + md5: 0c944213e40c9e4aa32292776b9c6903 + sha256: 0be3064cb30e3e69a47370abae85b2780cd81fbca00cbd17076d40c0f6302fdb manager: conda name: cairo optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/cairo-1.16.0-ha61ee94_1014.tar.bz2 + url: https://conda.anaconda.org/conda-forge/linux-64/cairo-1.16.0-h35add3b_1015.conda version: 1.16.0 - category: main dependencies: @@ -3449,20 +3472,19 @@ package: version: 1.15.1 - category: main dependencies: - libclang-cpp15: '>=15.0.7,<15.1.0a0' + libclang-cpp16: '>=16.0.3,<16.1.0a0' libgcc-ng: '>=12' - libllvm15: '>=15.0.7,<15.1.0a0' + libllvm16: '>=16.0.3,<16.1.0a0' libstdcxx-ng: '>=12' - libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: d2fcc7c0381194ca6fcb38a6d06255b8 - sha256: eee53b98b40099c9289a732f6c915f9c80714d8a7a8a977f921c0782c6f5200f + md5: 14a18f87f492a905cee3d833eae4e86b + sha256: 0896316dbdcd3dca118c61127b2d79cc0c0bdb08f869cff9f35fe2c5a4673555 manager: conda - name: clang-format-15 + name: clang-format-16 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/clang-format-15-15.0.7-default_had23c3d_1.conda - version: 15.0.7 + url: https://conda.anaconda.org/conda-forge/linux-64/clang-format-16-16.0.3-default_h83cc7fd_0.conda + version: 16.0.3 - category: main dependencies: click: '' @@ -3493,8 +3515,9 @@ package: - category: main dependencies: bzip2: '>=1.0.8,<2.0a0' - expat: '>=2.5.0,<3.0a0' - libcurl: '>=7.88.1,<8.0a0' + expat: '' + libcurl: '>=7.88.1,<9.0a0' + libexpat: '>=2.5.0,<3.0a0' libgcc-ng: '>=12' libstdcxx-ng: '>=12' libuv: '' @@ -3505,14 +3528,14 @@ package: zlib: '' zstd: '>=1.5.2,<1.6.0a0' hash: - md5: 02142080aee43c8ef90db543ffbc13dd - sha256: cbd17c0375a021b7de854e0841f3f1b28b1359bc52bdc0ba5aabaee0f65a0b7d + md5: 6edec767268ad8451d27bb65f38c7ea4 + sha256: 3bb9d7c35d5297d85516769eb0517c83f7fc2ed7ab944a8c028871bb375bed51 manager: conda name: cmake optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/cmake-3.26.0-h077f3f9_0.conda - version: 3.26.0 + url: https://conda.anaconda.org/conda-forge/linux-64/cmake-3.26.3-h077f3f9_0.conda + version: 3.26.3 - category: main dependencies: libgcc-ng: '>=12' @@ -3565,7 +3588,7 @@ package: dependencies: bzip2: '>=1.0.8,<2.0a0' libarchive: '>=3.5.2,<3.6.0a0' - libcurl: '>=7.82.0,<8.0a0' + libcurl: '>=7.82.0,<9.0a0' libgcc-ng: '>=10.3.0' libmicrohttpd: '>=0.9.75,<0.10.0a0' libstdcxx-ng: '>=10.3.0' @@ -3591,14 +3614,14 @@ package: python_abi: 3.10.* *_cp310 unicodedata2: '>=14.0.0' hash: - md5: 3b354798e12b65fa8ebe1d189de6a507 - sha256: 20b42570005cd3f6d961efa3ac1e389ef763a94224406a6f33121824390f5b71 + md5: 4f39f656d6ff2761d698e69af952be82 + sha256: 9c3765958a18d9bfc33e42d78a554aff00041d3da474db3045d6ce95ef6a4643 manager: conda name: fonttools optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/fonttools-4.39.2-py310h1fa729e_0.conda - version: 4.39.2 + url: https://conda.anaconda.org/conda-forge/linux-64/fonttools-4.39.3-py310h1fa729e_0.conda + version: 4.39.3 - category: main dependencies: python: '>=3.4' @@ -3644,14 +3667,14 @@ package: python: '>=3.8' zipp: '>=0.5' hash: - md5: 30b3127c385ca2ed5ef87f3d53d466bc - sha256: 4fe127138487a2aa171862407605f0cd601d005f85e0eee7f38c770b407e4145 + md5: f91a5d5175fb7ff2a91952ec7da59cb9 + sha256: 33d49065756a73fbb92277c756fa00a41891408528eb90ae05ff3367a401ae6e manager: conda name: importlib-metadata optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-6.1.0-pyha770c72_0.conda - version: 6.1.0 + url: https://conda.anaconda.org/conda-forge/noarch/importlib-metadata-6.6.0-pyha770c72_0.conda + version: 6.6.0 - category: main dependencies: more-itertools: '' @@ -3704,45 +3727,29 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/junit-xml-1.9-pyh9f0ad1d_0.tar.bz2 version: '1.9' -- category: main - dependencies: - libclang13: 15.0.7 default_h3e3d535_1 - libgcc-ng: '>=12' - libllvm15: '>=15.0.7,<15.1.0a0' - libstdcxx-ng: '>=12' - libzlib: '>=1.2.13,<1.3.0a0' - hash: - md5: 36c65ed73b7c92589bd9562ef8a6023d - sha256: eba3ed760c72c992a04d86455556ecb90c0e1e3688defcac44b28a848d71651c - manager: conda - name: libclang - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libclang-15.0.7-default_had23c3d_1.conda - version: 15.0.7 - category: main dependencies: expat: '>=2.5.0,<3.0a0' - fontconfig: '>=2.14.1,<3.0a0' + fontconfig: '>=2.14.2,<3.0a0' fonts-conda-ecosystem: '' freetype: '>=2.12.1,<3.0a0' - icu: '>=70.1,<71.0a0' - jpeg: '>=9e,<10a' + icu: '>=72.1,<73.0a0' libgcc-ng: '>=12' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libpng: '>=1.6.39,<1.7.0a0' libtiff: '>=4.5.0,<4.6.0a0' libwebp: '' - libwebp-base: '>=1.2.4,<2.0a0' + libwebp-base: '>=1.3.0,<2.0a0' libzlib: '>=1.2.13,<1.3.0a0' zlib: '' hash: - md5: 82ef57611ace65b59db35a9687264572 - sha256: 6674781023188deeda7752e5dc429a54fd1639c9d61cbb25296cbbb55367884a + md5: ef06bee47510a7f5db3c2297a51d6ce2 + sha256: 6335db21afc72f86cf4ee0298acde3af950087db2b24df3d28a81c7d24574244 manager: conda name: libgd optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libgd-2.3.3-h5aea950_4.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libgd-2.3.3-hfa28ad5_6.conda version: 2.3.3 - category: main dependencies: @@ -3769,14 +3776,14 @@ package: tomli: '>=1.1.0' typing_extensions: '>=3.10' hash: - md5: 7f519094ddab6b939cf6dae229c3b17b - sha256: d58fd7f0c34995d5dd829eff8b4261e782b65a6bb50f072919f0d0002fd35a77 + md5: 7696ac5b7bc40cd66e483f16ee652243 + sha256: 20901dc450437d7e583c1c8e63321bdaf105e6703a41f9d3a6d5551a0707bcfc manager: conda name: mypy optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/mypy-1.1.1-py310h1fa729e_0.conda - version: 1.1.1 + url: https://conda.anaconda.org/conda-forge/linux-64/mypy-1.2.0-py310h1fa729e_0.conda + version: 1.2.0 - category: main dependencies: python: 2.7|>=3.7 @@ -3793,11 +3800,11 @@ package: - category: main dependencies: freetype: '>=2.12.1,<3.0a0' - jpeg: '>=9e,<10a' - lcms2: '>=2.14,<3.0a0' + lcms2: '>=2.15,<3.0a0' libgcc-ng: '>=12' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libtiff: '>=4.5.0,<4.6.0a0' - libwebp-base: '>=1.2.4,<2.0a0' + libwebp-base: '>=1.3.0,<2.0a0' libxcb: '>=1.13,<1.14.0a0' libzlib: '>=1.2.13,<1.3.0a0' openjpeg: '>=2.5.0,<3.0a0' @@ -3805,60 +3812,28 @@ package: python_abi: 3.10.* *_cp310 tk: '>=8.6.12,<8.7.0a0' hash: - md5: bbea829b541aa15df5c65bd40b8c1981 - sha256: 6d17af4c8bc8d8668d033725dd4691cfac86fdf0f46f655ab6f5df3e3ae0bb7c + md5: 58ea77873883be5b59328e29ca50997e + sha256: ca081b2a1af2dcab802dece28ac1a95e873c9ee278bbd50a5c2882b621dd0d99 manager: conda name: pillow optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/pillow-9.4.0-py310h023d228_1.conda - version: 9.4.0 + url: https://conda.anaconda.org/conda-forge/linux-64/pillow-9.5.0-py310h065c6d2_0.conda + version: 9.5.0 - category: main dependencies: python: '>=3.7' setuptools: '' wheel: '' hash: - md5: 8025ca83b8ba5430b640b83917c2a6f7 - sha256: e1698cbf4964cd60a2885c0edbc654133cd0db5ac4cb568412250e577dbc42ad + md5: 7288da0d36821349cf1126e8670292df + sha256: 4fe1f47f6eac5b2635a622b6f985640bf835843c1d8d7ccbbae0f7d27cadec92 manager: conda name: pip optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pip-23.0.1-pyhd8ed1ab_0.conda - version: 23.0.1 -- category: main - dependencies: - python: '>=3.6' - setuptools: '' - hash: - md5: c78cd16b11cd6a295484bd6c8f24bea1 - sha256: e8710e24f60b6a97289468f47914e53610101755088bc237621cc1980edbfcd9 - manager: conda - name: pygments - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pygments-2.14.0-pyhd8ed1ab_0.conda - version: 2.14.0 -- category: main - dependencies: - attrs: '>=19.2.0' - colorama: '' - exceptiongroup: '' - iniconfig: '' - packaging: '' - pluggy: '>=0.12,<2.0' - python: '>=3.8' - tomli: '>=1.0.0' - hash: - md5: 60958b19354e0ec295b43f6ab5cfab86 - sha256: d074ef1e2ffc3334927c281e4b79aebfa8eefd2d1588c3830a45ba4bce3e6ea9 - manager: conda - name: pytest - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pytest-7.2.2-pyhd8ed1ab_0.conda - version: 7.2.2 + url: https://conda.anaconda.org/conda-forge/noarch/pip-23.1.2-pyhd8ed1ab_0.conda + version: 23.1.2 - category: main dependencies: python: '>=3.6' @@ -3912,27 +3887,14 @@ package: ruamel.yaml.clib: '>=0.1.2' setuptools: '' hash: - md5: 97204ae92b703d74a983db0e6d07d009 - sha256: 2e390037976718f762b8db6703aadeb950fe4c409c64a7e5985157cbb2d58d52 + md5: 475a6b5d3a01fc0d7d494ccd94db0b1d + sha256: 90ea9bbd357fa206ac07623f57d990adb318a43bc402a85d31bcb907552e2b5e manager: conda name: ruamel.yaml optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml-0.17.21-py310h1fa729e_3.conda - version: 0.17.21 -- category: main - dependencies: - python: '>=3.6' - typing: '>=3.6,<4.0' - hash: - md5: 471bf9e605820b59988e830382b8d654 - sha256: e8b3bc2203266636740ce10536ef951c52b53b43bfed3b938117547efc47e374 - manager: conda - name: tomlkit - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/tomlkit-0.11.6-pyha770c72_0.tar.bz2 - version: 0.11.6 + url: https://conda.anaconda.org/conda-forge/linux-64/ruamel.yaml-0.17.25-py310h2372a71_0.conda + version: 0.17.25 - category: main dependencies: colorama: '' @@ -3951,14 +3913,14 @@ package: python: '>=3.6' types-urllib3: <1.27 hash: - md5: 35221b6d2f75276b786fb53fac5c4c35 - sha256: 54b0949b6fcdbdc36474dd3403a926b55331de6c1ea543c1d87f444f7fa8702a + md5: 1ab2e9a47f24fac257f88956828f1956 + sha256: 19d2affb4d3fab4d1d60eb3748b2d80b9ff2983c9b196e74aae7a0dc03fe74d8 manager: conda name: types-requests optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/types-requests-2.28.11.15-pyhd8ed1ab_0.conda - version: 2.28.11.15 + url: https://conda.anaconda.org/conda-forge/noarch/types-requests-2.30.0.0-pyhd8ed1ab_0.conda + version: 2.30.0.0 - category: main dependencies: typing_extensions: 4.5.0 pyha770c72_0 @@ -3971,6 +3933,39 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/typing-extensions-4.5.0-hd8ed1ab_0.conda version: 4.5.0 +- category: main + dependencies: + gettext: '>=0.21.1,<1.0a0' + libgcc-ng: '>=12' + libstdcxx-ng: '>=12' + ncurses: '>=6.3,<7.0a0' + perl: '>=5.32.1,<5.33.0a0 *_perl5' + python: '>=3.10,<3.11.0a0' + python_abi: 3.10.* *_cp310 + xorg-libx11: '>=1.8.4,<2.0a0' + xorg-libxt: '' + hash: + md5: e7f0a31678b40de1586967a9087cca8b + sha256: f996584fc8c85e11d9caf7554b0c857060498e5dc6ba608d0551b14b67ccaa1d + manager: conda + name: vim + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/vim-9.0.1425-py310pl5321he660f0e_0.conda + version: 9.0.1425 +- category: main + dependencies: + markupsafe: '>=2.1.1' + python: '>=3.8' + hash: + md5: 23ddbe41ab0115bc0bfb75dcbf5de7cf + sha256: 2df1970270839b36e13a4ba7e4b393cfa95aa1d7438909aa8c3db14170ea207c + manager: conda + name: werkzeug + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/werkzeug-2.3.4-pyhd8ed1ab_0.conda + version: 2.3.4 - category: main dependencies: libgcc-ng: '>=9.3.0' @@ -3995,14 +3990,14 @@ package: python: '>=3.10,<3.11.0a0' python_abi: 3.10.* *_cp310 hash: - md5: a88cda17074955bdb5e93b8e3be59e7d - sha256: eb7fd99bf87e0d150ee6946479172688ded1c4fb51382ad27be5da217cd8815b + md5: e8ede9a6fedf3e0e640e810749b4cb6e + sha256: d56b21d563c673023561a4e83e9f5731441ce2bce80ca5cfe55cfa8bfa5d5eb1 manager: conda name: yarl optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/yarl-1.8.2-py310h5764c6d_0.conda - version: 1.8.2 + url: https://conda.anaconda.org/conda-forge/linux-64/yarl-1.9.1-py310h2372a71_0.conda + version: 1.9.1 - category: main dependencies: python: '>=3.6' @@ -4050,37 +4045,36 @@ package: version: 0.7.0 - category: main dependencies: - clang-format-15: 15.0.7 default_had23c3d_1 - libclang-cpp15: '>=15.0.7,<15.1.0a0' + clang-format-16: 16.0.3 default_h83cc7fd_0 + libclang-cpp16: '>=16.0.3,<16.1.0a0' libgcc-ng: '>=12' - libllvm15: '>=15.0.7,<15.1.0a0' + libllvm16: '>=16.0.3,<16.1.0a0' libstdcxx-ng: '>=12' - libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: 841d93c086f15b68916b3455711c2638 - sha256: 517c759576600decafd005b14f3df9660b525fdb85645a0c588ea979b62bdc5e + md5: a1f13606e670bdaaee724536218f5c40 + sha256: 5eb61124b6f96015aee46217f081953cb4efee9f9d39ac7c98e76d734f384693 manager: conda name: clang-format optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/clang-format-15.0.7-default_had23c3d_1.conda - version: 15.0.7 + url: https://conda.anaconda.org/conda-forge/linux-64/clang-format-16.0.3-default_h83cc7fd_0.conda + version: 16.0.3 - category: main dependencies: cffi: '>=1.12' libgcc-ng: '>=12' - openssl: '>=3.0.8,<4.0a0' + openssl: '>=3.1.0,<4.0a0' python: '>=3.10,<3.11.0a0' python_abi: 3.10.* *_cp310 hash: - md5: 99dc5a02a8b16cd88ca9a12354496e78 - sha256: 23d3015849c45febab3085ecf2cc193c0966c1e2348756722b776f1cedea8596 + md5: 991a12eccbca3c9897c62f44b1104a54 + sha256: 692b0394bb3104ec117faa0130d67109a0132e9bd57084ebfde81fc2b9790e58 manager: conda name: cryptography optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/cryptography-39.0.2-py310h34c0648_0.conda - version: 39.0.2 + url: https://conda.anaconda.org/conda-forge/linux-64/cryptography-40.0.2-py310h34c0648_0.conda + version: 40.0.2 - category: main dependencies: cloudpickle: '' @@ -4097,41 +4091,42 @@ package: version: 0.36.0 - category: main dependencies: - click: '>=8.0' + blinker: '>=1.6.2' + click: '>=8.1.3' importlib-metadata: '>=3.6.0' - itsdangerous: '>=2.0' - jinja2: '>=3.0' - python: '>=3.7' - werkzeug: '>=2.0' + itsdangerous: '>=2.1.2' + jinja2: '>=3.1.2' + python: '>=3.8' + werkzeug: '>=2.3.3' hash: - md5: 4b95b1c750d6d737905cdb447f097b9c - sha256: de8f2eb0b86e28b672839ae4ad0032eda30e09fee28a19b79159b35673f25a42 + md5: 816d75d4c0f2e41b5765d17498c57a2e + sha256: f93246be286f2d0f93e85c4f08f9ce48f3eed875a79225e2ea119e70c0237421 manager: conda name: flask optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/flask-2.1.3-pyhd8ed1ab_0.tar.bz2 - version: 2.1.3 + url: https://conda.anaconda.org/conda-forge/noarch/flask-2.3.2-pyhd8ed1ab_0.conda + version: 2.3.2 - category: main dependencies: curl: '' - expat: '>=2.5.0,<3.0a0' gettext: '' + libexpat: '>=2.5.0,<3.0a0' libgcc-ng: '>=12' libiconv: '>=1.17,<2.0a0' libzlib: '>=1.2.13,<1.3.0a0' - openssl: '>=3.0.8,<4.0a0' + openssl: '>=3.1.0,<4.0a0' pcre2: '>=10.40,<10.41.0a0' perl: 5.* hash: - md5: 70fd89375d9b5ca90c15dcf3662b1b42 - sha256: fba1e93848c20e29d205726142fb37ad7e2be785699f98aac348524080354f6d + md5: 0cb5ff348eb4c201b3b920eff851675d + sha256: 528c9fdaf799b38611276d6f676da6018da2aaf93fb5b0328c00923909e99432 manager: conda name: git optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/git-2.40.0-pl5321h693f4a3_0.conda - version: 2.40.0 + url: https://conda.anaconda.org/conda-forge/linux-64/git-2.40.1-pl5321h86e50cf_0.conda + version: 2.40.1 - category: main dependencies: gitdb: '>=4.0.1,<5' @@ -4151,31 +4146,31 @@ package: cairo: '>=1.16.0,<2.0a0' freetype: '>=2.12.1,<3.0a0' graphite2: '' - icu: '>=70.1,<71.0a0' + icu: '>=72.1,<73.0a0' libgcc-ng: '>=12' libglib: '>=2.74.1,<3.0a0' libstdcxx-ng: '>=12' hash: - md5: 448fe40d2fed88ccf4d9ded37cbb2b38 - sha256: f300fcb390253d6d63346ee71e56f82bc830783d1682ac933fe9ac86f39da942 + md5: 73d2c2d25fdcec40c24929bab9f44831 + sha256: d4bf8a3e23478efefe39ac2d965f44b55cee4058277f2ad7478384e7973fc97f manager: conda name: harfbuzz optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/harfbuzz-6.0.0-h8e241bc_0.conda + url: https://conda.anaconda.org/conda-forge/linux-64/harfbuzz-6.0.0-h3ff4399_1.conda version: 6.0.0 - category: main dependencies: - importlib-metadata: '>=6.1.0,<6.1.1.0a0' + importlib-metadata: '>=6.6.0,<6.6.1.0a0' hash: - md5: 90bab1d97fdb6bb40c8e00207bf222dc - sha256: 80a10ad1bacf5bb85d497fd3e5629f5805b6e90ad8c8b923daa3e36729e7429a + md5: 3cbc9615f10a3d471532b83e4250b971 + sha256: 5de35d3c019d8a36e0a0deeb04a62689837bd68234a0a73a3355b860b442eca4 manager: conda name: importlib_metadata optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/importlib_metadata-6.1.0-hd8ed1ab_0.conda - version: 6.1.0 + url: https://conda.anaconda.org/conda-forge/noarch/importlib_metadata-6.6.0-hd8ed1ab_0.conda + version: 6.6.0 - category: main dependencies: attrs: '>=17.4.0' @@ -4240,17 +4235,18 @@ package: numpy: '>=1.21.6,<2.0a0' python: '>=3.10,<3.11.0a0' python-dateutil: '>=2.8.1' + python-tzdata: '>=2022a' python_abi: 3.10.* *_cp310 pytz: '>=2020.1' hash: - md5: 467244b0dbb7da40927ac6ee0e9491de - sha256: 289bdc902fb8c536d8fe1297fdc97bb17f01a9b19ad15d96fc8ba0dbe239a379 + md5: 25fc16ee9a1df69e91c8213530f2cc8c + sha256: 4af68421353f552c6d321bfc8b76040eaa89fa35c0a7854be8acaddf154be63e manager: conda name: pandas optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/pandas-1.5.3-py310h9b08913_0.conda - version: 1.5.3 + url: https://conda.anaconda.org/conda-forge/linux-64/pandas-2.0.1-py310h7cbd5c2_1.conda + version: 2.0.1 - category: main dependencies: pip: '' @@ -4267,16 +4263,16 @@ package: - category: main dependencies: python: '>=3.7' - typing-extensions: '>=4.4' + typing-extensions: '>=4.5' hash: - md5: 1d1a27f637808c76dd83e3f469aa6f7e - sha256: 5875ef7f4b079fe080c10287b13843860bc69a42e457729a8c5dc32cb3563e92 + md5: 6c36f1c42dd0069b7f23acc74f19be46 + sha256: e6d247b9a645ac6a2e4909cbe9cfad5cf9ba1a2f4352fee7aac3acb640371a54 manager: conda name: platformdirs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/platformdirs-3.1.1-pyhd8ed1ab_0.conda - version: 3.1.1 + url: https://conda.anaconda.org/conda-forge/noarch/platformdirs-3.5.0-pyhd8ed1ab_0.conda + version: 3.5.0 - category: main dependencies: libgcc-ng: '>=12' @@ -4284,14 +4280,14 @@ package: python_abi: 3.10.* *_cp310 typing-extensions: '>=4.2.0' hash: - md5: d84eeeb2a7ef8ef996bb6acdb5ecdeb6 - sha256: 8ea1a03876dcf6432acd88f15cdb64bf4f985ea54599adef552f376cf68cf7a7 + md5: 6306ca76bc0635d84940349cf8d96264 + sha256: b0d9edaba389b3714bbc59266cfe7e7fef9c7f0bc664f455026455c998129b30 manager: conda name: pydantic optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/pydantic-1.10.6-py310h1fa729e_0.conda - version: 1.10.6 + url: https://conda.anaconda.org/conda-forge/linux-64/pydantic-1.10.7-py310h1fa729e_0.conda + version: 1.10.7 - category: main dependencies: cffi: '>=1.4.1' @@ -4311,43 +4307,36 @@ package: version: 1.5.0 - category: main dependencies: - pytest: '>=3.6.0' - python: '' + colorama: '' + exceptiongroup: '' + importlib-metadata: '>=0.12' + iniconfig: '' + packaging: '' + pluggy: '>=0.12,<2.0' + python: '>=3.8' + tomli: '>=1.0.0' hash: - md5: b6764e23dece9f9cda0469af044fafeb - sha256: bdb25a7daf3efb7255b1a19d7b5d41d7d4d96bc647b8e5f7407ec4dd9e384257 + md5: 547c7de697ec99b494a28ddde185b5a4 + sha256: 42f89db577266b9dc195d09189b92f3af3354fb50c98b1f996c580322dffa8b5 manager: conda - name: pytest-dependency + name: pytest optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pytest-dependency-0.5.1-pyh9f0ad1d_0.tar.bz2 - version: 0.5.1 -- category: main - dependencies: - pytest: '>=5.0' - python: '>=3.7' - hash: - md5: db93caa9fe182f0cd20291aeb22f57ac - sha256: 87bb8edc9976403237a0e6c3bd7b2224c346c95e4c7345971f411aef21593450 - manager: conda - name: pytest-mock - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pytest-mock-3.10.0-pyhd8ed1ab_0.tar.bz2 - version: 3.10.0 + url: https://conda.anaconda.org/conda-forge/noarch/pytest-7.3.1-pyhd8ed1ab_0.conda + version: 7.3.1 - category: main dependencies: pip: '' python: '>=3.7,<4.0' hash: - md5: 25923bf9620c56f8bc0d4923d870edd8 - sha256: 3f8be46ba1cbd8533d25eba1a5b32062bb9231b16e308bbbc92b5e32177cbdad + md5: 8462b4f53fa7d7dc057a26d589ec71de + sha256: dc2928817ff89e3628f82f3cedd4369c84d7079d04493b33dc67e4288d1de35d manager: conda name: types-awscrt optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/types-awscrt-0.16.13-pyhd8ed1ab_0.conda - version: 0.16.13 + url: https://conda.anaconda.org/conda-forge/noarch/types-awscrt-0.16.17-pyhd8ed1ab_0.conda + version: 0.16.17 - category: main dependencies: cffi: '' @@ -4424,32 +4413,31 @@ package: types-awscrt: '' typing_extensions: '' hash: - md5: 96971bc5cc944a1743fdde0634e55480 - sha256: fee2b0596dd34a70081d745e06f9302dd06fb56dd366e51a302f93c9764126d9 + md5: 01961f718d29cabd188e863a61d8fd81 + sha256: 1fc8f40eb33d7e38590d88d847fb39329628c31269c8a2e5aaab7d51cc5b501f manager: conda name: botocore-stubs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.29.94-pyhd8ed1ab_0.conda - version: 1.29.94 + url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.29.129-pyhd8ed1ab_0.conda + version: 1.29.129 - category: main dependencies: - clang-format: 15.0.7 default_had23c3d_1 - libclang: '>=15.0.7,<15.1.0a0' - libclang-cpp15: '>=15.0.7,<15.1.0a0' + clang-format: 16.0.3 default_h83cc7fd_0 + libclang-cpp16: '>=16.0.3,<16.1.0a0' + libclang13: '>=16.0.3' libgcc-ng: '>=12' - libllvm15: '>=15.0.7,<15.1.0a0' + libllvm16: '>=16.0.3,<16.1.0a0' libstdcxx-ng: '>=12' - libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: c23e2b0154fb2eb92442fa8ecbcf571c - sha256: d9931c1ce5907073de0269666881309cc896267723f38ef269101bd211e49062 + md5: ceedc73b354682b0d63d61d654ebcd33 + sha256: b5ea9bef3e3316c34bfbde0a3a50cb53a2bf2db89221c9b145d37fc1e5c89576 manager: conda name: clang-tools optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/clang-tools-15.0.7-default_had23c3d_1.conda - version: 15.0.7 + url: https://conda.anaconda.org/conda-forge/linux-64/clang-tools-16.0.3-default_h83cc7fd_0.conda + version: 16.0.3 - category: main dependencies: python: '>=3.7' @@ -4482,14 +4470,14 @@ package: python: '>=3.6' ukkonen: '' hash: - md5: b5ada314668cded097e08fea86262317 - sha256: 88bcba64d462867b5759e29784cf24685e1e49fffea75452b94d438d6bd9587c + md5: a4085ab0562d5081a9333435837b538a + sha256: 4027103c59220a68b41aed056d2ce89d46e4971033d259293ca07198a8a81fdc manager: conda name: identify optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/identify-2.5.21-pyhd8ed1ab_0.conda - version: 2.5.21 + url: https://conda.anaconda.org/conda-forge/noarch/identify-2.5.24-pyhd8ed1ab_0.conda + version: 2.5.24 - category: main dependencies: importlib_metadata: '' @@ -4533,31 +4521,31 @@ package: - category: main dependencies: alsa-lib: '>=1.2.8,<1.2.9.0a0' - fontconfig: '>=2.14.1,<3.0a0' + fontconfig: '>=2.14.2,<3.0a0' fonts-conda-ecosystem: '' freetype: '>=2.12.1,<3.0a0' giflib: '>=5.2.1,<5.3.0a0' harfbuzz: '>=6.0.0,<7.0a0' - jpeg: '>=9e,<10a' - lcms2: '>=2.14,<3.0a0' + lcms2: '>=2.15,<3.0a0' libcups: '>=2.3.3,<2.4.0a0' libgcc-ng: '>=12' + libjpeg-turbo: '>=2.1.5.1,<3.0a0' libpng: '>=1.6.39,<1.7.0a0' libstdcxx-ng: '>=12' libzlib: '>=1.2.13,<1.3.0a0' - xorg-libx11: '' - xorg-libxext: '' + xorg-libx11: '>=1.8.4,<2.0a0' + xorg-libxext: '>=1.3.4,<2.0a0' xorg-libxi: '' xorg-libxrender: '' xorg-libxtst: '' hash: - md5: 71a5dfe4a375fc43497cdc6f4aedff9d - sha256: baa527e6b59572e00e68c2362e1771f7741f3f062dac7a8c6365a97f48c04413 + md5: 33527b036cd6d369be12fd772cdd49e4 + sha256: 221de13214f051654177dd331c019a889ab1bbe3b2cf30d5cf17596378740359 manager: conda name: openjdk optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/openjdk-17.0.3-h58dac75_5.conda + url: https://conda.anaconda.org/conda-forge/linux-64/openjdk-17.0.3-h4335b31_6.conda version: 17.0.3 - category: main dependencies: @@ -4596,17 +4584,43 @@ package: version: 3.1.0 - category: main dependencies: - cryptography: '>=38.0.0,<40' + cryptography: '>=38.0.0,<41' python: '>=3.6' hash: - md5: d41957700e83bbb925928764cb7f8878 - sha256: adbf8951f22bfa950b9e24394df1ef1d2b2d7dfb194d91c7f42bc11900695785 + md5: 0b34aa3ab7e7ccb1765a03dd9ed29938 + sha256: 458428cb867f70f2af2a4ed59d382291ea3eb3f10490196070a15d1d71d5432a manager: conda name: pyopenssl optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pyopenssl-23.0.0-pyhd8ed1ab_0.conda - version: 23.0.0 + url: https://conda.anaconda.org/conda-forge/noarch/pyopenssl-23.1.1-pyhd8ed1ab_0.conda + version: 23.1.1 +- category: main + dependencies: + pytest: '>=3.6.0' + python: '' + hash: + md5: b6764e23dece9f9cda0469af044fafeb + sha256: bdb25a7daf3efb7255b1a19d7b5d41d7d4d96bc647b8e5f7407ec4dd9e384257 + manager: conda + name: pytest-dependency + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/pytest-dependency-0.5.1-pyh9f0ad1d_0.tar.bz2 + version: 0.5.1 +- category: main + dependencies: + pytest: '>=5.0' + python: '>=3.7' + hash: + md5: db93caa9fe182f0cd20291aeb22f57ac + sha256: 87bb8edc9976403237a0e6c3bd7b2224c346c95e4c7345971f411aef21593450 + manager: conda + name: pytest-mock + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/pytest-mock-3.10.0-pyhd8ed1ab_0.tar.bz2 + version: 3.10.0 - category: main dependencies: cryptography: '' @@ -4670,19 +4684,18 @@ package: - category: main dependencies: distlib: <1,>=0.3.6 - filelock: <4,>=3.4.1 - importlib-metadata: '>=4.8.3' - platformdirs: <4,>=2.4 - python: '>=3.7' + filelock: <4,>=3.11 + platformdirs: <4,>=3.2 + python: '>=3.8' hash: - md5: cb9a711f7c9f3074fe522e5a34481e60 - sha256: 28540cdda9279d7daeb8f2deec6f1128869ba90742a966e488b692e8083c5349 + md5: a920e114c4c2ced2280e266da65ab5e6 + sha256: 13d667887ea08b6d1fe2eb09d2d737f9af7343735d3bfa5ffaa3f67eec8eaff7 manager: conda name: virtualenv optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.21.0-pyhd8ed1ab_0.conda - version: 20.21.0 + url: https://conda.anaconda.org/conda-forge/noarch/virtualenv-20.23.0-pyhd8ed1ab_0.conda + version: 20.23.0 - category: main dependencies: conda-package-streaming: '>=0.7.0' @@ -4748,22 +4761,22 @@ package: version: 23.13.1 - category: main dependencies: - cairo: '>=1.16.0,<2.0.0a0' - gdk-pixbuf: '>=2.42.8,<3.0a0' - gettext: '>=0.19.8.1,<1.0a0' + cairo: '>=1.16.0,<2.0a0' + gdk-pixbuf: '>=2.42.10,<3.0a0' + gettext: '>=0.21.1,<1.0a0' libgcc-ng: '>=12' - libglib: '>=2.70.2,<3.0a0' - libxml2: '>=2.9.14,<2.11.0a0' - pango: '>=1.50.7,<1.51.0a0' + libglib: '>=2.76.1,<3.0a0' + libxml2: '>=2.10.4,<2.11.0a0' + pango: '>=1.50.14,<2.0a0' hash: - md5: 921e53675ed5ea352f022b79abab076a - sha256: 9b81f3854660e902a417e8194b43ed2f5d2a082227df28ba6804c68ac7c16aa0 + md5: 1ec4fab6eb4af1db9056b94265fe19cf + sha256: 6449497e50d2343c6caf73ad9c74f82341e0c22aca3d6f333869e0a069d0c472 manager: conda name: librsvg optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/librsvg-2.54.4-h7abd40a_0.tar.bz2 - version: 2.54.4 + url: https://conda.anaconda.org/conda-forge/linux-64/librsvg-2.56.0-h5cef280_0.conda + version: 2.56.0 - category: main dependencies: jsonschema: '>=3.2.0,<5.0.0' @@ -4789,14 +4802,14 @@ package: pyyaml: '>=5.1' virtualenv: '>=20.10.0' hash: - md5: 9a160452d1d88a9f10c373888f93586b - sha256: 91e104de6854e07a580603a7affb1a6e77823e9d4246486ecfd47d3978839212 + md5: c3ad8d291556452edb6c301c91f330ed + sha256: db90abf2c06c8bace41c491e2af445d06178fa8c9111e0e2ae4738866cb929ef manager: conda name: pre-commit optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.2.0-pyha770c72_0.conda - version: 3.2.0 + url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.3.1-pyha770c72_0.conda + version: 3.3.1 - category: main dependencies: __unix: '' @@ -4835,89 +4848,74 @@ package: python-dateutil: '>=2.1,<3.0.0' urllib3: '>=1.25.4,<1.27' hash: - md5: 3faabd8720a81a91566e6c01bf7bbacb - sha256: c677cba87c7027ccf264574a87130bf44f69be008315d2a840ae6cfaa61b7e44 + md5: 7da51e7dabbb80ebe3064e9343e8e818 + sha256: 1806dfc46c9f4b51ff56575025e7e5491ee630a6be5997dd1536009585da4c4c manager: conda name: botocore optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.27.59-pyhd8ed1ab_0.tar.bz2 - version: 1.27.59 + url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.29.131-pyhd8ed1ab_0.conda + version: 1.29.131 - category: main dependencies: cairo: '>=1.16.0,<2.0a0' - expat: '>=2.5.0,<3.0a0' - fontconfig: '>=2.14.1,<3.0a0' + expat: '' + fontconfig: '>=2.14.2,<3.0a0' fonts-conda-ecosystem: '' freetype: '>=2.12.1,<3.0a0' gdk-pixbuf: '>=2.42.10,<3.0a0' gtk2: '' gts: '>=0.7.6,<0.8.0a0' + libexpat: '>=2.5.0,<3.0a0' libgcc-ng: '>=12' libgd: '>=2.3.3,<2.4.0a0' - libglib: '>=2.74.1,<3.0a0' - librsvg: '>=2.54.4,<3.0a0' + libglib: '>=2.76.2,<3.0a0' + librsvg: '>=2.56.0,<3.0a0' libstdcxx-ng: '>=12' libtool: '' - libwebp-base: '>=1.2.4,<2.0a0' + libwebp-base: '>=1.3.0,<2.0a0' libzlib: '>=1.2.13,<1.3.0a0' - pango: '>=1.50.12,<2.0a0' + pango: '>=1.50.14,<2.0a0' zlib: '' hash: - md5: e7ecda996c443142a0e9c379f3b28e48 - sha256: cecaa9e6dce7f2df042768d9a794f0126565a30384fcd59879e107d760bed7f1 + md5: 597e2d0e1c6bc2e4457714ff479fe142 + sha256: 4bfb42de2d28406666ef6729169cae3f49c216c5ebd9f34afa40223755e2aaf8 manager: conda name: graphviz optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/graphviz-7.1.0-h2e5815a_0.conda - version: 7.1.0 + url: https://conda.anaconda.org/conda-forge/linux-64/graphviz-8.0.5-h28d9a01_0.conda + version: 8.0.5 - category: main dependencies: certifi: '>=2017.4.17' - charset-normalizer: '>=2,<3' + charset-normalizer: '>=2,<4' idna: '>=2.5,<4' - python: '>=3.7,<4.0' + python: '>=3.7' urllib3: '>=1.21.1,<1.27' hash: - md5: 11d178fc55199482ee48d6812ea83983 - sha256: 22c081b4cdd023a514400413f50efdf2c378f56f2a5ea9d65666aacf4696490a + md5: 5fa992d972fbccfc069161805122cb8d + sha256: bd06a6603104050fc9c4fd9bf3de7b28bbb6b9ce4b33130519d8611488213f67 manager: conda name: requests optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/requests-2.28.2-pyhd8ed1ab_0.conda - version: 2.28.2 -- category: main - dependencies: - aiohttp: '>=3.3.1' - aioitertools: '>=0.5.1' - botocore: '>=1.27.59,<1.27.60' - python: '>=3.6' - wrapt: '>=1.10.10' - hash: - md5: a3f48ea10883a5df371b895008b1ca4b - sha256: 76068553358b26c9c03be992cbe982a369d1e015a53700f092db92c784ce98a9 - manager: conda - name: aiobotocore - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/aiobotocore-2.4.2-pyhd8ed1ab_0.conda - version: 2.4.2 + url: https://conda.anaconda.org/conda-forge/noarch/requests-2.29.0-pyhd8ed1ab_0.conda + version: 2.29.0 - category: main dependencies: botocore: '>=1.11.3' python: '>=3.4' wrapt: '' hash: - md5: 2f18ecd9ec078c10f7086ad7ee05289b - sha256: ab3afec58f5368351efac43e813e62f944d41bd879c99e45ad49910aac666447 + md5: a9f8851a7aad0fa6ec843b1beb95decf + sha256: ad37f3f8a6653fb91354716adec29dfb9f5917b7aa06d77f33af8ea7947eb116 manager: conda name: aws-xray-sdk optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/aws-xray-sdk-2.11.0-pyhd8ed1ab_0.tar.bz2 - version: 2.11.0 + url: https://conda.anaconda.org/conda-forge/noarch/aws-xray-sdk-2.12.0-pyhd8ed1ab_0.conda + version: 2.12.0 - category: main dependencies: python: '>=3.6' @@ -4925,14 +4923,14 @@ package: six: '>=1.11.0' typing-extensions: '>=4.0.1' hash: - md5: e49892b87d27fce696b7118a27558fae - sha256: bb995e74396dc34da1a1f9931f40949979913c7b2802c51c799a604edbb45516 + md5: f4d871cde207029fbd3059fc4ad76af9 + sha256: 85884ae07cd171b577dba67059b633df5c6ad0a8fff8222de4bf77530426aea6 manager: conda name: azure-core optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/azure-core-1.26.3-pyhd8ed1ab_0.conda - version: 1.26.3 + url: https://conda.anaconda.org/conda-forge/noarch/azure-core-1.26.4-pyhd8ed1ab_0.conda + version: 1.26.4 - category: main dependencies: msgpack-python: '>=0.5.2' @@ -4979,14 +4977,14 @@ package: urllib3: '>=1.26.0' websocket-client: '>=0.32.0' hash: - md5: 8b0d1b5227ce39053aa69c3ff18417ec - sha256: 45e16e6f7e4105c71c1494ca523b01e676349a25ee1f8114a6c10bbdd8549d50 + md5: 543336c6aa9516cfb29c51d5c162b177 + sha256: 5e01e15e20ee573c99b530633a0d5c71fd515e4ac6d2f5f5f57baece8b915cc3 manager: conda name: docker-py optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/docker-py-6.0.0-pyhd8ed1ab_0.tar.bz2 - version: 6.0.0 + url: https://conda.anaconda.org/conda-forge/noarch/docker-py-6.1.0-pyhd8ed1ab_0.conda + version: 6.1.0 - category: main dependencies: appdirs: '' @@ -5005,19 +5003,19 @@ package: version: 1.4.3 - category: main dependencies: - cryptography: '>=0.6,<41' + cryptography: '>=0.6,<43' pyjwt: '>=1.0.0,<3' python: '>=3.6' requests: '>=2.0.0,<3' hash: - md5: 9304c2492b162934f748d061be0042e8 - sha256: a516cdfa79d90f678507c986da24d5d9979083d90337eeaa17fdd7f3d2e1a976 + md5: 24c290ee3278fd9a33b00cd1f8d1db0f + sha256: 7f4cc4d6383263ad9cc69dc83bb5dd5d4a309ebe53f117e1d14ffd76f31939de manager: conda name: msal optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/msal-1.21.0-pyhd8ed1ab_0.conda - version: 1.21.0 + url: https://conda.anaconda.org/conda-forge/noarch/msal-1.22.0-pyhd8ed1ab_0.conda + version: 1.22.0 - category: main dependencies: graphviz: '>=2.46.1' @@ -5050,14 +5048,14 @@ package: botocore: '>=1.12.36,<2.0a.0' python: '>=3.7' hash: - md5: 900e74d8547fbea3af028937df28ed77 - sha256: 0e459ed32b00e96b62c2ab7e2dba0135c73fd980120fe1a7bd49901f2d50760f + md5: b19a857ac845097e9c823c9f4d35f80e + sha256: 99512bf4f4e297cc7565c94eee8ccc908411f836b341668e2b5d064273e21762 manager: conda name: s3transfer optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/s3transfer-0.6.0-pyhd8ed1ab_0.tar.bz2 - version: 0.6.0 + url: https://conda.anaconda.org/conda-forge/noarch/s3transfer-0.6.1-pyhd8ed1ab_0.conda + version: 0.6.1 - category: main dependencies: alabaster: '>=0.7,<0.8' @@ -5089,7 +5087,7 @@ package: version: 5.1.1 - category: main dependencies: - botocore: 1.27.59 + botocore: 1.29.131 colorama: '>=0.2.5,<0.4.5' docutils: '>=0.10,<0.17' python: '>=3.10,<3.11.0a0' @@ -5098,29 +5096,29 @@ package: rsa: '>=3.1.2,<4.8' s3transfer: '>=0.6.0,<0.7.0' hash: - md5: 7fca00e32e7d64340bebb17799aafd16 - sha256: 118e95635796784bb1d0072d65be0fc1151ba7aca7118a5c79764ff2667301ad + md5: a8803614b98f834dd8e9239b1c172bb1 + sha256: 627c4db1e6c5e2febb5b9a7acf92b68a3c26afc26800700b510e076c46c02129 manager: conda name: awscli optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.25.60-py310hff52083_0.tar.bz2 - version: 1.25.60 + url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.27.131-py310hff52083_0.conda + version: 1.27.131 - category: main dependencies: - botocore: '>=1.27.59,<1.28.0' + botocore: '>=1.29.131,<1.30.0' jmespath: '>=0.7.1,<2.0.0' python: '>=3.7' s3transfer: '>=0.6.0,<0.7.0' hash: - md5: ffb13a0a5fc8e17ce396f4dfcdf5dab5 - sha256: 89fd09bdc9d9a608387fd80b19fd084f26309d7857bd9a3957216a718f58b3de + md5: f51fe6d09662dc8ec9672be8567b7430 + sha256: 888fa362ba6db8b881a200539c1cc4379379ec1937168e5e475245fa1a3544c7 manager: conda name: boto3 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.24.59-pyhd8ed1ab_0.tar.bz2 - version: 1.24.59 + url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.26.131-pyhd8ed1ab_0.conda + version: 1.26.131 - category: main dependencies: cachecontrol: 0.12.11 pyhd8ed1ab_1 @@ -5142,13 +5140,13 @@ package: networkx: '' python: '>=3.6' hash: - md5: f47b4fbd862cc05b914d2e4862df72a1 - sha256: 3a7f989bdcb5a6a284d092745892f8f27d15b348a02b95229d258899d418fd82 + md5: 184216409957e082712d750862782903 + sha256: 54e9cf114ca4eaeda91b5bb11a09d4391ba4be8a4fb2911259fc7dc2ec636054 manager: conda name: conda-tree optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/conda-tree-1.1.0-pyhd8ed1ab_0.conda + url: https://conda.anaconda.org/conda-forge/noarch/conda-tree-1.1.0-pyhd8ed1ab_2.conda version: 1.1.0 - category: main dependencies: @@ -5181,21 +5179,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/noarch/msal_extensions-1.0.0-pyhd8ed1ab_0.tar.bz2 version: 1.0.0 -- category: main - dependencies: - aiobotocore: '>=2.4.2,<2.4.3' - aiohttp: '' - fsspec: 2023.3.0 - python: '>=3.8' - hash: - md5: 53b2e3e80df2a18eb74d53729b9464f2 - sha256: 2737102a9d3d538dccf22fc32e32e2ec608d69c2a002a1f137091b9611bf5d6e - manager: conda - name: s3fs - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/s3fs-2023.3.0-pyhd8ed1ab_0.conda - version: 2023.3.0 - category: main dependencies: livereload: '>=2.3.0' @@ -5261,14 +5244,14 @@ package: python: '' typing_extensions: '' hash: - md5: 009fa15810ae5d376e1bd29ab93c1081 - sha256: 380426f97ae074ad86a1b52bb106e1f10e868bc8b7c575bea6ea5ac7725bc84d + md5: da03042814034e36f0938058b7b218fb + sha256: d18385d39e4af117b99cbd931cb68cbd33582949a837ae4e6453964ecc64d80a manager: conda name: boto3-stubs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.95-pyhd8ed1ab_0.conda - version: 1.26.95 + url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.130-pyhd8ed1ab_0.conda + version: 1.26.130 - category: main dependencies: cachecontrol-with-filecache: '>=0.12.9' @@ -5309,28 +5292,42 @@ package: python: '>=3.6' typing-extensions: '' hash: - md5: 0c79de238c80f668f5a4e85a2ca1dced - sha256: 348b0bdb9d9fcfdfc24c43ea93a29e2c5aba7f8d0e5570517e965c758c380419 + md5: adb30ee4ef9f506b62f732c8a78d250b + sha256: 281ba68f92f05626bf37df32156abbf62e6ed963ab40b2205277a066391cc06f manager: conda name: mypy-boto3-s3 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.26.62-pyhd8ed1ab_0.conda - version: 1.26.62 + url: https://conda.anaconda.org/conda-forge/noarch/mypy-boto3-s3-1.26.127-pyhd8ed1ab_0.conda + version: 1.26.127 - category: main dependencies: boto3: '' python: '>=3.6' typing-extensions: '' hash: - md5: a0ead2e95ffa5942c419234c15463344 - sha256: 7e7bb339939a50d9e682c01938062d2d4e1157a7b034d7f91e44e11d98c0d05d + md5: 35a0dc87b7ff0abd9e3012bea164f439 + sha256: 706be4a8f070af47d29e18315c3053977315c1c58479ecfebb2443d3a72edf87 manager: conda name: mypy_boto3_ec2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.26.91-pyhd8ed1ab_0.conda - version: 1.26.91 + url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.26.129-pyhd8ed1ab_0.conda + version: 1.26.129 +- category: main + dependencies: + boto3: '' + fsspec: '>=0.6.0' + python: '>=3.5' + hash: + md5: ead328eb12f01d88706126ba061e7a69 + sha256: 7a4cb574ff7edf773e5e4c396733dcb08ffcfd6e4f8b27e5b84b35fd4666ef5b + manager: conda + name: s3fs + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/s3fs-0.4.2-py_0.tar.bz2 + version: 0.4.2 - category: main dependencies: docutils: <0.19 @@ -5371,18 +5368,18 @@ package: aws-xray-sdk: '!=0.96,>=0.93' boto3: '>=1.9.201' botocore: '>=1.12.201' - cfn-lint: '>=0.4.0' + cfn-lint: '>=0.40.0' cryptography: '>=3.3.1' docker-py: '>=2.5.1' - flask: '' + flask: '!=2.2.0,!=2.2.1' flask_cors: '' graphql-core: '' idna: '>=2.5,<4' importlib_metadata: '' jinja2: '>=2.10.1' jsondiff: '>=1.1.2' - openapi-spec-validator: '' - pyparsing: '' + openapi-spec-validator: '>=0.2.8' + pyparsing: '>=3.0.7' python: '>=3.3' python-dateutil: '>=2.1,<3.0.0' python-jose: '>=3.1.0,<4.0.0' @@ -5392,27 +5389,27 @@ package: responses: '>=0.9.0' setuptools: '' sshpubkeys: '>=3.1.0' - werkzeug: <2.2.0,>=0.5 + werkzeug: '>=0.5,!=2.2.0,!=2.2.1' xmltodict: '' hash: - md5: 702e5d281f691be1bec2f23d1f24fee8 - sha256: 5f7094094ef361b135068b12facdf34c18d2b285c4bd87a935ab1c7e633990ee + md5: 89dfb6776dcc992a100cafd0c612b7fb + sha256: f5de61e07e99798c0f73947fae9f947a4eb7aeff7adc04e78b9a9a3ef2ddc780 manager: conda name: moto optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.5-pyhd8ed1ab_0.conda - version: 4.1.5 + url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.9-pyhd8ed1ab_0.conda + version: 4.1.9 - category: main dependencies: {} hash: - sha256: c41cfb1e99ba5d341fbcc5308836e7d7c9786d302f995b2c271ce2144dece9eb + sha256: 0e0bc5ba78b8db3667ad636d964eb963dc97a59f04c6f6214c5f0e4a8f726c56 manager: pip name: mock optional: false platform: linux-64 - url: https://files.pythonhosted.org/packages/e6/88/8a05e7ad0bb823246b2add3d2e97f990c41c71a40762c8db77a4bd78eedf/mock-5.0.1-py3-none-any.whl - version: 5.0.1 + url: https://files.pythonhosted.org/packages/27/6f/fbb16f260a7107ee98871d83f6793d88c4311b7189b10ef239da0b2181db/mock-5.0.2-py3-none-any.whl + version: 5.0.2 - dependencies: {} hash: sha256: f84fbc98b019fef2ee9a1cb3ce93e3187a6df0b2538a651bfb890254ba9f90b5 @@ -5455,15 +5452,17 @@ package: platform: linux-64 url: https://files.pythonhosted.org/packages/9f/53/1ac75eab589149b1e02e38185ecebf09e1b805fc3fdeadbc16d1a2b7d208/paramiko_ng-2.8.10-py2.py3-none-any.whl version: 2.8.10 -- dependencies: - ruamel.yaml.clib: '>=0.2.6' +- category: main + dependencies: + ruamel.yaml.clib: '>=0.2.7' hash: - sha256: 742b35d3d665023981bd6d16b3d24248ce5df75fdb4e2924e93a05c1f8b61ca7 + sha256: 25d0ee82a0a9a6f44683dcf8c282340def4074a4562f3a24f55695bb254c1693 manager: pip name: ruamel.yaml + optional: false platform: linux-64 - url: https://files.pythonhosted.org/packages/9e/cb/938214ac358fbef7058343b3765c79a1b7ed0c366f7f992ce7ff38335652/ruamel.yaml-0.17.21-py3-none-any.whl - version: 0.17.21 + url: https://files.pythonhosted.org/packages/23/33/dbc62343de0cf92e0f9c15bc0a287bdaea0953f1cadca0480c78d5ac6641/ruamel.yaml-0.17.26-py3-none-any.whl + version: 0.17.26 - category: main dependencies: mock: '*' @@ -5496,13 +5495,13 @@ package: pyyaml: '>=6.0,<7.0' ruamel.yaml: '>=0.17.21,<0.18.0' hash: - sha256: 638a6b8c3e631f85f235acf02d3bef35a0a6d7da2ec9fef17420d5dd2ce66678 + sha256: f4fb4dd5f7fac1f2206a25d0949024046fe8f855198e8edbd5206fa9d58ab05f manager: pip name: hammer-vlsi optional: false platform: linux-64 - url: https://files.pythonhosted.org/packages/53/39/18367e6fb4f20e9ae4fb3097f7b80704ff5cccf62980ea2871ba1d817a74/hammer_vlsi-1.1.0-py3-none-any.whl - version: 1.1.0 + url: https://files.pythonhosted.org/packages/0a/da/1897421311c6332655e2f73d02d8c914ecb724198a1988aacd8f4c61ae6e/hammer_vlsi-1.1.1-py3-none-any.whl + version: 1.1.1 - category: main dependencies: asttokens: '>=2,<3' diff --git a/docs/Advanced-Concepts/Architectural-Checkpoints.rst b/docs/Advanced-Concepts/Architectural-Checkpoints.rst new file mode 100644 index 00000000..490bddc5 --- /dev/null +++ b/docs/Advanced-Concepts/Architectural-Checkpoints.rst @@ -0,0 +1,39 @@ +.. _checkpointing: + +Architectural Checkpoints +========================= + +Chipyard supports generating architectural checkpoints using Spike. +These checkpoints contain a snapshot of the architectural state of a RISC-V SoC at some point in the execution of a program. +The checkpoints include the contents of cacheable memory, core architectural registers, and core CSRs. +RTL simulations of SoCs can resume execution from checkpoints after restoring the architectural state. + +.. note:: + Currently, only checkpoints of single-core systems are supported + +Generating Checkpoints +------------------------ + +``scripts/generate-ckpt.sh`` is a script that runs spike with the right commands to generate an architectural checkpoint +``scripts/generate-ckpt.sh -h`` lists options for checkpoint generation. + +Example: run the ``hello.riscv`` binary for 1000 instructions before generating a checkpoint. +This should produce a directory named ``hello.riscv.0x80000000.1000.loadarch`` + +.. code:: + + scripts/generate-ckpt.sh -b tests/hello.riscv -i 1000 + + +Loading Checkpoints in RTL Simulation +-------------------------------------- + +Checkpoints can be loaded in RTL simulations with the ``LOADARCH`` flag. +The target config **MUST** use dmi-based bringup (as opposed to the default TSI-based bringup), and support fast ``LOADMEM``. +The target config should also match the architectural configuration of however spike was configured when generating the checkpoint. + +.. code:: + + cd sims/vcs + make CONFIG=dmiRocketConfig run-binary LOADARCH=../../hello.riscv.0x80000000.1000.loadarch + diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index f86a118a..3e067965 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -47,12 +47,12 @@ Using the Tethered Serial Interface (TSI) By default, Chipyard uses the Tethered Serial Interface (TSI) to communicate with the DUT. TSI protocol is an implementation of HTIF that is used to send commands to the RISC-V DUT. These TSI commands are simple R/W commands that are able to access the DUT's memory space. -During simulation, the host sends TSI commands to a simulation stub in the test harness called ``SimSerial`` -(C++ class) that resides in a ``SimSerial`` Verilog module (both are located in the ``generators/testchipip`` +During simulation, the host sends TSI commands to a simulation stub in the test harness called ``SimTSI`` +(C++ class) that resides in a ``SimTSI`` Verilog module (both are located in the ``generators/testchipip`` project). -This ``SimSerial`` Verilog module then sends the TSI command recieved by the simulation stub +This ``SimTSI`` Verilog module then sends the TSI command recieved by the simulation stub to an adapter that converts the TSI command into a TileLink request. -This conversion is done by the ``SerialAdapter`` module (located in the ``generators/testchipip`` project). +This conversion is done by the ``TSIToTileLink`` module (located in the ``generators/testchipip`` project). After the transaction is converted to TileLink, the ``TLSerdesser`` (located in ``generators/testchipip``) serializes the transaction and sends it to the chip (this ``TLSerdesser`` is sometimes also referred to as a digital serial-link or SerDes). Once the serialized transaction is received on the chip, it is deserialized and masters a TileLink bus on the chip @@ -76,7 +76,7 @@ simulation stub called ``SimDTM`` (C++ class) that resides in a ``SimDTM`` Veril sends the DMI command recieved by the simulation stub into the DUT which then converts the DMI command into a TileLink request. This conversion is done by the DTM named ``DebugModule`` in the ``generators/rocket-chip`` project. When the DTM receives the program to load, it starts to write the binary byte-wise into memory. -This is considerably slower than the TSI protocol communication pipeline (i.e. ``SimSerial``/``SerialAdapter``/TileLink) +This is considerably slower than the TSI protocol communication pipeline (i.e. ``SimTSI``/``TSIToTileLink``/TileLink) which directly writes the program binary to memory. Starting the TSI or DMI Simulation @@ -206,13 +206,17 @@ This type of simulation setup is done in the following multi-clock configuration :start-after: DOC include start: MulticlockAXIOverSerialConfig :end-before: DOC include end: MulticlockAXIOverSerialConfig -Bringup Setup of the Example Test Chip after Tapeout -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Softcore-driven Bringup Setup of the Example Test Chip after Tapeout +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. warning:: + Bringing up test chips with a FPGA softcore as described here is discouraged. + An alternative approach using the FPGA to "bridge" between a host computer and the test chip is the preferred approach. Assuming this example test chip is taped out and now ready to be tested, we can communicate with the chip using this serial-link. For example, a common test setup used at Berkeley to evaluate Chipyard-based test-chips includes an FPGA running a RISC-V soft-core that is able to speak to the DUT (over an FMC). This RISC-V soft-core would serve as the host of the test that will run on the DUT. -This is done by the RISC-V soft-core running FESVR, sending TSI commands to a ``SerialAdapter`` / ``TLSerdesser`` programmed on the FPGA. +This is done by the RISC-V soft-core running FESVR, sending TSI commands to a ``TSIToTileLink`` / ``TLSerdesser`` programmed on the FPGA. Once the commands are converted to serialized TileLink, then they can be sent over some medium to the DUT (like an FMC cable or a set of wires connecting FPGA outputs to the DUT board). Similar to simulation, if the chip requests offchip memory, it can then send the transaction back over the serial-link. @@ -222,4 +226,4 @@ The following image shows this flow: .. image:: ../_static/images/chip-bringup.png In fact, this exact type of bringup setup is what the following section discusses: -:ref:`Prototyping/VCU118:Introduction to the Bringup Design`. +:ref:_legacy-vcu118-bringup. diff --git a/docs/Advanced-Concepts/Harness-Clocks.rst b/docs/Advanced-Concepts/Harness-Clocks.rst index ef224974..e7501cec 100644 --- a/docs/Advanced-Concepts/Harness-Clocks.rst +++ b/docs/Advanced-Concepts/Harness-Clocks.rst @@ -18,12 +18,12 @@ for a new clock domain. This is useful for simulating systems in which modules in the harness have independent clock domains from the DUT. -Requests for a harness clock is done by the ``HarnessClockInstantiator`` class in ``generators/chipyard/src/main/scala/TestHarness.scala``. +Requests for a harness clock is done by the ``HarnessClockInstantiator`` class in ``generators/chipyard/src/main/scala/harness/TestHarness.scala``. This class is accessed in harness components by referencing the Rocket Chip parameters key ``p(HarnessClockInstantiatorKey)``. Then you can request a clock and syncronized reset at a particular frequency by invoking the ``requestClockBundle`` function. Take the following example: -.. literalinclude:: ../../generators/chipyard/src/main/scala/HarnessBinders.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/harness/HarnessBinders.scala :language: scala :start-after: DOC include start: HarnessClockInstantiatorEx :end-before: DOC include end: HarnessClockInstantiatorEx diff --git a/docs/Advanced-Concepts/Resources.rst b/docs/Advanced-Concepts/Resources.rst index 6af72836..fbfaad60 100644 --- a/docs/Advanced-Concepts/Resources.rst +++ b/docs/Advanced-Concepts/Resources.rst @@ -2,24 +2,24 @@ Accessing Scala Resources =============================== A simple way to copy over a source file to the build directory to be used for a simulation compile or VLSI flow is to use the ``addResource`` function given by FIRRTL. -An example of its use can be seen in `generators/testchipip/src/main/scala/SerialAdapter.scala `_. +An example of its use can be seen in `generators/testchipip/src/main/scala/SimTSI.scala `_. Here is the example inlined: .. code-block:: scala - class SimSerial(w: Int) extends BlackBox with HasBlackBoxResource { + class SimTSI extends BlackBox with HasBlackBoxResource { val io = IO(new Bundle { val clock = Input(Clock()) val reset = Input(Bool()) - val serial = Flipped(new SerialIO(w)) + val tsi = Flipped(new TSIIO) val exit = Output(Bool()) }) - addResource("/testchipip/vsrc/SimSerial.v") - addResource("/testchipip/csrc/SimSerial.cc") + addResource("/testchipip/vsrc/SimTSI.v") + addResource("/testchipip/csrc/SimTSI.cc") } -In this example, the ``SimSerial`` files will be copied from a specific folder (in this case the ``path/to/testchipip/src/main/resources/testchipip/...``) to the build folder. +In this example, the ``SimTSI`` files will be copied from a specific folder (in this case the ``path/to/testchipip/src/main/resources/testchipip/...``) to the build folder. The ``addResource`` path retrieves resources from the ``src/main/resources`` directory. So to get an item at ``src/main/resources/fileA.v`` you can use ``addResource("/fileA.v")``. However, one caveat of this approach is that to retrieve the file during the FIRRTL compile, you must have that project in the FIRRTL compiler's classpath. diff --git a/docs/Advanced-Concepts/Top-Testharness.rst b/docs/Advanced-Concepts/Top-Testharness.rst index 23f3f56a..e412eeff 100644 --- a/docs/Advanced-Concepts/Top-Testharness.rst +++ b/docs/Advanced-Concepts/Top-Testharness.rst @@ -18,6 +18,13 @@ The ``IOBinders`` are responsible for instantiating the IO cells for ``ChipTop`` The ``HarnessBinders`` are responsible for instantiating test harness collateral that connects to the ``ChipTop`` ports. Most types of devices and testing collateral can be instantiated using custom ``IOBinders`` and ``HarnessBinders``. +Custom ChipTops +^^^^^^^^^^^^^^^^^^^^^^^^^ + +The default standard ``ChipTop`` provides a mimimal, barebones template for ``IOBinders`` to generate IOCells around ``DigitalTop`` traits. +For tapeouts, integrating Analog IP, or other non-standard use cases, Chipyard supports specifying a custom ``ChipTop`` using the ``BuildTop`` key. +An example of a custom ChipTop which uses non-standard IOCells is provided in `generators/chipyard/src/main/scala/example/CustomChipTop.scala `__ + System/DigitalTop ------------------------- diff --git a/docs/Advanced-Concepts/index.rst b/docs/Advanced-Concepts/index.rst index b67bbbb3..d5455ddb 100644 --- a/docs/Advanced-Concepts/index.rst +++ b/docs/Advanced-Concepts/index.rst @@ -16,3 +16,4 @@ They expect you to know about Chisel, Parameters, configs, etc. CDEs Harness-Clocks Managing-Published-Scala-Dependencies + Architectural-Checkpoints diff --git a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst index f55d15be..818d7b69 100644 --- a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst +++ b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst @@ -83,8 +83,8 @@ This example shows the Chipyard default top that composes multiple traits togeth :end-before: DOC include end: DigitalTop -There are two "cakes" or mixins here. One for the lazy module (ex. ``CanHavePeripherySerial``) and one for the lazy module -implementation (ex. ``CanHavePeripherySerialModuleImp`` where ``Imp`` refers to implementation). The lazy module defines +There are two "cakes" or mixins here. One for the lazy module (ex. ``CanHavePeripheryTLSerial``) and one for the lazy module +implementation (ex. ``CanHavePeripheryTLSerialModuleImp`` where ``Imp`` refers to implementation). The lazy module defines all the logical connections between generators and exchanges configuration information among them, while the lazy module implementation performs the actual Chisel RTL elaboration. @@ -93,19 +93,17 @@ In the ``DigitalTop`` example class, the "outer" ``DigitalTop`` instantiates the of the module until all logical connections are determined and all configuration information is exchanged. The ``System`` outer base class, as well as the ``CanHavePeriphery`` outer traits contain code to perform high-level logical -connections. For example, the ``CanHavePeripherySerial`` outer trait contains code -to optionally lazily instantiate the ``SerialAdapter``, and connect the ``SerialAdapter``'s +connections. For example, the ``CanHavePeripheryTLSerial`` outer trait contains code +to optionally lazily instantiate the ``TLSerdesser``, and connect the ``TLSerdesser`` 's TileLink node to the Front bus. The ``ModuleImp`` classes and traits perform elaboration of real RTL. -For example, the ``CanHavePeripherySerialModuleImp`` trait optionally physically connects -the ``SerialAdapter`` module, and instantiates queues. In the test harness, the SoC is elaborated with ``val dut = p(BuildTop)(p)``. After elaboration, the system submodule of ``ChipTop`` will be a ``DigitalTop`` module, which contains a -``SerialAdapter`` module (among others), if the config specified for that block to be instantiated. +``TLSerdesser`` module (among others), if the config specified for that block to be instantiated. From a high level, classes which extend ``LazyModule`` *must* reference their module implementation through ``lazy val module``, and they @@ -116,7 +114,7 @@ other normal modules OR lazy modules (for nested Diplomacy graphs, for example). The naming convention for an additive mixin or trait is ``CanHave``. -This is shown in the ``Top`` class where things such as ``CanHavePeripherySerial`` connect a RTL component to a bus and expose signals to the top-level. +This is shown in the ``Top`` class where things such as ``CanHavePeripheryTLSerial`` connect a RTL component to a bus and expose signals to the top-level. Additional References --------------------------- diff --git a/docs/Customization/IOBinders.rst b/docs/Customization/IOBinders.rst index 1ae95512..d3626a03 100644 --- a/docs/Customization/IOBinders.rst +++ b/docs/Customization/IOBinders.rst @@ -31,7 +31,7 @@ Like ``IOBinders``, ``HarnessBinders`` are defined using macros (``OverrideHarne For exmaple, the ``WithUARTAdapter`` will connect the UART SW display adapter to the ports generated by the ``WithUARTIOCells`` described earlier, if those ports are present. -.. literalinclude:: ../../generators/chipyard/src/main/scala/HarnessBinders.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/harness/HarnessBinders.scala :language: scala :start-after: DOC include start: WithUARTAdapter :end-before: DOC include end: WithUARTAdapter diff --git a/docs/Customization/Keys-Traits-Configs.rst b/docs/Customization/Keys-Traits-Configs.rst index 364f31cb..7b6d565b 100644 --- a/docs/Customization/Keys-Traits-Configs.rst +++ b/docs/Customization/Keys-Traits-Configs.rst @@ -79,5 +79,4 @@ We can use this config fragment when composing our configs. Chipyard Config Fragments ------------------------- -For discoverability, users can run ``make find-config-fragments`` to see a list of config. fragments -(config. fragments that match "class NAME extends CONFIG\n" on a single line and a subset of their children) and their file path in a fully initialized Chipyard repository. +For discoverability, users can run ``make find-config-fragments`` to see a list of config. fragments. diff --git a/docs/Generators/TestChipIP.rst b/docs/Generators/TestChipIP.rst index 9d08a895..2c382d4f 100644 --- a/docs/Generators/TestChipIP.rst +++ b/docs/Generators/TestChipIP.rst @@ -2,16 +2,16 @@ Test Chip IP ============ Chipyard includes a Test Chip IP library which provides various hardware -widgets that may be useful when designing SoCs. This includes a :ref:`Generators/TestChipIP:Serial Adapter`, +widgets that may be useful when designing SoCs. This includes a :ref:`Generators/TestChipIP:SimTSI`, :ref:`Generators/TestChipIP:Block Device Controller`, :ref:`Generators/TestChipIP:TileLink SERDES`, :ref:`Generators/TestChipIP:TileLink Switcher`, :ref:`Generators/TestChipIP:TileLink Ring Network`, and :ref:`Generators/TestChipIP:UART Adapter`. -Serial Adapter +SimTSI -------------- -The serial adapter is used by tethered test chips to communicate with the host +The SimTSI and TSIToTileLink are used by tethered test chips to communicate with the host processor. An instance of RISC-V frontend server running on the host CPU -can send commands to the serial adapter to read and write data from the memory +can send commands to the TSIToTileLink to read and write data from the memory system. The frontend server uses this functionality to load the test program into memory and to poll for completion of the program. More information on this can be found in :ref:`Customization/Boot-Process:Chipyard Boot Process`. diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst index 89c0b512..2b7a7332 100644 --- a/docs/Prototyping/General.rst +++ b/docs/Prototyping/General.rst @@ -1,18 +1,11 @@ General Setup and Usage ============================== -Sources and Submodule Setup +Sources --------------------------- All FPGA prototyping-related collateral and sources are located in the ``fpga`` top-level Chipyard directory. This includes the ``fpga-shells`` submodule and the ``src`` directory that hold both Scala, TCL and other collateral. -However, the ``fpga-shells`` submodule repository is not initialized by default. -To initialize the ``fpga-shells`` submodule repository, run the included initialization script from the Chipyard top-level directory: - -.. code-block:: shell - - # in the chipyard top level folder - ./scripts/init-fpga.sh Generating a Bitstream ---------------------- diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst index c2c84dcb..96c67f48 100644 --- a/docs/Prototyping/VCU118.rst +++ b/docs/Prototyping/VCU118.rst @@ -47,8 +47,14 @@ After the harness is created, the ``BundleBridgeSource``'s must be connected to This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``). For more information on harness binders and io binders, refer to :ref:`Customization/IOBinders:IOBinders and HarnessBinders`. -Introduction to the Bringup Design ----------------------------------- +(Legacy) Introduction to the Legacy Bringup Design +-------------------------------------------------- + +.. warning:: + The bringup VCU118 design described here is designed for old versions of Chipyard SoCs, pre-1.9.1. + The key difference is that these designs rely on a clock generated on-chip to synchronize the slow serialized-TileLink interface. + After Chipyard 1.9.1, the FPGA host is expected to pass the clock to the chip, instead of the other way around. + A new bringup solution will be developed for post-1.9.1 Chipyard designs. An example of a more complicated design used for Chipyard test chips can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. This example extends the default test harness and creates new ``Overlays`` to connect to a DUT (connected to the FMC port). diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index d62f6f1c..580a5d2e 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -151,25 +151,17 @@ Fast Memory Loading ------------------- The simulator loads the program binary over a simulated serial line. This can be quite slow if there is a lot of static data, so the simulator also allows data to be loaded from a file directly into the DRAM model. +Loadmem files should be ELF files. In the most common use case, this can be the binary. .. code-block:: shell - make run-binary BINARY=test.riscv LOADMEM=testdata.hex LOADMEM_ADDR=81000000 + make run-binary BINARY=test.riscv LOADMEM=test.riscv -The ``.hex`` file should be a text file with a hexadecimal number on each line. - -.. code-block:: text - - deadbeef - 0123 - -Each line uses little-endian order, so this file would produce the bytes "ef be ad de 01 23". ``LOADMEM_ADDR`` specifies which address in memory (in hexadecimal) to write the first byte to. The default is 0x81000000. - -A special target that facilitates automatically generating a hex file for an entire elf RISC-V exectuable and then running the simulator with the appropriate flags is also available. +Usually the ``LOADMEM`` ELF is the same as the ``BINARY`` ELF, so ``LOADMEM=1`` can be used as a shortcut. .. code-block:: shell - make run-binary-hex BINARY=test.riscv + make run-binary BINARY=test.riscv LOADMEM=1 Generating Waveforms ----------------------- diff --git a/docs/Software/Spike.rst b/docs/Software/Spike.rst index bdaa4750..e9abe0c0 100644 --- a/docs/Software/Spike.rst +++ b/docs/Software/Spike.rst @@ -32,4 +32,21 @@ In this configuration, Spike is cache-coherent, and communicates with the uncore make CONFIG=SpikeConfig run-binary BINARY=hello.riscv +Spike-as-a-Tile also supports Tightly-Coupled-Memory (TCM) for the SpikeTile, in which the main system memory is entirely modeled +within the Spike tile, allowing for very fast simulatoin performance. +.. code-block:: shell + + make CONFIG=SpikeUltraFastConfig run-binary BINARY=hello.riscv + +Spike-as-a-Tile can be configured with custom IPC, commit logging, and other behaviors. Spike-specific flags can be added as plusargs to ``EXTRA_SIM_FLAGS`` + +.. code-block:: shell + + make CONFIG=SpikeUltraFastConfig run-binary BINARY=hello.riscv EXTRA_SPIKE_FLAGS="+spike-ipc=10000 +spike-fast-clint +spike-debug" LOADMEM=1 + + +* ``+spike-ipc=``: Sets the maximum number of instructions Spike can retire in a single "tick", or cycle of the uncore simulation. +* ``+spike-fast-clint``: Enables fast-forwarding through WFI stalls by generating fake timer interrupts +* ``+spike-debug``: Enables debug Spike logging +* ``+spike-verbose``: Enables Spike commit-log generation diff --git a/docs/VLSI/ASAP7-Tutorial.rst b/docs/VLSI/ASAP7-Tutorial.rst index 2da52d24..890d991c 100644 --- a/docs/VLSI/ASAP7-Tutorial.rst +++ b/docs/VLSI/ASAP7-Tutorial.rst @@ -115,7 +115,7 @@ Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped .. code-block:: shell - ./view_gds.py build/chipyard.TestHarness.TinyRocketConfig/par-rundir/ChipTop.gds + ./view_gds.py build/chipyard.harness.TestHarness.TinyRocketConfig/par-rundir/ChipTop.gds By default, this script only shows the M2 thru M4 routing. Layers can be toggled in the layout viewer's side pane and ``view_gds.py`` has a mapping of layer numbers to layer names. @@ -126,9 +126,9 @@ To run DRC & LVS, and view the results in Calibre: .. code-block:: shell make drc CONFIG=TinyRocketConfig - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view-drc + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view-drc make lvs CONFIG=TinyRocketConfig - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view-lvs + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view-lvs Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme `__. Furthermore, the dummy SRAMs that are provided in this tutorial and PDK do not have any geometry inside, so will certainly cause DRC errors. diff --git a/docs/VLSI/Sky130-Commercial-Tutorial.rst b/docs/VLSI/Sky130-Commercial-Tutorial.rst index 4bc8449e..300a22d7 100644 --- a/docs/VLSI/Sky130-Commercial-Tutorial.rst +++ b/docs/VLSI/Sky130-Commercial-Tutorial.rst @@ -121,7 +121,7 @@ It is recommended that you edit these variables directly in the Makefile rather The ``buildfile`` make target has dependencies on both (1) the Verilog that is elaborated from all Chisel sources and (2) the mapping of memory instances in the design to SRAM macros; -all files related to these two steps reside in the ``generated-src/chipyard.TestHarness.TinyRocketConfig-ChipTop`` directory. +all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory. Note that the files in ``generated-src`` vary for each tool/technology flow. This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows (due to the ``ENABLE_YOSYS_FLOW`` flag present for the OpenROAD flow), so these flows should be run in separate @@ -168,9 +168,9 @@ To run DRC & LVS, and view the results in Calibre: .. code-block:: shell make drc tutorial=sky130-commercial - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc make lvs tutorial=sky130-commercial - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the `Sky130 Hammer plugin README `__. diff --git a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst index 882429d7..6777bb79 100644 --- a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst +++ b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst @@ -149,7 +149,7 @@ It is recommended that you edit these variables directly in the Makefile rather The ``buildfile`` make target has dependencies on both (1) the Verilog that is elaborated from all Chisel sources and (2) the mapping of memory instances in the design to SRAM macros; -all files related to these two steps reside in the ``generated-src/chipyard.TestHarness.TinyRocketConfig-ChipTop`` directory. +all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory. Note that the files in ``generated-src`` vary for each tool/technology flow. This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows (due to the ``ENABLE_YOSYS_FLOW`` flag, explained below), so these flows should be run in separate @@ -197,7 +197,7 @@ Hammer generates a convenient script to launch these sessions .. code-block:: shell - cd ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir + cd ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/par-rundir ./generated-scripts/open_chip Note that the conda OpenROAD package was compiled with the GUI disabled, so in order to view the layout, @@ -212,7 +212,7 @@ These databases can be restored using the same ``open_chip`` script for debuggin .. code-block:: shell - cd build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir + cd build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/par-rundir ./generated_scripts/open_chip -h " Usage: ./generated-scripts/open_chip [-t] [openroad_db_name] @@ -245,9 +245,9 @@ To run DRC & LVS in Magic & Netgen, respectively: .. code-block:: shell make drc tutorial=sky130-openroad - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc make lvs tutorial=sky130-openroad - ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs + ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs Note that in ``sky130-openroad.yml`` we have set the following YAML keys: diff --git a/fpga/fpga-shells b/fpga/fpga-shells index b6cd1bb7..9f4c6ac5 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit b6cd1bb7fe35bb7a44b6fe5a0d88d1293d7a3bc9 +Subproject commit 9f4c6ac5719b03ded61022dc3767e750872d0535 diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index a88848d0..ad8b9a32 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -1,7 +1,7 @@ // See LICENSE for license details. package chipyard.fpga.arty -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.devices.tilelink._ @@ -17,11 +17,11 @@ import chipyard.{BuildSystem} // DOC include start: AbstractArty and Rocket class WithArtyTweaks extends Config( + new WithArtyResetHarnessBinder ++ new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ - new WithArtyResetHarnessBinder ++ new WithDebugResetPassthrough ++ - + new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new chipyard.config.WithDTSTimebase(32768) ++ new testchipip.WithNoSerialTL ) diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 4e90e858..84d47967 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -2,7 +2,7 @@ package chipyard.fpga.arty import chisel3._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.devices.debug.{HasPeripheryDebug} import freechips.rocketchip.jtag.{JTAGIO} import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp} @@ -15,15 +15,15 @@ import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder} import chipyard.iobinders.JTAGChipIO class WithArtyResetHarnessBinder extends ComposeHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => { - require(ports.size == 2) - + (system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => { + val resetPorts = ports.collect { case b: Bool => b } + require(resetPorts.size == 2) withClockAndReset(th.clock_32MHz, th.ck_rst) { // Debug module reset - th.dut_ndreset := ports(0) + th.dut_ndreset := resetPorts(0) // JTAG reset - ports(1) := PowerOnResetFPGAOnly(th.clock_32MHz) + resetPorts(1) := PowerOnResetFPGAOnly(th.clock_32MHz) } } }) @@ -63,6 +63,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ io_jtag.TMS.i.po.map(_ := DontCare) io_jtag.TDO.i.po.map(_ := DontCare) } + case b: Bool => } } }) diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala index db656752..da6c7318 100644 --- a/fpga/src/main/scala/arty/IOBinders.scala +++ b/fpga/src/main/scala/arty/IOBinders.scala @@ -3,12 +3,12 @@ package chipyard.fpga.arty import chisel3._ import chisel3.experimental.{IO} -import freechips.rocketchip.devices.debug.{HasPeripheryDebugModuleImp} +import freechips.rocketchip.devices.debug.{HasPeripheryDebug} import chipyard.iobinders.{ComposeIOBinder} class WithDebugResetPassthrough extends ComposeIOBinder({ - (system: HasPeripheryDebugModuleImp) => { + (system: HasPeripheryDebug) => { // Debug module reset val io_ndreset: Bool = IO(Output(Bool())).suggestName("ndreset") io_ndreset := system.debug.get.ndreset diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index a3d7fc33..6f7c5ea5 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -3,12 +3,12 @@ package chipyard.fpga.arty import chisel3._ import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters} +import org.chipsalliance.cde.config.{Parameters} import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} -import chipyard.{BuildTop, HasHarnessSignalReferences} -import chipyard.harness.{ApplyHarnessBinders} +import chipyard.harness.{ApplyHarnessBinders, BuildTop, HasHarnessSignalReferences} import chipyard.iobinders.{HasIOBinders} class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { @@ -37,4 +37,9 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell lazyDut match { case d: HasIOBinders => ApplyHarnessBinders(this, d.lazySystem, d.portMap) } + + val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters())) + implicitHarnessClockBundle.clock := buildtopClock + implicitHarnessClockBundle.reset := buildtopReset + harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle) } diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index 0930dbdb..16683141 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -1,7 +1,7 @@ // See LICENSE for license details. package chipyard.fpga.arty100t -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.devices.tilelink._ @@ -22,6 +22,7 @@ class WithNoDesignKey extends Config((site, here, up) => { }) class WithArty100TTweaks extends Config( + new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new WithArty100TUARTTSI ++ new WithArty100TDDRTL ++ new WithNoDesignKey ++ diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala index 5cc1e348..d4e7ebc9 100644 --- a/fpga/src/main/scala/arty100t/Harness.scala +++ b/fpga/src/main/scala/arty100t/Harness.scala @@ -3,8 +3,9 @@ package chipyard.fpga.arty100t import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Parameters} +import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tilelink.{TLClientNode, TLBlockDuringReset} +import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters} import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.shell._ @@ -13,8 +14,8 @@ import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly} import sifive.blocks.devices.uart._ -import chipyard._ -import chipyard.harness.{ApplyHarnessBinders} +import chipyard.{ChipTop, CanHaveMasterTLMemPort, ExtTLMem} +import chipyard.harness._ import chipyard.iobinders.{HasIOBinders} class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell with HasHarnessSignalReferences @@ -87,6 +88,11 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell chiptop match { case d: HasIOBinders => ApplyHarnessBinders(this, d.lazySystem, d.portMap) } + + val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters())) + implicitHarnessClockBundle.clock := buildtopClock + implicitHarnessClockBundle.reset := buildtopReset + harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle) } } diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index 3d86f354..c403b604 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -2,7 +2,6 @@ package chipyard.fpga.arty100t import chisel3._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} import freechips.rocketchip.jtag.{JTAGIO} import freechips.rocketchip.subsystem.{PeripheryBusKey} import freechips.rocketchip.tilelink.{TLBundle} @@ -26,24 +25,25 @@ class WithArty100TUARTTSI(uartBaudRate: BigInt = 115200) extends OverrideHarness ports.map({ port => val ath = th.asInstanceOf[Arty100THarness] val freq = p(PeripheryBusKey).dtsFrequency.get - val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) + val bits = port.bits + port.clock := th.buildtopClock withClockAndReset(th.buildtopClock, th.buildtopReset) { - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) + val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.buildtopReset) val uart_to_serial = Module(new UARTToSerial( freq, UARTParams(0, initBaudRate=uartBaudRate))) val serial_width_adapter = Module(new SerialWidthAdapter( - narrowW = 8, wideW = SerialAdapter.SERIAL_TSI_WIDTH)) + narrowW = 8, wideW = TSI.WIDTH)) serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial) - ram.module.io.tsi_ser.flipConnect(serial_width_adapter.io.wide) + ram.module.io.tsi.flipConnect(serial_width_adapter.io.wide) ath.io_uart_bb.bundle <> uart_to_serial.io.uart ath.other_leds(1) := uart_to_serial.io.dropped - ath.other_leds(9) := ram.module.io.adapter_state(0) - ath.other_leds(10) := ram.module.io.adapter_state(1) - ath.other_leds(11) := ram.module.io.adapter_state(2) - ath.other_leds(12) := ram.module.io.adapter_state(3) + ath.other_leds(9) := ram.module.io.tsi2tl_state(0) + ath.other_leds(10) := ram.module.io.tsi2tl_state(1) + ath.other_leds(11) := ram.module.io.tsi2tl_state(2) + ath.other_leds(12) := ram.module.io.tsi2tl_state(3) } }) } diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala index 07a96cfd..70bd7073 100644 --- a/fpga/src/main/scala/vc707/Configs.scala +++ b/fpga/src/main/scala/vc707/Configs.scala @@ -2,7 +2,7 @@ package chipyard.fpga.vc707 import sys.process._ -import freechips.rocketchip.config.{Config, Parameters} +import org.chipsalliance.cde.config.{Config, Parameters} import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} @@ -17,7 +17,8 @@ import sifive.fpgashells.shell.xilinx.{VC7074GDDRSize} import testchipip.{SerialTLKey} -import chipyard.{BuildSystem, ExtTLMem, DefaultClockFrequencyKey} +import chipyard.{BuildSystem, ExtTLMem} +import chipyard.harness.{DefaultClockFrequencyKey} class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) @@ -39,6 +40,7 @@ class WithSystemModifications extends Config((site, here, up) => { class WithVC707Tweaks extends Config ( // harness binders + new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new WithVC707UARTHarnessBinder ++ new WithVC707SPISDCardHarnessBinder ++ new WithVC707DDRMemHarnessBinder ++ diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala index 924c768e..553cf06e 100644 --- a/fpga/src/main/scala/vc707/TestHarness.scala +++ b/fpga/src/main/scala/vc707/TestHarness.scala @@ -4,8 +4,9 @@ import chisel3._ import chisel3.experimental.{IO} import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource} -import freechips.rocketchip.config.{Parameters} +import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tilelink.{TLClientNode} +import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters} import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay} import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly} @@ -16,9 +17,9 @@ import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{XilinxVC707PCIeX1IO} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO} import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO} -import chipyard.{HasHarnessSignalReferences, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort, DefaultClockFrequencyKey} +import chipyard.{ChipTop, ExtTLMem, CanHaveMasterTLMemPort} import chipyard.iobinders.{HasIOBinders} -import chipyard.harness.{ApplyHarnessBinders} +import chipyard.harness.{ApplyHarnessBinders, HasHarnessSignalReferences, BuildTop, DefaultClockFrequencyKey} class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707Shell { outer => @@ -132,4 +133,9 @@ class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModul // check the top-level reference clock is equal to the default // non-exhaustive since you need all ChipTop clocks to equal the default require(getRefClockFreq == p(DefaultClockFrequencyKey)) + + val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters())) + implicitHarnessClockBundle.clock := buildtopClock + implicitHarnessClockBundle.reset := buildtopReset + harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle) } diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index 85b6ee24..0d82e107 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -2,7 +2,7 @@ package chipyard.fpga.vcu118 import sys.process._ -import freechips.rocketchip.config.{Config, Parameters} +import org.chipsalliance.cde.config.{Config, Parameters} import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} @@ -17,7 +17,8 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} import testchipip.{SerialTLKey} -import chipyard.{BuildSystem, ExtTLMem, DefaultClockFrequencyKey} +import chipyard.{BuildSystem, ExtTLMem} +import chipyard.harness.{DefaultClockFrequencyKey} class WithDefaultPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L))) @@ -41,6 +42,7 @@ class WithSystemModifications extends Config((site, here, up) => { // DOC include start: AbstractVCU118 and Rocket class WithVCU118Tweaks extends Config( // harness binders + new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++ new WithUART ++ new WithSPISDCard ++ new WithDDRMem ++ diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala index 250e2040..02669b79 100644 --- a/fpga/src/main/scala/vcu118/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala @@ -3,7 +3,7 @@ package chipyard.fpga.vcu118 import chisel3._ import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Parameters, Field} +import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink} import sifive.fpgashells.shell._ diff --git a/fpga/src/main/scala/vcu118/HarnessBinders.scala b/fpga/src/main/scala/vcu118/HarnessBinders.scala index d60af21a..50fbfeb4 100644 --- a/fpga/src/main/scala/vcu118/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala @@ -9,8 +9,8 @@ import freechips.rocketchip.tilelink.{TLBundle} import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} -import chipyard.{HasHarnessSignalReferences, CanHaveMasterTLMemPort} -import chipyard.harness.{OverrideHarnessBinder} +import chipyard.{CanHaveMasterTLMemPort} +import chipyard.harness.{HasHarnessSignalReferences, OverrideHarnessBinder} /*** UART ***/ class WithUART extends OverrideHarnessBinder({ diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 9a3cc0d5..5ca3d4a0 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -4,8 +4,9 @@ import chisel3._ import chisel3.experimental.{IO} import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource} -import freechips.rocketchip.config.{Parameters} +import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tilelink.{TLClientNode} +import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters} import sifive.fpgashells.shell.xilinx._ import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly} @@ -17,7 +18,7 @@ import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO} import chipyard._ import chipyard.iobinders.{HasIOBinders} -import chipyard.harness.{ApplyHarnessBinders} +import chipyard.harness._ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays { @@ -134,4 +135,9 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod // check the top-level reference clock is equal to the default // non-exhaustive since you need all ChipTop clocks to equal the default require(getRefClockFreq == p(DefaultClockFrequencyKey)) + + val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters())) + implicitHarnessClockBundle.clock := buildtopClock + implicitHarnessClockBundle.reset := buildtopReset + harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle) } diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 62c2af31..bff715dc 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -2,7 +2,7 @@ package chipyard.fpga.vcu118.bringup import math.min -import freechips.rocketchip.config.{Config, Parameters} +import org.chipsalliance.cde.config.{Config, Parameters} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} import freechips.rocketchip.tilelink._ import freechips.rocketchip.diplomacy._ diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala index 43d559f0..4b9604f9 100644 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.experimental.{attach} import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config.{Parameters, Field} +import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink} import sifive.fpgashells.shell._ diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala index 5b554f5b..c5401d32 100644 --- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala +++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala @@ -4,7 +4,7 @@ import chisel3._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system._ -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala index 27689ca8..7008092a 100644 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -13,8 +13,7 @@ import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO} import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} -import chipyard.{HasHarnessSignalReferences} -import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder} +import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder, HasHarnessSignalReferences} /*** UART ***/ class WithBringupUART extends ComposeHarnessBinder({ diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 2406cb7b..c311d84f 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -3,7 +3,7 @@ package chipyard.fpga.vcu118.bringup import chisel3._ import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ diff --git a/generators/boom b/generators/boom index deae9f70..679f3587 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit deae9f70469336a3787fa7fcc10135ffb93d21d9 +Subproject commit 679f358755c57524f18cf46b72fc3fc1ac67f127 diff --git a/generators/chipyard/src/main/resources/csrc/cospike.cc b/generators/chipyard/src/main/resources/csrc/cospike.cc index fa0513d7..b30806ce 100644 --- a/generators/chipyard/src/main/resources/csrc/cospike.cc +++ b/generators/chipyard/src/main/resources/csrc/cospike.cc @@ -1,3 +1,4 @@ +#include #include #include #include @@ -5,6 +6,25 @@ #include #include #include +#include +#include +#include +#include +#include +#include + +#if __has_include ("cospike_dtm.h") +#define COSPIKE_DTM +#include "testchip_dtm.h" +extern testchip_dtm_t* dtm; +bool spike_loadarch_done = false; +#endif + +#if __has_include ("mm.h") +#define COSPIKE_SIMDRAM +#include "mm.h" +extern std::map backing_mem_data; +#endif #define CLINT_BASE (0x2000000) #define CLINT_SIZE (0x1000) @@ -20,6 +40,7 @@ typedef struct system_info_t { system_info_t* info = NULL; sim_t* sim = NULL; +bool cospike_debug; reg_t tohost_addr = 0; reg_t fromhost_addr = 0; std::set magic_addrs; @@ -42,7 +63,8 @@ extern "C" void cospike_set_sysinfo(char* isa, int pmpregions, ) { if (!info) { info = new system_info_t; - info->isa = std::string(isa); + // technically the targets aren't zicntr compliant, but they implement the zicntr registers + info->isa = std::string(isa) + "_zicntr"; info->pmpregions = pmpregions; info->mem0_base = mem0_base; info->mem0_size = mem0_size; @@ -64,10 +86,11 @@ extern "C" void cospike_cosim(long long int cycle, int raise_exception, int raise_interrupt, unsigned long long int cause, - unsigned long long int wdata) + unsigned long long int wdata, + int priv) { assert(info); - if (!sim) { + if (unlikely(!sim)) { printf("Configuring spike cosim\n"); std::vector mem_cfg; std::vector hartids; @@ -110,7 +133,7 @@ extern "C" void cospike_cosim(long long int cycle, abort(); std::vector htif_args; bool in_permissive = false; - bool cospike_debug = false; + cospike_debug = false; for (int i = 1; i < vinfo.argc; i++) { std::string arg(vinfo.argv[i]); if (arg == "+permissive") { @@ -136,7 +159,7 @@ extern "C" void cospike_cosim(long long int cycle, .support_impebreak = true }; - printf("%s\n", info->isa.c_str()); + printf("isa string is %s\n", info->isa.c_str()); for (int i = 0; i < htif_args.size(); i++) { printf("%s\n", htif_args[i].c_str()); } @@ -146,13 +169,29 @@ extern "C" void cospike_cosim(long long int cycle, plugin_devices, htif_args, dm_config, - nullptr, + "cospike.log", false, nullptr, false, nullptr ); +#ifdef COSPIKE_SIMDRAM + // match sim_t's backing memory with the SimDRAM memory + bus_t temp_mem_bus; + for (auto& pair : mems) temp_mem_bus.add_device(pair.first, pair.second); + + for (auto& pair : backing_mem_data) { + size_t base = pair.first; + size_t size = pair.second.size; + printf("Matching spike memory initial state for region %lx-%lx\n", base, base + size); + if (!temp_mem_bus.store(base, size, pair.second.data)) { + printf("Error, unable to match memory at address %lx\n", base); + abort(); + } + } +#endif + sim->configure_log(true, true); // Use our own reset vector for (int i = 0; i < info->nharts; i++) { @@ -166,93 +205,207 @@ extern "C" void cospike_cosim(long long int cycle, fromhost_addr = ((htif_t*)sim)->get_fromhost_addr(); printf("Tohost : %lx\n", tohost_addr); printf("Fromhost: %lx\n", fromhost_addr); + printf("Memory base : %lx\n", info->mem0_base); + printf("Memory Size : %lx\n", info->mem0_size); + } + + if (priv & 0x4) { // debug + return; } processor_t* p = sim->get_core(hartid); state_t* s = p->get_state(); +#ifdef COSPIKE_DTM + if (dtm && dtm->loadarch_done && !spike_loadarch_done) { + printf("Restoring spike state from testchip_dtm loadarch\n"); + // copy the loadarch state into the cosim + loadarch_state_t &ls = dtm->loadarch_state[hartid]; + s->pc = ls.pc; + s->prv = ls.prv; + s->csrmap[CSR_MSTATUS]->write(s->csrmap[CSR_MSTATUS]->read() | MSTATUS_VS | MSTATUS_XS | MSTATUS_FS); +#define RESTORE(CSRID, csr) s->csrmap[CSRID]->write(ls.csr); + RESTORE(CSR_FCSR , fcsr); + RESTORE(CSR_VSTART , vstart); + RESTORE(CSR_VXSAT , vxsat); + RESTORE(CSR_VXRM , vxrm); + RESTORE(CSR_VCSR , vcsr); + RESTORE(CSR_VTYPE , vtype); + RESTORE(CSR_STVEC , stvec); + RESTORE(CSR_SSCRATCH , sscratch); + RESTORE(CSR_SEPC , sepc); + RESTORE(CSR_SCAUSE , scause); + RESTORE(CSR_STVAL , stval); + RESTORE(CSR_SATP , satp); + RESTORE(CSR_MSTATUS , mstatus); + RESTORE(CSR_MEDELEG , medeleg); + RESTORE(CSR_MIDELEG , mideleg); + RESTORE(CSR_MIE , mie); + RESTORE(CSR_MTVEC , mtvec); + RESTORE(CSR_MSCRATCH , mscratch); + RESTORE(CSR_MEPC , mepc); + RESTORE(CSR_MCAUSE , mcause); + RESTORE(CSR_MTVAL , mtval); + RESTORE(CSR_MIP , mip); + RESTORE(CSR_MCYCLE , mcycle); + RESTORE(CSR_MINSTRET , minstret); + if (ls.VLEN != p->VU.VLEN) { + printf("VLEN mismatch loadarch: $d != spike: $d\n", ls.VLEN, p->VU.VLEN); + abort(); + } + if (ls.ELEN != p->VU.ELEN) { + printf("ELEN mismatch loadarch: $d != spike: $d\n", ls.ELEN, p->VU.ELEN); + abort(); + } + for (size_t i = 0; i < 32; i++) { + s->XPR.write(i, ls.XPR[i]); + s->FPR.write(i, { (uint64_t)ls.FPR[i], (uint64_t)-1 }); + memcpy(p->VU.reg_file + i * ls.VLEN / 8, ls.VPR[i], ls.VLEN / 8); + } + spike_loadarch_done = true; + p->clear_waiting_for_interrupt(); + } +#endif uint64_t s_pc = s->pc; + uint64_t interrupt_cause = cause & 0x7FFFFFFFFFFFFFFF; + bool ssip_interrupt = interrupt_cause == 0x1; + bool msip_interrupt = interrupt_cause == 0x3; + bool debug_interrupt = interrupt_cause == 0xe; if (raise_interrupt) { printf("%d interrupt %lx\n", cycle, cause); - uint64_t interrupt_cause = cause & 0x7FFFFFFFFFFFFFFF; - if (interrupt_cause == 3) { + + if (ssip_interrupt) { + // do nothing + } else if (msip_interrupt) { s->mip->backdoor_write_with_mask(MIP_MSIP, MIP_MSIP); + } else if (debug_interrupt) { + return; } else { printf("Unknown interrupt %lx\n", interrupt_cause); + abort(); } } if (raise_exception) printf("%d exception %lx\n", cycle, cause); if (valid) { printf("%d Cosim: %lx", cycle, iaddr); - if (has_wdata) { - printf(" %lx", wdata); - } + // if (has_wdata) { + // printf(" s: %lx", wdata); + // } printf("\n"); } - if (valid || raise_interrupt || raise_exception) + if (valid || raise_interrupt || raise_exception) { p->step(1); + if (unlikely(cospike_debug)) { + printf("spike pc is %lx\n", s->pc); + printf("spike mstatus is %lx\n", s->mstatus->read()); + printf("spike mip is %lx\n", s->mip->read()); + printf("spike mie is %lx\n", s->mie->read()); + } + } - if (valid) { + if (valid && !raise_exception) { if (s_pc != iaddr) { - printf("%d PC mismatch %lx != %lx\n", cycle, s_pc, iaddr); + printf("%d PC mismatch spike %llx != DUT %llx\n", cycle, s_pc, iaddr); + if (unlikely(cospike_debug)) { + printf("spike mstatus is %lx\n", s->mstatus->read()); + printf("spike mcause is %lx\n", s->mcause->read()); + printf("spike mtval is %lx\n" , s->mtval->read()); + printf("spike mtinst is %lx\n", s->mtinst->read()); + } exit(1); } - // Try to remember magic_mem addrs, and ignore these in the future + auto& mem_write = s->log_mem_write; - if (!mem_write.empty() && tohost_addr && std::get<0>(mem_write[0]) == tohost_addr) { - reg_t wdata = std::get<1>(mem_write[0]); - if (wdata >= info->mem0_base && wdata < (info->mem0_base + info->mem0_size)) { - printf("Probable magic mem %x\n", wdata); - magic_addrs.insert(wdata); + auto& log = s->log_reg_write; + auto& mem_read = s->log_mem_read; + + for (auto memwrite : mem_write) { + reg_t waddr = std::get<0>(memwrite); + uint64_t w_data = std::get<1>(memwrite); + if ((waddr == CLINT_BASE + 4*hartid) && w_data == 0) { + s->mip->backdoor_write_with_mask(MIP_MSIP, 0); + } + // Try to remember magic_mem addrs, and ignore these in the future + if ( waddr == tohost_addr && w_data >= info->mem0_base && w_data < (info->mem0_base + info->mem0_size)) { + printf("Probable magic mem %lx\n", w_data); + magic_addrs.insert(w_data); + } + // Try to remember magic_mem addrs, and ignore these in the future + if ( waddr == tohost_addr && w_data >= info->mem0_base && w_data < (info->mem0_base + info->mem0_size)) { + printf("Probable magic mem %lx\n", w_data); + magic_addrs.insert(w_data); } } - if (has_wdata) { - auto& log = s->log_reg_write; - auto& mem_read = s->log_mem_read; + bool scalar_wb = false; + bool vector_wb = false; + uint32_t vector_cnt = 0; + + for (auto ®write : log) { + + //TODO: scaling to multi issue reads? reg_t mem_read_addr = mem_read.empty() ? 0 : std::get<0>(mem_read[0]); - for (auto regwrite : log) { - int rd = regwrite.first >> 4; - int type = regwrite.first & 0xf; - // 0 => int - // 1 => fp - // 2 => vec - // 3 => vec hint - // 4 => csr - if ((rd != 0 && type == 0) || type == 1) { - // Override reads from some CSRs - uint64_t csr_addr = (insn >> 20) & 0xfff; - bool csr_read = (insn & 0x7f) == 0x73; - if (csr_read) printf("CSR read %lx\n", csr_addr); - if (csr_read && ( - (csr_addr == 0x301) || // misa - (csr_addr == 0xf13) || // mimpid - (csr_addr == 0xf12) || // marchid - (csr_addr == 0xf11) || // mvendorid - (csr_addr == 0xb00) || // mcycle - (csr_addr == 0xb02) || // minstret - (csr_addr >= 0x3b0 && csr_addr <= 0x3ef) // pmpaddr - )) { - printf("CSR override\n"); - s->XPR.write(rd, wdata); - } else if (!mem_read.empty() && ((magic_addrs.count(mem_read_addr) || - (tohost_addr && mem_read_addr == tohost_addr) || - (fromhost_addr && mem_read_addr == fromhost_addr) || - (CLINT_BASE <= mem_read_addr && mem_read_addr < (CLINT_BASE + CLINT_SIZE)) - ))) { - // Don't check reads from tohost, reads from magic memory, or reads from clint - // Technically this could be buggy because log_mem_read only reports vaddrs, but - // no software ever should access tohost/fromhost/clint with vaddrs anyways - printf("Read override %lx\n", mem_read_addr); - s->XPR.write(rd, wdata); - } else if (wdata != regwrite.second.v[0]) { - printf("%d wdata mismatch reg %d %lx != %lx\n", cycle, rd, regwrite.second.v[0], wdata); - exit(1); - } - } + + int rd = regwrite.first >> 4; + int type = regwrite.first & 0xf; + + // 0 => int + // 1 => fp + // 2 => vec + // 3 => vec hint + // 4 => csr + + bool ignore_read = (!mem_read.empty() && + ((magic_addrs.count(mem_read_addr) || + (tohost_addr && mem_read_addr == tohost_addr) || + (fromhost_addr && mem_read_addr == fromhost_addr) || + (CLINT_BASE <= mem_read_addr && mem_read_addr < (CLINT_BASE + CLINT_SIZE))))); + + // check the type is compliant with writeback first + if ((type == 0 || type == 1)) + scalar_wb = true; + if (type == 2) { + vector_wb = true; } + if (type == 3) continue; + + + if ((rd != 0 && type == 0) || type == 1) { + // Override reads from some CSRs + uint64_t csr_addr = (insn >> 20) & 0xfff; + bool csr_read = (insn & 0x7f) == 0x73; + if (csr_read) + printf("CSR read %lx\n", csr_addr); + if (csr_read && ((csr_addr == 0xf13) || // mimpid + (csr_addr == 0xf12) || // marchid + (csr_addr == 0xf11) || // mvendorid + (csr_addr == 0xb00) || // mcycle + (csr_addr == 0xb02) || // minstret + (csr_addr >= 0x7a0 && csr_addr <= 0x7aa) || // debug trigger registers + (csr_addr >= 0x3b0 && csr_addr <= 0x3ef) // pmpaddr + )) { + printf("CSR override\n"); + s->XPR.write(rd, wdata); + } else if (ignore_read) { + // Don't check reads from tohost, reads from magic memory, or reads + // from clint Technically this could be buggy because log_mem_read + // only reports vaddrs, but no software ever should access + // tohost/fromhost/clint with vaddrs anyways + printf("Read override %lx\n", mem_read_addr); + s->XPR.write(rd, wdata); + } else if (wdata != regwrite.second.v[0]) { + printf("%d wdata mismatch reg %d %lx != %lx\n", cycle, rd, + regwrite.second.v[0], wdata); + exit(1); + } + } + + // TODO FIX: Rocketchip TracedInstruction.wdata should be Valid(UInt) + // if (scalar_wb ^ has_wdata) { + // printf("Scalar wdata behavior divergence between spike and DUT\n"); + // exit(-1); + // } } } } -// } diff --git a/generators/chipyard/src/main/resources/csrc/cospike_dtm.h b/generators/chipyard/src/main/resources/csrc/cospike_dtm.h new file mode 100644 index 00000000..e69de29b diff --git a/generators/chipyard/src/main/resources/csrc/cy-emulator.cc b/generators/chipyard/src/main/resources/csrc/cy-emulator.cc deleted file mode 100644 index 40b5a2fa..00000000 --- a/generators/chipyard/src/main/resources/csrc/cy-emulator.cc +++ /dev/null @@ -1,394 +0,0 @@ -// See LICENSE.SiFive for license details. -// See LICENSE.Berkeley for license details. - -#if VM_TRACE -#include -#if CY_FST_TRACE -#include "verilated_fst_c.h" -#else -#include "verilated.h" -#include "verilated_vcd_c.h" -#endif // CY_FST_TRACE -#endif // VM_TRACE -#include -#include -#include "remote_bitbang.h" -#include -#include -#include -#include -#include -#include -#include - -// For option parsing, which is split across this file, Verilog, and -// FESVR's HTIF, a few external files must be pulled in. The list of -// files and what they provide is enumerated: -// -// $RISCV/include/fesvr/htif.h: -// defines: -// - HTIF_USAGE_OPTIONS -// - HTIF_LONG_OPTIONS_OPTIND -// - HTIF_LONG_OPTIONS -// $(ROCKETCHIP_DIR)/generated-src(-debug)?/$(CONFIG).plusArgs: -// defines: -// - PLUSARG_USAGE_OPTIONS -// variables: -// - static const char * verilog_plusargs - -extern tsi_t* tsi; -extern dtm_t* dtm; -extern remote_bitbang_t * jtag; - -static uint64_t trace_count = 0; -bool verbose = false; -bool done_reset = false; - -void handle_sigterm(int sig) -{ - dtm->stop(); -} - -double sc_time_stamp() -{ - return trace_count; -} - -static void usage(const char * program_name) -{ - printf("Usage: %s [EMULATOR OPTION]... [VERILOG PLUSARG]... [HOST OPTION]... BINARY [TARGET OPTION]...\n", - program_name); - fputs("\ -Run a BINARY on the Rocket Chip emulator.\n\ -\n\ -Mandatory arguments to long options are mandatory for short options too.\n\ -\n\ -EMULATOR OPTIONS\n\ - -c, --cycle-count Print the cycle count before exiting\n\ - +cycle-count\n\ - -h, --help Display this help and exit\n\ - -m, --max-cycles=CYCLES Kill the emulation after CYCLES\n\ - +max-cycles=CYCLES\n\ - -s, --seed=SEED Use random number seed SEED\n\ - -r, --rbb-port=PORT Use PORT for remote bit bang (with OpenOCD and GDB) \n\ - If not specified, a random port will be chosen\n\ - automatically.\n\ - -V, --verbose Enable all Chisel printfs (cycle-by-cycle info)\n\ - +verbose\n\ -", stdout); -#if VM_TRACE == 0 - fputs("\ -\n\ -EMULATOR DEBUG OPTIONS (only supported in debug build -- try `make debug`)\n", - stdout); -#endif - fputs("\ - -v, --vcd=FILE, Write vcd trace to FILE (or '-' for stdout)\n\ - -x, --dump-start=CYCLE Start VCD tracing at CYCLE\n\ - +dump-start\n\ -", stdout); - fputs("\n" PLUSARG_USAGE_OPTIONS, stdout); - fputs("\n" HTIF_USAGE_OPTIONS, stdout); - printf("\n" -"EXAMPLES\n" -" - run a bare metal test:\n" -" %s $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add\n" -" - run a bare metal test showing cycle-by-cycle information:\n" -" %s +verbose $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add 2>&1 | spike-dasm\n" -#if VM_TRACE -" - run a bare metal test to generate a VCD waveform:\n" -" %s -v rv64ui-p-add.vcd $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add\n" -#endif -" - run an ELF (you wrote, called 'hello') using the proxy kernel:\n" -" %s pk hello\n", - program_name, program_name, program_name -#if VM_TRACE - , program_name -#endif - ); -} - -int main(int argc, char** argv) -{ - unsigned random_seed = (unsigned)time(NULL) ^ (unsigned)getpid(); - uint64_t max_cycles = -1; - int ret = 0; - bool print_cycles = false; - // Port numbers are 16 bit unsigned integers. - uint16_t rbb_port = 0; -#if VM_TRACE - const char* vcdfile_name = NULL; - FILE * vcdfile = NULL; - uint64_t start = 0; -#endif - int verilog_plusargs_legal = 1; - - int verilated_argc = 1; - char** verilated_argv = new char*[argc]; - verilated_argv[0] = argv[0]; - - opterr = 1; - - while (1) { - static struct option long_options[] = { - {"cycle-count", no_argument, 0, 'c' }, - {"help", no_argument, 0, 'h' }, - {"max-cycles", required_argument, 0, 'm' }, - {"seed", required_argument, 0, 's' }, - {"rbb-port", required_argument, 0, 'r' }, - {"verbose", no_argument, 0, 'V' }, - {"permissive", no_argument, 0, 'p' }, - {"permissive-off", no_argument, 0, 'o' }, -#if VM_TRACE - {"vcd", required_argument, 0, 'v' }, - {"dump-start", required_argument, 0, 'x' }, -#endif - HTIF_LONG_OPTIONS - }; - int option_index = 0; -#if VM_TRACE - int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:po", long_options, &option_index); -#else - int c = getopt_long(argc, argv, "-chm:s:r:Vpo", long_options, &option_index); -#endif - if (c == -1) break; - retry: - switch (c) { - // Process long and short EMULATOR options - case '?': usage(argv[0]); return 1; - case 'c': print_cycles = true; break; - case 'h': usage(argv[0]); return 0; - case 'm': max_cycles = atoll(optarg); break; - case 's': random_seed = atoi(optarg); break; - case 'r': rbb_port = atoi(optarg); break; - case 'V': verbose = true; break; - case 'p': opterr = 0; break; - case 'o': opterr = 1; break; -#if VM_TRACE - case 'v': { - vcdfile_name = optarg; - vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w"); - if (!vcdfile) { - std::cerr << "Unable to open " << optarg << " for VCD write\n"; - return 1; - } - break; - } - case 'x': start = atoll(optarg); break; -#endif - // Process legacy '+' EMULATOR arguments by replacing them with - // their getopt equivalents - case 1: { - std::string arg = optarg; - if (arg.substr(0, 1) != "+") { - optind--; - goto done_processing; - } - if (arg == "+verbose") - c = 'V'; - else if (arg.substr(0, 12) == "+max-cycles=") { - c = 'm'; - optarg = optarg+12; - } -#if VM_TRACE - else if (arg.substr(0, 12) == "+dump-start=") { - c = 'x'; - optarg = optarg+12; - } -#endif - else if (arg.substr(0, 12) == "+cycle-count") - c = 'c'; - else if (arg == "+permissive") - { - c = 'p'; - verilated_argv[verilated_argc++] = optarg; - } - else if (arg == "+permissive-off") - { - c = 'o'; - verilated_argv[verilated_argc++] = optarg; - } - // If we don't find a legacy '+' EMULATOR argument, it still could be - // a VERILOG_PLUSARG and not an error. - else if (verilog_plusargs_legal) { - const char ** plusarg = &verilog_plusargs[0]; - int legal_verilog_plusarg = 0; - while (*plusarg && (legal_verilog_plusarg == 0)){ - if (arg.substr(1, strlen(*plusarg)) == *plusarg) { - legal_verilog_plusarg = 1; - } - plusarg ++; - } - if (!legal_verilog_plusarg) { - verilog_plusargs_legal = 0; - } else { - c = 'P'; - } - goto retry; - } - // If we STILL don't find a legacy '+' argument, it still could be - // an HTIF (HOST) argument and not an error. If this is the case, then - // we're done processing EMULATOR and VERILOG arguments. - else { - static struct option htif_long_options [] = { HTIF_LONG_OPTIONS }; - struct option * htif_option = &htif_long_options[0]; - while (htif_option->name) { - if (arg.substr(1, strlen(htif_option->name)) == htif_option->name) { - optind--; - goto done_processing; - } - htif_option++; - } - if(opterr) { - std::cerr << argv[0] << ": invalid plus-arg (Verilog or HTIF) \"" - << arg << "\"\n"; - c = '?'; - } else { - c = 'P'; - } - } - goto retry; - } - case 'P': // Verilog PlusArg, add to the argument list for verilator environment - verilated_argv[verilated_argc++] = optarg; - break; - // Realize that we've hit HTIF (HOST) arguments or error out - default: - if (c >= HTIF_LONG_OPTIONS_OPTIND) { - optind--; - goto done_processing; - } - c = '?'; - goto retry; - } - } - -done_processing: - if (optind == argc) { - std::cerr << "No binary specified for emulator\n"; - usage(argv[0]); - return 1; - } - - // Copy remaining HTIF arguments (if any) and the binary file name into the verilator argument stack - while (optind < argc) verilated_argv[verilated_argc++] = argv[optind++]; - - if (verbose) - fprintf(stderr, "using random seed %u\n", random_seed); - - srand(random_seed); - srand48(random_seed); - - Verilated::randReset(2); - Verilated::commandArgs(verilated_argc, verilated_argv); - TEST_HARNESS *tile = new TEST_HARNESS; - -#if VM_TRACE - Verilated::traceEverOn(true); // Verilator must compute traced signals -#if CY_FST_TRACE - std::unique_ptr tfp(new VerilatedFstC); -#else - std::unique_ptr vcdfd(new VerilatedVcdFILE(vcdfile)); - std::unique_ptr tfp(new VerilatedVcdC(vcdfd.get())); -#endif // CY_FST_TRACE - if (vcdfile_name) { - tile->trace(tfp.get(), 99); // Trace 99 levels of hierarchy - tfp->open(vcdfile_name); - } -#endif // VM_TRACE - - // RocketChip currently only supports RBB port 0, so this needs to stay here - jtag = new remote_bitbang_t(rbb_port); - - signal(SIGTERM, handle_sigterm); - - bool dump; - // start reset off low so a rising edge triggers async reset - tile->reset = 0; - tile->clock = 0; - tile->eval(); - // reset for several cycles to handle pipelined reset - for (int i = 0; i < 100; i++) { - tile->reset = 1; - tile->clock = 0; - tile->eval(); -#if VM_TRACE - dump = tfp && trace_count >= start; - if (dump) - tfp->dump(static_cast(trace_count * 2)); -#endif - tile->clock = 1; - tile->eval(); -#if VM_TRACE - if (dump) - tfp->dump(static_cast(trace_count * 2 + 1)); -#endif - trace_count ++; - } - tile->reset = 0; - done_reset = true; - - do { - tile->clock = 0; - tile->eval(); -#if VM_TRACE - dump = tfp && trace_count >= start; - if (dump) - tfp->dump(static_cast(trace_count * 2)); -#endif - - tile->clock = 1; - tile->eval(); -#if VM_TRACE - if (dump) - tfp->dump(static_cast(trace_count * 2 + 1)); -#endif - trace_count++; - } - // for verilator multithreading. need to do 1 loop before checking if - // tsi exists, since tsi is created by verilated thread on the first - // serial_tick. - while ((!dtm || !dtm->done()) && - (!jtag || !jtag->done()) && - (!tsi || !tsi->done()) && - !tile->io_success && trace_count < max_cycles); - -#if VM_TRACE - if (tfp) - tfp->close(); - if (vcdfile) - fclose(vcdfile); -#endif - - if (dtm && dtm->exit_code()) - { - fprintf(stderr, "*** FAILED *** via dtm (code = %d, seed %d) after %ld cycles\n", dtm->exit_code(), random_seed, trace_count); - ret = dtm->exit_code(); - } - else if (tsi && tsi->exit_code()) - { - fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %ld cycles\n", tsi->exit_code(), random_seed, trace_count); - ret = tsi->exit_code(); - } - else if (jtag && jtag->exit_code()) - { - fprintf(stderr, "*** FAILED *** via jtag (code = %d, seed %d) after %ld cycles\n", jtag->exit_code(), random_seed, trace_count); - ret = jtag->exit_code(); - } - else if (trace_count == max_cycles) - { - fprintf(stderr, "*** FAILED *** via trace_count (timeout, seed %d) after %ld cycles\n", random_seed, trace_count); - ret = 2; - } - else if (verbose || print_cycles) - { - fprintf(stderr, "*** PASSED *** Completed after %ld cycles\n", trace_count); - } - - if (dtm) delete dtm; - if (tsi) delete tsi; - if (jtag) delete jtag; - if (tile) delete tile; - if (verilated_argv) delete[] verilated_argv; - return ret; -} diff --git a/generators/chipyard/src/main/resources/csrc/spiketile.cc b/generators/chipyard/src/main/resources/csrc/spiketile.cc index 4d2bb8a5..3b14079b 100644 --- a/generators/chipyard/src/main/resources/csrc/spiketile.cc +++ b/generators/chipyard/src/main/resources/csrc/spiketile.cc @@ -2,11 +2,23 @@ #include #include #include +#include +#include +#include #include #include #include #include +#if __has_include("spiketile_tsi.h") +#define SPIKETILE_HTIF_TSI +extern htif_t* tsi; +#endif +#if __has_include("spiketile_dtm.h") +#define SPIKETILE_HTIF_DTM +extern htif_t* dtm; +#endif + enum transfer_t { NToB, NToT, @@ -73,8 +85,18 @@ public: void dcache_b(uint64_t address, uint64_t source, int param); bool dcache_c(uint64_t *address, uint64_t* source, int* param, unsigned char* voluntary, unsigned char* has_data, uint64_t* data[8]); void dcache_d(uint64_t sourceid, uint64_t data[8], unsigned char has_data, unsigned char grantack); + + void tcm_a(uint64_t address, uint64_t data, uint32_t mask, uint32_t opcode, uint32_t size); + bool tcm_d(uint64_t *data); + + void loadmem(size_t base, const char* fname); + void drain_stq(); bool stq_empty() { return st_q.size() == 0; }; + void flush_icache(); + + const cfg_t &get_cfg() const { return cfg; } + const std::map& get_harts() const { return harts; } ~chipyard_simif_t() { }; chipyard_simif_t(size_t icache_ways, @@ -86,9 +108,18 @@ public: char* readonly_uncacheable, char* executable, size_t icache_sourceids, - size_t dcache_sourceids); + size_t dcache_sourceids, + size_t tcm_base, + size_t tcm_size, + const char* isastr, + size_t pmpregions); uint64_t cycle; bool use_stq; + htif_t *htif; + bool fast_clint; + cfg_t cfg; + std::map harts; + bool accessed_tofrom_host; private: bool handle_cache_access(reg_t addr, size_t len, uint8_t* load_bytes, @@ -133,6 +164,11 @@ private: uint64_t mmio_stdata; size_t mmio_len; uint64_t mmio_lddata; + + uint64_t tcm_base; + uint64_t tcm_size; + uint8_t* tcm; + std::vector tcm_q; }; class tile_t { @@ -163,6 +199,7 @@ extern "C" void spike_tile(int hartid, char* isa, int dcache_sets, int dcache_ways, char* cacheable, char* uncacheable, char* readonly_uncacheable, char* executable, int icache_sourceids, int dcache_sourceids, + long long int tcm_base, long long int tcm_size, long long int reset_vector, long long int ipc, long long int cycle, @@ -237,7 +274,18 @@ extern "C" void spike_tile(int hartid, char* isa, int* mmio_a_size, unsigned char mmio_d_valid, - long long int mmio_d_data + long long int mmio_d_data, + + unsigned char tcm_a_valid, + long long int tcm_a_address, + long long int tcm_a_data, + int tcm_a_mask, + int tcm_a_opcode, + int tcm_a_size, + + unsigned char* tcm_d_valid, + unsigned char tcm_d_ready, + long long int* tcm_d_data ) { if (!host) { @@ -248,36 +296,26 @@ extern "C" void spike_tile(int hartid, char* isa, if (tiles.find(hartid) == tiles.end()) { printf("Constructing spike processor_t\n"); isa_parser_t *isa_parser = new isa_parser_t(isa, "MSU"); + std::string* isastr = new std::string(isa); chipyard_simif_t* simif = new chipyard_simif_t(icache_ways, icache_sets, dcache_ways, dcache_sets, cacheable, uncacheable, readonly_uncacheable, executable, - icache_sourceids, dcache_sourceids); - std::string* isastr = new std::string(isa); - cfg_t* cfg = new cfg_t(std::make_pair(0, 0), - nullptr, - isastr->c_str(), - "MSU", - "vlen:128,elen:64", - false, - endianness_little, - pmpregions, - std::vector(), - std::vector(), - false, - 0); + icache_sourceids, dcache_sourceids, + tcm_base, tcm_size, + isastr->c_str(), pmpregions); processor_t* p = new processor_t(isa_parser, - cfg, + &simif->get_cfg(), simif, hartid, false, log_file->get(), sout); - - p->enable_log_commits(); + simif->harts[hartid] = p; s_vpi_vlog_info vinfo; if (!vpi_get_vlog_info(&vinfo)) abort(); + std::string loadmem_file = ""; for (int i = 1; i < vinfo.argc; i++) { std::string arg(vinfo.argv[i]); if (arg == "+spike-debug") { @@ -286,7 +324,18 @@ extern "C" void spike_tile(int hartid, char* isa, if (arg == "+spike-stq") { simif->use_stq = true; } + if (arg.find("+loadmem=") == 0) { + loadmem_file = arg.substr(strlen("+loadmem=")); + } + if (arg == "+spike-fast-clint") { + simif->fast_clint = true; + } + if (arg == "+spike-verbose") { + p->enable_log_commits(); + } } + if (loadmem_file != "" && tcm_size > 0) + simif->loadmem(tcm_base, loadmem_file.c_str()); p->reset(); p->get_state()->pc = reset_vector; @@ -296,11 +345,22 @@ extern "C" void spike_tile(int hartid, char* isa, tile_t* tile = tiles[hartid]; chipyard_simif_t* simif = tile->simif; processor_t* proc = tile->proc; +#if defined(SPIKETILE_HTIF_TSI) + if (!simif->htif && tsi) + simif->htif = tsi; +#endif +#if defined(SPIKETILE_HTIF_DTM) + if (!simif->htif && dtm) + simif->htif = dtm; +#endif simif->cycle = cycle; if (debug) { proc->halt_request = proc->HR_REGULAR; } + if (!debug && proc->halt_request != proc->HR_NONE) { + proc->halt_request = proc->HR_NONE; + } proc->get_state()->mip->backdoor_write_with_mask(MIP_MTIP, mtip ? MIP_MTIP : 0); proc->get_state()->mip->backdoor_write_with_mask(MIP_MSIP, msip ? MIP_MSIP : 0); @@ -309,6 +369,7 @@ extern "C" void spike_tile(int hartid, char* isa, tile->max_insns = ipc; uint64_t pre_insns = proc->get_state()->minstret->read(); + simif->accessed_tofrom_host = false; tile->spike_context.switch_to(); *insns_retired = proc->get_state()->minstret->read() - pre_insns; if (simif->use_stq) { @@ -357,6 +418,13 @@ extern "C" void spike_tile(int hartid, char* isa, if (mmio_d_valid) { simif->mmio_d(mmio_d_data); } + + if (tcm_a_valid) { + simif->tcm_a(tcm_a_address, tcm_a_data, tcm_a_mask, tcm_a_opcode, tcm_a_size); + } + if (tcm_d_ready) { + *tcm_d_valid = simif->tcm_d((uint64_t*)tcm_d_data); + } } @@ -369,14 +437,35 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways, char* readonly_uncacheable, char* executable, size_t ic_sourceids, - size_t dc_sourceids + size_t dc_sourceids, + size_t tcm_base, + size_t tcm_size, + const char* isastr, + size_t pmpregions ) : cycle(0), use_stq(false), + htif(nullptr), + fast_clint(false), + cfg(std::make_pair(0, 0), + nullptr, + isastr, + "MSU", + "vlen:128,elen:64", + false, + endianness_little, + pmpregions, + std::vector(), + std::vector(), + false, + 0), + accessed_tofrom_host(false), icache_ways(icache_ways), icache_sets(icache_sets), dcache_ways(dcache_ways), dcache_sets(dcache_sets), + tcm_base(tcm_base), + tcm_size(tcm_size), mmio_valid(false), mmio_inflight(false) { @@ -432,6 +521,14 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways, uint64_t size_int = std::stoul(size); executables.push_back(mem_region_t { base_int, size_int }); } + + tcm = (uint8_t*)malloc(tcm_size); +} + +void chipyard_simif_t::flush_icache() { + for (auto &w : icache) { + for (size_t i = 0; i < icache_sets; i++) w[i].state = NONE; + } } bool chipyard_simif_t::reservable(reg_t addr) { @@ -440,12 +537,20 @@ bool chipyard_simif_t::reservable(reg_t addr) { return true; } } + if (addr >= tcm_base && addr < tcm_base + tcm_size) { + return true; + } return false; } bool chipyard_simif_t::mmio_fetch(reg_t addr, size_t len, uint8_t* bytes) { bool executable = false; + if (addr >= tcm_base && addr < tcm_base + tcm_size) { + memcpy(bytes, tcm + addr - tcm_base, len); + return true; + } + for (auto& r: executables) { if (addr >= r.base && addr + len <= r.base + r.size) { executable = true; @@ -466,6 +571,16 @@ bool chipyard_simif_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes) { bool found = false; bool cacheable = false; bool readonly = false; + reg_t tohost_addr = htif ? htif->get_tohost_addr() : 0; + reg_t fromhost_addr = htif ? htif->get_fromhost_addr() : 0; + if (addr == tohost_addr || addr == fromhost_addr) { + accessed_tofrom_host = true; + } + + if (addr >= tcm_base && addr < tcm_base + tcm_size) { + memcpy(bytes, tcm + addr - tcm_base, len); + return true; + } for (auto& r: cacheables) { if (addr >= r.base && addr + len <= r.base + r.size) { cacheable = true; @@ -497,6 +612,8 @@ bool chipyard_simif_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes) { while (!handle_cache_access(addr, len, bytes, nullptr, LOAD)) { host->switch_to(); } + uint64_t lddata = 0; + memcpy(&lddata, bytes, len); } else { handle_mmio_access(addr, len, bytes, nullptr, LOAD, readonly); } @@ -523,6 +640,7 @@ void chipyard_simif_t::handle_mmio_access(reg_t addr, size_t len, mmio_st = type == STORE; if (type == STORE) { assert(len <= 8); + mmio_stdata = 0; memcpy(&mmio_stdata, store_bytes, len); } mmio_len = len; @@ -829,9 +947,21 @@ bool chipyard_simif_t::dcache_c(uint64_t* address, uint64_t* source, int* param, } bool chipyard_simif_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) { + reg_t tohost_addr = htif ? htif->get_tohost_addr() : 0; + reg_t fromhost_addr = htif ? htif->get_fromhost_addr() : 0; + + if (addr == tohost_addr || addr == fromhost_addr) { + accessed_tofrom_host = true; + } + + if (addr >= tcm_base && addr < tcm_base + tcm_size) { + memcpy(tcm + addr - tcm_base, bytes, len); + return true; + } + bool found = false; bool cacheable = false; - for (auto& r: cacheables) { + for (auto& r: cacheables) { if (addr >= r.base && addr + len <= r.base + r.size) { cacheable = true; found = true; @@ -849,6 +979,8 @@ bool chipyard_simif_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) return false; } if (cacheable) { + uint64_t temp = 0; + memcpy(&temp, bytes, len); if (use_stq) { assert(len <= 8); uint64_t stdata; @@ -899,27 +1031,104 @@ void chipyard_simif_t::dcache_d(uint64_t sourceid, uint64_t data[8], unsigned ch } } +void chipyard_simif_t::tcm_a(uint64_t address, uint64_t data, uint32_t mask, uint32_t opcode, uint32_t size) { + bool load = opcode == 4; + uint64_t rdata = 0; + memcpy(&rdata, tcm + address - tcm_base, 8); + tcm_q.push_back(rdata); + + if (!load) { + for (size_t i = 0; i < 8; i++) { + if ((mask >> i) & 1) { + memcpy(tcm + address - tcm_base + i, ((uint8_t*)&data) + i, 1); + } + } + } +} + +bool chipyard_simif_t::tcm_d(uint64_t* data) { + if (tcm_q.size() == 0) + return false; + *data = tcm_q[0]; + tcm_q.erase(tcm_q.begin()); + return true; +} + +void chipyard_simif_t::loadmem(size_t base, const char* fname) { + class loadmem_memif_t : public memif_t { + public: + loadmem_memif_t(chipyard_simif_t* _simif, size_t _start) : memif_t(nullptr), simif(_simif), start(_start) {} + void write(addr_t taddr, size_t len, const void* src) override + { + addr_t addr = taddr - start; + memcpy(simif->tcm + addr, src, len); + } + void read(addr_t taddr, size_t len, void* bytes) override { + assert(false); + } + endianness_t get_target_endianness() const override { + return endianness_little; + } + private: + chipyard_simif_t* simif; + size_t start; + } loadmem_memif(this, tcm_base); + + reg_t entry; + load_elf(fname, &loadmem_memif, &entry); +} + bool insn_should_fence(uint64_t bits) { uint8_t opcode = bits & 0x7f; return opcode == 0b0101111 || opcode == 0b0001111; } +bool insn_is_wfi(uint64_t bits) { + return bits == 0x10500073; +} + void spike_thread_main(void* arg) { tile_t* tile = (tile_t*) arg; + processor_t* proc = tile->proc; + chipyard_simif_t* simif = tile->simif; + state_t* state = proc->get_state(); while (true) { while (tile->max_insns == 0) { host->switch_to(); } while (tile->max_insns != 0) { // TODO: Fences don't work - // uint64_t last_bits = tile->proc->get_last_bits(); - // if (insn_should_fence(last_bits) && !tile->simif->stq_empty()) { + //uint64_t last_bits = proc->get_last_bits(); + // if (insn_should_fence(last_bits) && !simif->stq_empty()) { // host->switch_to(); // } - tile->proc->step(1); + uint64_t old_minstret = state->minstret->read(); + proc->step(1); tile->max_insns--; - tile->proc->get_state()->mcycle->write(tile->simif->cycle); + if (proc->is_waiting_for_interrupt()) { + if (simif->fast_clint) { + state->mip->backdoor_write_with_mask(MIP_MTIP, MIP_MTIP); + tile->max_insns = tile->max_insns <= 1 ? 0 : 1; + } else { + tile->max_insns = 0; + } + } + if (state->debug_mode) { + // TODO: Fix. This needs to apply the same hack as rocket-chip... + // JALRs in debug mode should flush the ICache. + // There is no API to determine if a JALR was executed, so hack the + // pc of the JALR in the debug rom here instead. + if (state->pc == 0x838) { + simif->flush_icache(); + } + } + + // If we get stuck in WFI, or we start polling tohost/fromhost, switch to host thread + if ((old_minstret == state->minstret->read()) || simif->accessed_tofrom_host) { + tile->max_insns = 0; + } + state->mcycle->write(simif->cycle); } } } diff --git a/generators/chipyard/src/main/resources/csrc/spiketile_dtm.h b/generators/chipyard/src/main/resources/csrc/spiketile_dtm.h new file mode 100644 index 00000000..e69de29b diff --git a/generators/chipyard/src/main/resources/csrc/spiketile_tsi.h b/generators/chipyard/src/main/resources/csrc/spiketile_tsi.h new file mode 100644 index 00000000..e69de29b diff --git a/generators/chipyard/src/main/resources/vsrc/cospike.v b/generators/chipyard/src/main/resources/vsrc/cospike.v index f9d2322c..824e8d35 100644 --- a/generators/chipyard/src/main/resources/vsrc/cospike.v +++ b/generators/chipyard/src/main/resources/vsrc/cospike.v @@ -16,7 +16,8 @@ import "DPI-C" function void cospike_cosim(input longint cycle, input bit raise_exception, input bit raise_interrupt, input longint cause, - input longint wdata + input longint wdata, + input int priv ); @@ -42,6 +43,7 @@ module SpikeCosim #( input [63:0] trace_0_cause, input trace_0_has_wdata, input [63:0] trace_0_wdata, + input [2:0] trace_0_priv, input trace_1_valid, input [63:0] trace_1_iaddr, @@ -50,7 +52,8 @@ module SpikeCosim #( input trace_1_interrupt, input [63:0] trace_1_cause, input trace_1_has_wdata, - input [63:0] trace_1_wdata + input [63:0] trace_1_wdata, + input [2:0] trace_1_priv ); initial begin @@ -62,12 +65,12 @@ module SpikeCosim #( if (trace_0_valid || trace_0_exception || trace_0_cause) begin cospike_cosim(cycle, hartid, trace_0_has_wdata, trace_0_valid, trace_0_iaddr, trace_0_insn, trace_0_exception, trace_0_interrupt, trace_0_cause, - trace_0_wdata); + trace_0_wdata, trace_0_priv); end if (trace_1_valid || trace_1_exception || trace_1_cause) begin cospike_cosim(cycle, hartid, trace_1_has_wdata, trace_1_valid, trace_1_iaddr, trace_1_insn, trace_1_exception, trace_1_interrupt, trace_1_cause, - trace_1_wdata); + trace_1_wdata, trace_1_priv); end end end diff --git a/generators/chipyard/src/main/resources/vsrc/spiketile.v b/generators/chipyard/src/main/resources/vsrc/spiketile.v index 87254e35..c78d7a0f 100644 --- a/generators/chipyard/src/main/resources/vsrc/spiketile.v +++ b/generators/chipyard/src/main/resources/vsrc/spiketile.v @@ -13,6 +13,8 @@ import "DPI-C" function void spike_tile(input int hartid, input string executable, input int icache_sourceids, input int dcache_sourceids, + input longint tcm_base, + input longint tcm_size, input longint reset_vector, input longint ipc, input longint cycle, @@ -89,7 +91,18 @@ import "DPI-C" function void spike_tile(input int hartid, output int mmio_a_size, input bit mmio_d_valid, - input longint mmio_d_data + input longint mmio_d_data, + + input bit tcm_a_valid, + input longint tcm_a_address, + input longint tcm_a_data, + input int tcm_a_mask, + input int tcm_a_opcode, + input int tcm_a_size, + + output bit tcm_d_valid, + input bit tcm_d_ready, + output longint tcm_d_data ); @@ -106,7 +119,9 @@ module SpikeBlackBox #( parameter READONLY_UNCACHEABLE, parameter EXECUTABLE, parameter ICACHE_SOURCEIDS, - parameter DCACHE_SOURCEIDS )( + parameter DCACHE_SOURCEIDS, + parameter TCM_BASE, + parameter TCM_SIZE)( input clock, input reset, input [63:0] reset_vector, @@ -185,7 +200,18 @@ module SpikeBlackBox #( output [31:0] mmio_a_size, input mmio_d_valid, - input [63:0] mmio_d_data + input [63:0] mmio_d_data, + + input tcm_a_valid, + input [63:0] tcm_a_address, + input [63:0] tcm_a_data, + input [31:0] tcm_a_mask, + input [31:0] tcm_a_opcode, + input [31:0] tcm_a_size, + + output tcm_d_valid, + input tcm_d_ready, + output [63:0] tcm_d_data ); longint __insns_retired; @@ -257,7 +283,13 @@ module SpikeBlackBox #( reg [63:0] __dcache_c_data_6_reg; reg [63:0] __dcache_c_data_7_reg; - + wire __tcm_d_ready; + bit __tcm_d_valid; + longint __tcm_d_data; + + reg __tcm_d_valid_reg; + reg [63:0] __tcm_d_data_reg; + always @(posedge clock) begin @@ -322,12 +354,18 @@ module SpikeBlackBox #( __dcache_c_data_6_reg <= 64'h0; __dcache_c_data_7 = 64'h0; __dcache_c_data_7_reg <= 64'h0; + + __tcm_d_valid = 1'b0; + __tcm_d_valid_reg <= 1'b0; + __tcm_d_data = 64'h0; + __tcm_d_data_reg <= 64'h0; spike_tile_reset(HARTID); end else begin spike_tile(HARTID, ISA, PMPREGIONS, ICACHE_SETS, ICACHE_WAYS, DCACHE_SETS, DCACHE_WAYS, CACHEABLE, UNCACHEABLE, READONLY_UNCACHEABLE, EXECUTABLE, ICACHE_SOURCEIDS, DCACHE_SOURCEIDS, + TCM_BASE, TCM_SIZE, reset_vector, ipc, cycle, __insns_retired, debug, mtip, msip, meip, seip, @@ -350,7 +388,10 @@ module SpikeBlackBox #( dcache_d_data_4, dcache_d_data_5, dcache_d_data_6, dcache_d_data_7, __mmio_a_ready, __mmio_a_valid, __mmio_a_address, __mmio_a_data, __mmio_a_store, __mmio_a_size, - mmio_d_valid, mmio_d_data + mmio_d_valid, mmio_d_data, + + tcm_a_valid, tcm_a_address, tcm_a_data, tcm_a_mask, tcm_a_opcode, tcm_a_size, + __tcm_d_valid, __tcm_d_ready, __tcm_d_data ); __insns_retired_reg <= __insns_retired; @@ -385,6 +426,10 @@ module SpikeBlackBox #( __mmio_a_data_reg <= __mmio_a_data; __mmio_a_store_reg <= __mmio_a_store; __mmio_a_size_reg <= __mmio_a_size; + + __tcm_d_valid_reg <= __tcm_d_valid; + __tcm_d_data_reg <= __tcm_d_data; + end end // always @ (posedge clock) assign insns_retired = __insns_retired_reg; @@ -424,6 +469,8 @@ module SpikeBlackBox #( assign mmio_a_size = __mmio_a_size_reg; assign __mmio_a_ready = mmio_a_ready; - + assign tcm_d_valid = __tcm_d_valid_reg; + assign tcm_d_data = __tcm_d_data_reg; + assign __tcm_d_ready = tcm_d_ready; endmodule; diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index 184f30f2..150221b6 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -6,7 +6,7 @@ import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup} import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} -import freechips.rocketchip.config.{Parameters, Field} +import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope} import freechips.rocketchip.util.{ResetCatchAndSync} import chipyard.iobinders._ diff --git a/generators/chipyard/src/main/scala/ConfigFinder.scala b/generators/chipyard/src/main/scala/ConfigFinder.scala new file mode 100644 index 00000000..dfee340d --- /dev/null +++ b/generators/chipyard/src/main/scala/ConfigFinder.scala @@ -0,0 +1,19 @@ +package chipyard + +import org.reflections.Reflections +import org.reflections.scanners.Scanners.SubTypes +import scala.jdk.CollectionConverters._ +import scala.collection.{SortedSet} + +import org.chipsalliance.cde.config.{Config} + +object ConfigFinder { + def main(args: Array[String]) = { + val reflections = new Reflections() + val classes = reflections.get(SubTypes.of(classOf[Config]).asClass()).asScala + val sortedClasses = SortedSet[String]() ++ classes.map(_.getName) + for (cls <- sortedClasses) { + println(cls) + } + } +} diff --git a/generators/chipyard/src/main/scala/Cospike.scala b/generators/chipyard/src/main/scala/Cospike.scala index 7b663b24..cee23413 100644 --- a/generators/chipyard/src/main/scala/Cospike.scala +++ b/generators/chipyard/src/main/scala/Cospike.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.experimental.{IntParam, StringParam, IO} import chisel3.util._ -import freechips.rocketchip.config.{Parameters, Field, Config} +import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.devices.tilelink._ @@ -18,7 +18,8 @@ case class SpikeCosimConfig( mem0_base: BigInt, mem0_size: BigInt, nharts: Int, - bootrom: String + bootrom: String, + has_dtm: Boolean ) class SpikeCosim(cfg: SpikeCosimConfig) extends BlackBox(Map( @@ -32,6 +33,7 @@ class SpikeCosim(cfg: SpikeCosimConfig) extends BlackBox(Map( { addResource("/csrc/cospike.cc") addResource("/vsrc/cospike.v") + if (cfg.has_dtm) addResource("/csrc/cospike_dtm.h") val io = IO(new Bundle { val clock = Input(Clock()) val reset = Input(Bool()) @@ -46,6 +48,7 @@ class SpikeCosim(cfg: SpikeCosimConfig) extends BlackBox(Map( val cause = UInt(64.W) val has_wdata = Bool() val wdata = UInt(64.W) + val priv = UInt(3.W) })) }) } @@ -64,12 +67,8 @@ object SpikeCosim require(trace.numInsns <= 2) cosim.io.cycle := cycle cosim.io.trace.map(t => { + t := DontCare t.valid := false.B - t.iaddr := 0.U - t.insn := 0.U - t.exception := false.B - t.interrupt := false.B - t.cause := 0.U }) cosim.io.hartid := hartid.U for (i <- 0 until trace.numInsns) { @@ -83,6 +82,7 @@ object SpikeCosim cosim.io.trace(i).cause := trace.insns(i).cause cosim.io.trace(i).has_wdata := trace.insns(i).wdata.isDefined.B cosim.io.trace(i).wdata := trace.insns(i).wdata.getOrElse(0.U) + cosim.io.trace(i).priv := trace.insns(i).priv } } } diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 2777ba36..6711eac7 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -4,7 +4,7 @@ import chisel3._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system._ -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.tilelink._ // ------------------------------------ @@ -14,7 +14,7 @@ import freechips.rocketchip.devices.tilelink._ // DOC include start: DigitalTop class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin - with testchipip.HasPeripheryBootAddrReg // Use programmable boot address register + with testchipip.CanHavePeripheryBootAddrReg // Use programmable boot address register with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 71eef713..8dd0020e 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -3,7 +3,7 @@ package chipyard.iobinders import chisel3._ import chisel3.experimental.{Analog, IO, DataMirror} -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.jtag.{JTAGIO} @@ -25,7 +25,6 @@ import barstools.iocell.chisel._ import testchipip._ import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import chipyard.{CanHaveMasterTLMemPort} -import chipyard.clocking.{HasChipyardPRCI, DividerOnlyClockGenerator} import scala.reflect.{ClassTag} @@ -51,6 +50,12 @@ case object IOBinders extends Field[Map[String, Seq[IOBinderFunction]]]( Map[String, Seq[IOBinderFunction]]().withDefaultValue(Nil) ) +case object DontTouchIOBindersPorts extends Field[Boolean](true) + +class WithDontTouchIOBinders(b: Boolean = true) extends Config((site, here, up) => { + case DontTouchIOBindersPorts => b +}) + abstract trait HasIOBinders { this: LazyModule => val lazySystem: LazyModule private val iobinders = p(IOBinders) @@ -67,10 +72,33 @@ abstract trait HasIOBinders { this: LazyModule => }) // A publicly accessible list of IO cells (useful for a floorplanning tool, for example) - lazy val iocells = (lzyFlattened.values ++ impFlattened.values).unzip._2.flatten.toBuffer + val iocells = InModuleBody { (lzyFlattened.values ++ impFlattened.values).unzip._2.flatten.toBuffer } // A mapping between stringified DigitalSystem traits and their corresponding ChipTop ports - lazy val portMap = iobinders.keys.map(k => k -> (lzyFlattened(k)._1 ++ impFlattened(k)._1)).toMap + val portMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._1 ++ impFlattened(k)._1)).toMap } + + // A mapping between stringified DigitalSystem traits and their corresponding ChipTop iocells + val iocellMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._2 ++ impFlattened(k)._2)).toMap } + + InModuleBody { + if (p(DontTouchIOBindersPorts)) { + portMap.values.foreach(_.foreach(dontTouch(_))) + } + + println("IOCells generated by IOBinders:") + for ((k, v) <- iocellMap) { + if (!v.isEmpty) { + val cells = v.map(_.getClass.getSimpleName).groupBy(identity).mapValues(_.size) + + println(s" IOBinder for $k generated:") + for ((t, c) <- cells) { println(s" $c X $t") } + } + } + println() + val totals = iocells.map(_.getClass.getSimpleName).groupBy(identity).mapValues(_.size) + println(s" Total generated ${iocells.size} IOCells:") + for ((t, c) <- totals) { println(s" $c X $t") } + } } // Note: The parameters instance is accessible only through LazyModule @@ -219,7 +247,7 @@ class WithDebugIOCells extends OverrideLazyIOBinder({ def clockBundle = clockSinkNode.get.in.head._1 - InModuleBody { system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripheryDebugModuleImp => { + InModuleBody { system.asInstanceOf[BaseSubsystem] match { case system: HasPeripheryDebug => { system.debug.map({ debug => // We never use the PSDIO, so tie it off on-chip system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) } @@ -396,45 +424,4 @@ class WithDontTouchPorts extends OverrideIOBinder({ (system: DontTouch) => system.dontTouchPorts(); (Nil, Nil) }) -class ClockWithFreq(val freqMHz: Double) extends Bundle { - val clock = Clock() -} -class WithDividerOnlyClockGenerator extends OverrideLazyIOBinder({ - (system: HasChipyardPRCI) => { - // Connect the implicit clock - implicit val p = GetSystemParameters(system) - val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) - system.connectImplicitClockSinkNode(implicitClockSinkNode) - InModuleBody { - val implicit_clock = implicitClockSinkNode.in.head._1.clock - val implicit_reset = implicitClockSinkNode.in.head._1.reset - system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => { - l.clock := implicit_clock - l.reset := implicit_reset - }} - } - - // Connect all other requested clocks - val referenceClockSource = ClockSourceNode(Seq(ClockSourceParameters())) - val dividerOnlyClockGen = LazyModule(new DividerOnlyClockGenerator("buildTopClockGenerator")) - - (system.allClockGroupsNode - := dividerOnlyClockGen.node - := referenceClockSource) - - InModuleBody { - val clock_wire = Wire(Input(new ClockWithFreq(dividerOnlyClockGen.module.referenceFreq))) - val reset_wire = Wire(Input(AsyncReset())) - val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey)) - val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey)) - - referenceClockSource.out.unzip._1.map { o => - o.clock := clock_wire.clock - o.reset := reset_wire - } - - (Seq(clock_io, reset_io), clockIOCell ++ resetIOCell) - } - } -}) diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala index c7e5b69d..c6ec13ae 100644 --- a/generators/chipyard/src/main/scala/SpikeTile.scala +++ b/generators/chipyard/src/main/scala/SpikeTile.scala @@ -4,9 +4,10 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.{IntParam, StringParam, IO} -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.devices.debug.{ExportDebug, DMI} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket._ import freechips.rocketchip.tilelink._ @@ -15,8 +16,7 @@ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci.ClockSinkParameters -case class SpikeCoreParams( -) extends CoreParams { +case class SpikeCoreParams() extends CoreParams { val useVM = true val useHypervisor = false val useSupervisor = true @@ -79,7 +79,8 @@ case class SpikeTileParams( hartId: Int = 0, val core: SpikeCoreParams = SpikeCoreParams(), icacheParams: ICacheParams = ICacheParams(nWays = 32), - dcacheParams: DCacheParams = DCacheParams(nWays = 32) + dcacheParams: DCacheParams = DCacheParams(nWays = 32), + tcmParams: Option[MasterPortParams] = None // tightly coupled memory ) extends InstantiableTileParams[SpikeTile] { val name = Some("spike_tile") @@ -145,6 +146,27 @@ class SpikeTile( sourceId = IdRange(0, 1), requestFifo = true)))))) + tlSlaveXbar.node :*= slaveNode + val tcmNode = spikeTileParams.tcmParams.map { tcmP => + val device = new MemoryDevice + val base = AddressSet.misaligned(tcmP.base, tcmP.size) + val tcmNode = TLManagerNode(Seq(TLSlavePortParameters.v1( + managers = Seq(TLSlaveParameters.v1( + address = base, + resources = device.reg, + regionType = RegionType.IDEMPOTENT, // not cacheable + executable = true, + supportsGet = TransferSizes(1, 8), + supportsPutFull = TransferSizes(1, 8), + supportsPutPartial = TransferSizes(1, 8), + fifoId = Some(0) + )), + beatBytes = 8 + ))) + connectTLSlave(tcmNode := TLBuffer(), 8) + tcmNode + } + tlOtherMastersNode := TLBuffer() := tlMasterXbar.node masterNode :=* tlOtherMastersNode tlMasterXbar.node := TLWidthWidget(64) := TLBuffer():= icacheNode @@ -166,7 +188,10 @@ class SpikeBlackBox( cacheable_regions: String, uncacheable_regions: String, readonly_uncacheable_regions: String, - executable_regions: String) extends BlackBox(Map( + executable_regions: String, + tcm_base: BigInt, + tcm_size: BigInt, + use_dtm: Boolean) extends BlackBox(Map( "HARTID" -> IntParam(hartId), "ISA" -> StringParam(isa), "PMPREGIONS" -> IntParam(pmpregions), @@ -179,7 +204,9 @@ class SpikeBlackBox( "UNCACHEABLE" -> StringParam(uncacheable_regions), "READONLY_UNCACHEABLE" -> StringParam(readonly_uncacheable_regions), "CACHEABLE" -> StringParam(cacheable_regions), - "EXECUTABLE" -> StringParam(executable_regions) + "EXECUTABLE" -> StringParam(executable_regions), + "TCM_BASE" -> IntParam(tcm_base), + "TCM_SIZE" -> IntParam(tcm_size) )) with HasBlackBoxResource { val io = IO(new Bundle { @@ -258,10 +285,30 @@ class SpikeBlackBox( val data = Input(UInt(64.W)) } } + + val tcm = new Bundle { + val a = new Bundle { + val valid = Input(Bool()) + val address = Input(UInt(64.W)) + val data = Input(UInt(64.W)) + val mask = Input(UInt(32.W)) + val opcode = Input(UInt(32.W)) + val size = Input(UInt(32.W)) + } + val d = new Bundle { + val valid = Output(Bool()) + val ready = Input(Bool()) + val data = Output(UInt(64.W)) + } + } }) addResource("/vsrc/spiketile.v") addResource("/csrc/spiketile.cc") - + if (use_dtm) { + addResource("/csrc/spiketile_dtm.h") + } else { + addResource("/csrc/spiketile_tsi.h") + } } class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { @@ -285,11 +332,19 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { val (dcache_tl, dcacheEdge) = outer.dcacheNode.out(0) val (mmio_tl, mmioEdge) = outer.mmioNode.out(0) + // Note: This assumes that if the debug module exposes the ClockedDMI port, + // then the DTM-based bringup with SimDTM will be used. This isn't required to be + // true, but it usually is + val useDTM = p(ExportDebug).protocols.contains(DMI) val spike = Module(new SpikeBlackBox(hartId, isaDTS, tileParams.core.nPMPs, tileParams.icache.get.nSets, tileParams.icache.get.nWays, tileParams.dcache.get.nSets, tileParams.dcache.get.nWays, tileParams.dcache.get.nMSHRs, - cacheable_regions, uncacheable_regions, readonly_uncacheable_regions, executable_regions)) + cacheable_regions, uncacheable_regions, readonly_uncacheable_regions, executable_regions, + outer.spikeTileParams.tcmParams.map(_.base).getOrElse(0), + outer.spikeTileParams.tcmParams.map(_.size).getOrElse(0), + useDTM + )) spike.io.clock := clock.asBool val cycle = RegInit(0.U(64.W)) cycle := cycle + 1.U @@ -304,64 +359,63 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { spike.io.msip := int_bundle.msip spike.io.meip := int_bundle.meip spike.io.seip := int_bundle.seip.get - spike.io.ipc := PlusArg("spike-ipc", 10000, width=64) + spike.io.ipc := PlusArg("spike-ipc", width=32, default=10000) val blockBits = log2Ceil(p(CacheBlockBytes)) - - val icache_a_q = Module(new Queue(new TLBundleA(icacheEdge.bundle), 1, flow=true, pipe=true)) - spike.io.icache.a.ready := icache_a_q.io.enq.ready && icache_a_q.io.count === 0.U - icache_tl.a <> icache_a_q.io.deq - icache_a_q.io.enq.valid := spike.io.icache.a.valid - icache_a_q.io.enq.bits := icacheEdge.Get( + spike.io.icache.a.ready := icache_tl.a.ready + icache_tl.a.valid := spike.io.icache.a.valid + icache_tl.a.bits := icacheEdge.Get( fromSource = spike.io.icache.a.sourceid, toAddress = (spike.io.icache.a.address >> blockBits) << blockBits, lgSize = blockBits.U)._2 - icache_tl.d.ready := true.B spike.io.icache.d.valid := icache_tl.d.valid spike.io.icache.d.sourceid := icache_tl.d.bits.source spike.io.icache.d.data := icache_tl.d.bits.data.asTypeOf(Vec(8, UInt(64.W))) - val dcache_a_q = Module(new Queue(new TLBundleA(dcacheEdge.bundle), 1, flow=true, pipe=true)) - spike.io.dcache.a.ready := dcache_a_q.io.enq.ready && dcache_a_q.io.count === 0.U - dcache_tl.a <> dcache_a_q.io.deq - dcache_a_q.io.enq.valid := spike.io.dcache.a.valid - dcache_a_q.io.enq.bits := dcacheEdge.AcquireBlock( - fromSource = spike.io.dcache.a.sourceid, - toAddress = (spike.io.dcache.a.address >> blockBits) << blockBits, - lgSize = blockBits.U, - growPermissions = Mux(spike.io.dcache.a.state_old, 2.U, Mux(spike.io.dcache.a.state_new, 1.U, 0.U)))._2 - + spike.io.dcache.a.ready := dcache_tl.a.ready + dcache_tl.a.valid := spike.io.dcache.a.valid + if (dcacheEdge.manager.anySupportAcquireB) { + dcache_tl.a.bits := dcacheEdge.AcquireBlock( + fromSource = spike.io.dcache.a.sourceid, + toAddress = (spike.io.dcache.a.address >> blockBits) << blockBits, + lgSize = blockBits.U, + growPermissions = Mux(spike.io.dcache.a.state_old, 2.U, Mux(spike.io.dcache.a.state_new, 1.U, 0.U)))._2 + } else { + dcache_tl.a.bits := DontCare + } dcache_tl.b.ready := true.B spike.io.dcache.b.valid := dcache_tl.b.valid spike.io.dcache.b.address := dcache_tl.b.bits.address spike.io.dcache.b.source := dcache_tl.b.bits.source spike.io.dcache.b.param := dcache_tl.b.bits.param - val dcache_c_q = Module(new Queue(new TLBundleC(dcacheEdge.bundle), 1, flow=true, pipe=true)) - spike.io.dcache.c.ready := dcache_c_q.io.enq.ready && dcache_c_q.io.count === 0.U - dcache_tl.c <> dcache_c_q.io.deq - dcache_c_q.io.enq.valid := spike.io.dcache.c.valid - dcache_c_q.io.enq.bits := Mux(spike.io.dcache.c.voluntary, - dcacheEdge.Release( - fromSource = spike.io.dcache.c.sourceid, - toAddress = spike.io.dcache.c.address, - lgSize = blockBits.U, - shrinkPermissions = spike.io.dcache.c.param, - data = spike.io.dcache.c.data.asUInt)._2, - Mux(spike.io.dcache.c.has_data, - dcacheEdge.ProbeAck( + spike.io.dcache.c.ready := dcache_tl.c.ready + dcache_tl.c.valid := spike.io.dcache.c.valid + if (dcacheEdge.manager.anySupportAcquireB) { + dcache_tl.c.bits := Mux(spike.io.dcache.c.voluntary, + dcacheEdge.Release( fromSource = spike.io.dcache.c.sourceid, toAddress = spike.io.dcache.c.address, lgSize = blockBits.U, - reportPermissions = spike.io.dcache.c.param, - data = spike.io.dcache.c.data.asUInt), - dcacheEdge.ProbeAck( - fromSource = spike.io.dcache.c.sourceid, - toAddress = spike.io.dcache.c.address, - lgSize = blockBits.U, - reportPermissions = spike.io.dcache.c.param) - )) + shrinkPermissions = spike.io.dcache.c.param, + data = spike.io.dcache.c.data.asUInt)._2, + Mux(spike.io.dcache.c.has_data, + dcacheEdge.ProbeAck( + fromSource = spike.io.dcache.c.sourceid, + toAddress = spike.io.dcache.c.address, + lgSize = blockBits.U, + reportPermissions = spike.io.dcache.c.param, + data = spike.io.dcache.c.data.asUInt), + dcacheEdge.ProbeAck( + fromSource = spike.io.dcache.c.sourceid, + toAddress = spike.io.dcache.c.address, + lgSize = blockBits.U, + reportPermissions = spike.io.dcache.c.param) + )) + } else { + dcache_tl.c.bits := DontCare + } val has_data = dcacheEdge.hasData(dcache_tl.d.bits) val should_finish = dcacheEdge.isRequest(dcache_tl.d.bits) @@ -376,12 +430,10 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { dcache_tl.e.valid := dcache_tl.d.valid && should_finish dcache_tl.e.bits := dcacheEdge.GrantAck(dcache_tl.d.bits) - val mmio_a_q = Module(new Queue(new TLBundleA(mmioEdge.bundle), 1, flow=true, pipe=true)) - spike.io.mmio.a.ready := mmio_a_q.io.enq.ready && mmio_a_q.io.count === 0.U - mmio_tl.a <> mmio_a_q.io.deq - mmio_a_q.io.enq.valid := spike.io.mmio.a.valid - val log_size = MuxCase(0.U, (0 until 3).map { i => (spike.io.mmio.a.size === (1 << i).U) -> i.U }) - mmio_a_q.io.enq.bits := Mux(spike.io.mmio.a.store, + spike.io.mmio.a.ready := mmio_tl.a.ready + mmio_tl.a.valid := spike.io.mmio.a.valid + val log_size = (0 until 4).map { i => Mux(spike.io.mmio.a.size === (1 << i).U, i.U, 0.U) }.reduce(_|_) + mmio_tl.a.bits := Mux(spike.io.mmio.a.store, mmioEdge.Put(0.U, spike.io.mmio.a.address, log_size, spike.io.mmio.a.data)._2, mmioEdge.Get(0.U, spike.io.mmio.a.address, log_size)._2) @@ -389,9 +441,33 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { spike.io.mmio.d.valid := mmio_tl.d.valid spike.io.mmio.d.data := mmio_tl.d.bits.data + spike.io.tcm := DontCare + spike.io.tcm.a.valid := false.B + spike.io.tcm.d.ready := true.B + outer.tcmNode.map { tcmNode => + val (tcm_tl, tcmEdge) = tcmNode.in(0) + val debug_tcm_tl = WireInit(tcm_tl) + dontTouch(debug_tcm_tl) + tcm_tl.a.ready := true.B + spike.io.tcm.a.valid := tcm_tl.a.valid + spike.io.tcm.a.address := tcm_tl.a.bits.address + spike.io.tcm.a.data := tcm_tl.a.bits.data + spike.io.tcm.a.mask := tcm_tl.a.bits.mask + spike.io.tcm.a.opcode := tcm_tl.a.bits.opcode + spike.io.tcm.a.size := tcm_tl.a.bits.size + + spike.io.tcm.d.ready := tcm_tl.d.ready + tcm_tl.d.bits := tcmEdge.AccessAck(RegNext(tcm_tl.a.bits)) + when (RegNext(tcm_tl.a.bits.opcode === TLMessages.Get)) { + tcm_tl.d.bits.opcode := TLMessages.AccessAckData + } + tcm_tl.d.valid := spike.io.tcm.d.valid + tcm_tl.d.bits.data := spike.io.tcm.d.data + } } -class WithNSpikeCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => { +class WithNSpikeCores(n: Int = 1, tileParams: SpikeTileParams = SpikeTileParams(), + overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => { // Calculate the next available hart ID (since hart ID cannot be duplicated) val prev = up(TilesLocated(InSubsystem), site) @@ -399,8 +475,21 @@ class WithNSpikeCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends // Create TileAttachParams for every core to be instantiated (0 until n).map { i => SpikeTileAttachParams( - tileParams = SpikeTileParams(hartId = i + idOffset) + tileParams = tileParams.copy(hartId = i + idOffset) ) } ++ prev } }) + +class WithSpikeTCM extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => { + val prev = up(TilesLocated(InSubsystem)) + require(prev.size == 1) + val spike = prev(0).asInstanceOf[SpikeTileAttachParams] + Seq(spike.copy(tileParams = spike.tileParams.copy( + tcmParams = Some(up(ExtMem).get.master) + ))) + } + case ExtMem => None + case BankedL2Key => up(BankedL2Key).copy(nBanks = 0) +}) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 34175d39..e98a51bc 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -9,9 +9,10 @@ import chisel3._ import chisel3.internal.sourceinfo.{SourceInfo} import freechips.rocketchip.prci._ -import freechips.rocketchip.config.{Field, Parameters} +import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey} +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, ExportDebug, DebugModuleKey} +import sifive.blocks.devices.uart.{HasPeripheryUART, PeripheryUARTKey} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ @@ -45,9 +46,35 @@ trait CanHaveHTIF { this: BaseSubsystem => } } +// This trait adds the "chosen" node to DTS, which +// can be used to pass information to OS about the earlycon +case object ChosenInDTS extends Field[Boolean](true) +trait CanHaveChosenInDTS { this: BaseSubsystem => + if (p(ChosenInDTS)) { + this match { + case t: HasPeripheryUART if (!p(PeripheryUARTKey).isEmpty) => { + val chosen = new Device { + def describe(resources: ResourceBindings): Description = { + val stdout = resources("stdout").map(_.value) + Description("chosen", resources("uart").headOption.map { case Binding(_, value) => + "stdout-path" -> Seq(value) + }.toMap) + } + } + ResourceBinding { + t.uarts.foreach(u => Resource(chosen, "uart").bind(ResourceAlias(u.device.label))) + } + } + case _ => + } + } +} + class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem with HasTiles + with HasPeripheryDebug with CanHaveHTIF + with CanHaveChosenInDTS { def coreMonitorBundles = tiles.map { case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index 827b97c0..5643e380 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -7,7 +7,7 @@ package chipyard import chisel3._ -import freechips.rocketchip.config.{Parameters, Field} +import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ @@ -31,6 +31,14 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) } val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) } + + // If there is no bootrom, the tile reset vector bundle will be tied to zero + if (bootROM.isEmpty) { + val fakeResetVectorSourceNode = BundleBridgeSource[UInt]() + InModuleBody { fakeResetVectorSourceNode.bundle := 0.U } + tileResetVectorNexusNode := fakeResetVectorSourceNode + } + override lazy val module = new ChipyardSystemModule(this) } diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala deleted file mode 100644 index 240ae5cc..00000000 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ /dev/null @@ -1,108 +0,0 @@ -package chipyard - -import chisel3._ - -import scala.collection.mutable.{ArrayBuffer, LinkedHashMap} -import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.util.{ResetCatchAndSync} -import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters} - -import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} -import chipyard.iobinders.HasIOBinders -import chipyard.clocking.{SimplePllConfiguration, ClockDividerN} - -// ------------------------------- -// Chipyard Test Harness -// ------------------------------- - -case object BuildTop extends Field[Parameters => LazyModule]((p: Parameters) => new ChipTop()(p)) -case object DefaultClockFrequencyKey extends Field[Double](100.0) // MHz - -trait HasHarnessSignalReferences { - implicit val p: Parameters - // clock/reset of the chiptop reference clock (can be different than the implicit harness clock/reset) - var refClockFreq: Double = p(DefaultClockFrequencyKey) - def setRefClockFreq(freqMHz: Double) = { refClockFreq = freqMHz } - def getRefClockFreq: Double = refClockFreq - def buildtopClock: Clock - def buildtopReset: Reset - def success: Bool -} - -class HarnessClockInstantiator { - private val _clockMap: LinkedHashMap[String, (Double, ClockBundle)] = LinkedHashMap.empty - - // request a clock bundle at a particular frequency - def requestClockBundle(name: String, freqRequested: Double): ClockBundle = { - val clockBundle = Wire(new ClockBundle(ClockBundleParameters())) - _clockMap(name) = (freqRequested, clockBundle) - clockBundle - } - - // connect all clock wires specified to a divider only PLL - def instantiateHarnessDividerPLL(refClock: ClockBundle): Unit = { - val sinks = _clockMap.map({ case (name, (freq, bundle)) => - ClockSinkParameters(take=Some(ClockParameters(freqMHz=freq / (1000 * 1000))), name=Some(name)) - }).toSeq - - val pllConfig = new SimplePllConfiguration("harnessDividerOnlyClockGenerator", sinks) - pllConfig.emitSummaries() - - val dividedClocks = LinkedHashMap[Int, Clock]() - def instantiateDivider(div: Int): Clock = { - val divider = Module(new ClockDividerN(div)) - divider.suggestName(s"ClockDivideBy${div}") - divider.io.clk_in := refClock.clock - dividedClocks(div) = divider.io.clk_out - divider.io.clk_out - } - - // connect wires to clock source - for (sinkParams <- sinks) { - // bypass the reference freq. (don't create a divider + reset sync) - val (divClock, divReset) = if (sinkParams.take.get.freqMHz != pllConfig.referenceFreqMHz) { - val div = pllConfig.sinkDividerMap(sinkParams) - val divClock = dividedClocks.getOrElse(div, instantiateDivider(div)) - (divClock, ResetCatchAndSync(divClock, refClock.reset.asBool)) - } else { - (refClock.clock, refClock.reset) - } - - _clockMap(sinkParams.name.get)._2.clock := divClock - _clockMap(sinkParams.name.get)._2.reset := divReset - } - } -} - -case object HarnessClockInstantiatorKey extends Field[HarnessClockInstantiator](new HarnessClockInstantiator) - -class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSignalReferences { - val io = IO(new Bundle { - val success = Output(Bool()) - }) - - val buildtopClock = Wire(Clock()) - val buildtopReset = Wire(Reset()) - - val lazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") - val dut = Module(lazyDut.module) - - io.success := false.B - - val success = io.success - - lazyDut match { case d: HasIOBinders => - ApplyHarnessBinders(this, d.lazySystem, d.portMap) - } - - val refClkBundle = p(HarnessClockInstantiatorKey).requestClockBundle("buildtop_reference_clock", getRefClockFreq * (1000 * 1000)) - - buildtopClock := refClkBundle.clock - buildtopReset := WireInit(refClkBundle.reset) - - val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters())) - implicitHarnessClockBundle.clock := clock - implicitHarnessClockBundle.reset := reset - p(HarnessClockInstantiatorKey).instantiateHarnessDividerPLL(implicitHarnessClockBundle) -} diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index a47ae425..0e4e3310 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -4,7 +4,7 @@ import scala.collection.mutable.{LinkedHashSet} import freechips.rocketchip.subsystem._ import freechips.rocketchip.tile.{XLen, TileParams} -import freechips.rocketchip.config.{Parameters, Field, Config} +import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite} /** diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala new file mode 100644 index 00000000..5a53051e --- /dev/null +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -0,0 +1,123 @@ +package chipyard.clocking + +import chisel3._ +import chisel3.util._ +import chipyard.iobinders.{OverrideLazyIOBinder, GetSystemParameters, IOCellKey} +import freechips.rocketchip.prci._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.tilelink._ +import barstools.iocell.chisel._ + +class ClockWithFreq(val freqMHz: Double) extends Bundle { + val clock = Clock() +} + +// This uses the FakePLL, which uses a ClockAtFreq Verilog blackbox to generate +// the requested clocks. This also adds TileLink ClockDivider and ClockSelector +// blocks, which allow memory-mapped control of clock division, and clock muxing +// between the FakePLL and the slow off-chip clock +// Note: This will not simulate properly with firesim +class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ + (system: HasChipyardPRCI) => { + // Connect the implicit clock + implicit val p = GetSystemParameters(system) + val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) + system.connectImplicitClockSinkNode(implicitClockSinkNode) + InModuleBody { + val implicit_clock = implicitClockSinkNode.in.head._1.clock + val implicit_reset = implicitClockSinkNode.in.head._1.reset + system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => { + l.clock := implicit_clock + l.reset := implicit_reset + }} + } + val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(system.prciParams.slaveWhere) + val baseAddress = system.prciParams.baseAddress + val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes)) } + val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) } + val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) } + + tlbus.toVariableWidthSlave(Some("clock-div-ctrl")) { clockDivider.tlNode := TLBuffer() } + tlbus.toVariableWidthSlave(Some("clock-sel-ctrl")) { clockSelector.tlNode := TLBuffer() } + tlbus.toVariableWidthSlave(Some("pll-ctrl")) { pllCtrl.tlNode := TLBuffer() } + + system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode + + // Connect all other requested clocks + val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters())) + val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters())) + + // The order of the connections to clockSelector.clockNode configures the inputs + // of the clockSelector's clockMux. Default to using the slowClockSource, + // software should enable the PLL, then switch to the pllClockSource + clockSelector.clockNode := slowClockSource + clockSelector.clockNode := pllClockSource + + val pllCtrlSink = BundleBridgeSink[FakePLLCtrlBundle]() + pllCtrlSink := pllCtrl.ctrlNode + + InModuleBody { + val clock_wire = Wire(Input(new ClockWithFreq(100))) + val reset_wire = Wire(Input(AsyncReset())) + val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey)) + val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey)) + + slowClockSource.out.unzip._1.map { o => + o.clock := clock_wire.clock + o.reset := reset_wire + } + + // For a real chip you should replace this ClockSourceAtFreqFromPlusArg + // with a blackbox of whatever PLL is being integrated + val fake_pll = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz")) + fake_pll.io.power := pllCtrlSink.in(0)._1.power + fake_pll.io.gate := pllCtrlSink.in(0)._1.gate + + pllClockSource.out.unzip._1.map { o => + o.clock := fake_pll.io.clk + o.reset := reset_wire + } + + (Seq(clock_io, reset_io), clockIOCell ++ resetIOCell) + } + } +}) + +// This passes all clocks through to the TestHarness +class WithPassthroughClockGenerator extends OverrideLazyIOBinder({ + (system: HasChipyardPRCI) => { + // Connect the implicit clock + implicit val p = GetSystemParameters(system) + val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) + system.connectImplicitClockSinkNode(implicitClockSinkNode) + InModuleBody { + val implicit_clock = implicitClockSinkNode.in.head._1.clock + val implicit_reset = implicitClockSinkNode.in.head._1.reset + system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => { + l.clock := implicit_clock + l.reset := implicit_reset + }} + } + + // This aggregate node should do nothing + val clockGroupAggNode = ClockGroupAggregateNode("fake") + val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) + system.allClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode + + InModuleBody { + val reset_io = IO(Input(AsyncReset())) + require(clockGroupAggNode.out.size == 1) + val (bundle, edge) = clockGroupAggNode.out(0) + + val clock_ios = (bundle.member.data zip edge.sink.members).map { case (b, m) => + val freq = m.take.get.freqMHz + val clock_io = IO(Input(new ClockWithFreq(freq))).suggestName(s"clock_${m.name.get}") + b.clock := clock_io.clock + b.reset := reset_io + clock_io + }.toSeq + ((clock_ios :+ reset_io), Nil) + } + } +}) diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala index 07ae536b..c8bad8c4 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.{Analog, IO} -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala index 965beed3..39cb379b 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala @@ -2,7 +2,7 @@ package chipyard.clocking import chisel3._ -import freechips.rocketchip.config.{Parameters, Config, Field} +import org.chipsalliance.cde.config.{Parameters, Config, Field} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ diff --git a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala index d72b2a70..0458c621 100644 --- a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala +++ b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala @@ -2,7 +2,7 @@ package chipyard.clocking import chisel3._ -import freechips.rocketchip.config.{Parameters} +import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.util.ElaborationArtefacts @@ -92,57 +92,3 @@ class SimplePllConfiguration( def referenceSinkParams(): ClockSinkParameters = sinkDividerMap.find(_._2 == 1).get._1 } -case class DividerOnlyClockGeneratorNode(pllName: String)(implicit valName: ValName) - extends MixedNexusNode(ClockImp, ClockGroupImp)( - dFn = { _ => ClockGroupSourceParameters() }, - uFn = { u => - require(u.size == 1) - require(!u.head.members.contains(None), - "All output clocks in group must set their take parameters. Use a ClockGroupDealiaser") - ClockSinkParameters( - name = Some(s"${pllName}_reference_input"), - take = Some(ClockParameters(new SimplePllConfiguration(pllName, u.head.members).referenceFreqMHz))) } - ) - -/** - * Generates a digital-divider-only PLL model that verilator can simulate. - * Inspects all take-specified frequencies in the output ClockGroup, calculates a - * fast reference clock (roughly LCM(requested frequencies)) which is passed up the - * diplomatic graph, and then generates dividers for each unique requested - * frequency. - * - * Output resets are not synchronized to generated clocks and should be - * synchronized by the user in a manner they see fit. - * - */ - -class DividerOnlyClockGenerator(pllName: String)(implicit p: Parameters, valName: ValName) extends LazyModule { - val node = DividerOnlyClockGeneratorNode(pllName) - - lazy val module = new Impl - class Impl extends LazyRawModuleImp(this) { - require(node.out.size == 1, "Idealized PLL expects to generate a single output clock group. Use a ClockGroupAggregator") - val (refClock, ClockEdgeParameters(_, refSinkParam, _, _)) = node.in.head - val (outClocks, ClockGroupEdgeParameters(_, outSinkParams, _, _)) = node.out.head - - val referenceFreq = refSinkParam.take.get.freqMHz - val pllConfig = new SimplePllConfiguration(pllName, outSinkParams.members) - pllConfig.emitSummaries() - - val dividedClocks = mutable.HashMap[Int, Clock]() - def instantiateDivider(div: Int): Clock = { - val divider = Module(new ClockDividerN(div)) - divider.suggestName(s"ClockDivideBy${div}") - divider.io.clk_in := refClock.clock - dividedClocks(div) = divider.io.clk_out - divider.io.clk_out - } - - for (((sinkBName, sinkB), sinkP) <- outClocks.member.elements.zip(outSinkParams.members)) { - val div = pllConfig.sinkDividerMap(sinkP) - sinkB.clock := dividedClocks.getOrElse(div, instantiateDivider(div)) - // Reset handling and synchronization is expected to be handled by a downstream node - sinkB.reset := refClock.reset - } - } -} diff --git a/generators/chipyard/src/main/scala/clocking/FakePLL.scala b/generators/chipyard/src/main/scala/clocking/FakePLL.scala new file mode 100644 index 00000000..ac8f8b44 --- /dev/null +++ b/generators/chipyard/src/main/scala/clocking/FakePLL.scala @@ -0,0 +1,36 @@ +package chipyard.clocking + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.util._ + +class FakePLLCtrlBundle extends Bundle { + val gate = Bool() + val power = Bool() +} + +class FakePLLCtrl(address: BigInt, beatBytes: Int)(implicit p: Parameters) extends LazyModule +{ + val device = new SimpleDevice(s"pll", Nil) + val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes) + val ctrlNode = BundleBridgeSource(() => Output(new FakePLLCtrlBundle)) + lazy val module = new LazyModuleImp(this) { + // This PLL only has 2 address, the gate and power + // Both should be set to turn on the PLL + // TODO: Should these be reset by the top level reset pin? + val gate_reg = Module(new AsyncResetRegVec(w=1, init=0)) + val power_reg = Module(new AsyncResetRegVec(w=1, init=0)) + + ctrlNode.out(0)._1.gate := gate_reg.io.q + ctrlNode.out(0)._1.power := power_reg.io.q + tlNode.regmap( + 0 -> Seq(RegField.rwReg(1, gate_reg.io)), + 4 -> Seq(RegField.rwReg(1, power_reg.io)) + ) + } +} diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index 0cfc702a..1522648a 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -4,7 +4,7 @@ import chisel3._ import scala.collection.mutable.{ArrayBuffer} -import freechips.rocketchip.config.{Parameters, Field, Config} +import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ @@ -15,12 +15,13 @@ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ import testchipip.{TLTileResetCtrl} -import chipyard.{DefaultClockFrequencyKey} +import chipyard.harness.{DefaultClockFrequencyKey} case class ChipyardPRCIControlParams( slaveWhere: TLBusWrapperLocation = CBUS, baseAddress: BigInt = 0x100000, - enableTileClockGating: Boolean = true + enableTileClockGating: Boolean = true, + enableTileResetSetting: Boolean = true ) @@ -72,12 +73,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles => val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey)) val clockGroupCombiner = ClockGroupCombiner() val resetSynchronizer = ClockGroupResetSynchronizer() - val tileClockGater = prci_ctrl_domain { - TileClockGater(prciParams.baseAddress + 0x00000, tlbus, prciParams.enableTileClockGating) - } - val tileResetSetter = prci_ctrl_domain { + val tileClockGater = if (prciParams.enableTileClockGating) { prci_ctrl_domain { + TileClockGater(prciParams.baseAddress + 0x00000, tlbus) + } } else { ClockGroupEphemeralNode() } + val tileResetSetter = if (prciParams.enableTileResetSetting) { prci_ctrl_domain { TileResetSetter(prciParams.baseAddress + 0x10000, tlbus, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil) - } + } } else { ClockGroupEphemeralNode() } + (aggregator := frequencySpecifier := clockGroupCombiner diff --git a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala new file mode 100644 index 00000000..bc722799 --- /dev/null +++ b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala @@ -0,0 +1,56 @@ +package chipyard.clocking + +import chisel3._ + +import org.chipsalliance.cde.config.Parameters +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.util._ +import freechips.rocketchip.prci._ +import freechips.rocketchip.util.ElaborationArtefacts + +import testchipip._ + +// This module adds a TileLink memory-mapped clock divider to the clock graph +// The output clock/reset pairs from this module should be synchronized later +class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit p: Parameters) extends LazyModule { + val device = new SimpleDevice(s"clk-div-ctrl", Nil) + val clockNode = ClockGroupIdentityNode() + val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes) + + lazy val module = new LazyModuleImp(this) { + require (clockNode.out.size == 1) + val sources = clockNode.in.head._1.member.data.toSeq + val sinks = clockNode.out.head._1.member.elements.toSeq + require (sources.size == sinks.size) + val nSinks = sinks.size + + val regs = (0 until nSinks) .map { i => + val sinkName = sinks(i)._1 + val asyncReset = sources(i).reset + val reg = withReset (asyncReset) { + Module(new AsyncResetRegVec(w=divBits, init=0)) + } + println(s"${(address+i*4).toString(16)}: Clock domain $sinkName divider") + sinks(i)._2.clock := withClockAndReset(sources(i).clock, asyncReset) { + val divider = Module(new testchipip.ClockDivideOrPass(divBits, depth = 3, genClockGate = p(ClockGateImpl))) + divider.io.divisor := reg.io.q + divider.io.resetAsync := ResetStretcher(sources(i).clock, asyncReset, 20).asAsyncReset + divider.io.clockOut + } + + // Note this is not synchronized to the output clock, which takes time to appear + // so this is still asyncreset + // Stretch the reset for 40 cycles, to give enough time to reset any downstream + // digital logic + sinks(i)._2.reset := ResetStretcher(sources(i).clock, asyncReset, 40).asAsyncReset + reg + } + + tlNode.regmap((0 until nSinks).map { i => + i * 4 -> Seq(RegField.rwReg(divBits, regs(i).io)) + }: _*) + } +} diff --git a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala new file mode 100644 index 00000000..06821ead --- /dev/null +++ b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala @@ -0,0 +1,73 @@ +package chipyard.clocking + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.util._ +import freechips.rocketchip.prci._ +import freechips.rocketchip.util.ElaborationArtefacts + +import testchipip._ + +object ResetStretcher { + def apply(clock: Clock, reset: Reset, cycles: Int): Reset = { + withClockAndReset(clock, reset) { + val n = log2Ceil(cycles) + val count = Module(new AsyncResetRegVec(w=n, init=0)) + val resetout = Module(new AsyncResetRegVec(w=1, init=1)) + count.io.en := resetout.io.q + count.io.d := count.io.q + 1.U + resetout.io.en := resetout.io.q + resetout.io.d := count.io.q < (cycles-1).U + + resetout.io.q.asBool + } + } +} + + +case class ClockSelNode()(implicit valName: ValName) + extends MixedNexusNode(ClockImp, ClockGroupImp)( + dFn = { d => ClockGroupSourceParameters() }, + uFn = { u => ClockSinkParameters() } +) + +// This module adds a TileLink memory-mapped clock mux for each downstream clock domain +// in the clock graph. The output clock/reset should be synchronized downstream +class TLClockSelector(address: BigInt, beatBytes: Int)(implicit p: Parameters) extends LazyModule { + val device = new SimpleDevice("clk-sel-ctrl", Nil) + val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes) + + val clockNode = ClockSelNode() + + lazy val module = new LazyModuleImp(this) { + val asyncReset = clockNode.in.map(_._1).map(_.reset).toSeq(0) + val clocks = clockNode.in.map(_._1).map(_.clock) + val (outClocks, _) = clockNode.out.head + val (sinkNames, sinks) = outClocks.member.elements.toSeq.unzip + + val regs = (0 until sinks.size).map { i => + val sinkName = sinkNames(i) + val sel = Wire(UInt(log2Ceil(clocks.size).W)) + val reg = withReset(asyncReset) { Module(new AsyncResetRegVec(w=log2Ceil(clocks.size), init=0)) } + sel := reg.io.q + println(s"${(address+i*4).toString(16)}: Clock domain $sinkName clock mux") + + val mux = testchipip.ClockMutexMux(clocks).suggestName(s"${sinkName}_clkmux") + mux.io.sel := sel + mux.io.resetAsync := asyncReset.asAsyncReset + sinks(i).clock := mux.io.clockOut + // Stretch the reset for 20 cycles, to give time to reset any downstream digital logic + sinks(i).reset := ResetStretcher(clocks(0), asyncReset, 20).asAsyncReset + + reg + } + tlNode.regmap((0 until sinks.size).map { i => + i * 4 -> Seq(RegField.rwReg(log2Ceil(clocks.size), regs(i).io)) + }: _*) + } +} diff --git a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala index 5ca8d271..23d525a6 100644 --- a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala +++ b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.{Analog, IO} -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ @@ -19,7 +19,7 @@ import freechips.rocketchip.subsystem._ * flag will generate the registers, preserving the same memory map and behavior, but will not * generate any gaters */ -class TileClockGater(address: BigInt, beatBytes: Int, enable: Boolean)(implicit p: Parameters, valName: ValName) extends LazyModule +class TileClockGater(address: BigInt, beatBytes: Int)(implicit p: Parameters, valName: ValName) extends LazyModule { val device = new SimpleDevice(s"clock-gater", Nil) val clockNode = ClockGroupIdentityNode() @@ -31,8 +31,8 @@ class TileClockGater(address: BigInt, beatBytes: Int, enable: Boolean)(implicit val regs = (0 until nSinks).map({i => val sinkName = sinks(i)._1 val reg = withReset(sources(i).reset) { Module(new AsyncResetRegVec(w=1, init=1)) } - if (sinkName.contains("tile") && enable) { - println(s"ClockGate for ${sinkName} regmapped at ${(address+i*4).toString(16)}") + if (sinkName.contains("tile")) { + println(s"${(address+i*4).toString(16)}: Tile $sinkName clock gate") sinks(i)._2.clock := ClockGate(sources(i).clock, reg.io.q.asBool) sinks(i)._2.reset := sources(i).reset } else { @@ -47,8 +47,8 @@ class TileClockGater(address: BigInt, beatBytes: Int, enable: Boolean)(implicit } object TileClockGater { - def apply(address: BigInt, tlbus: TLBusWrapper, enable: Boolean)(implicit p: Parameters, v: ValName) = { - val gater = LazyModule(new TileClockGater(address, tlbus.beatBytes, enable)) + def apply(address: BigInt, tlbus: TLBusWrapper)(implicit p: Parameters, v: ValName) = { + val gater = LazyModule(new TileClockGater(address, tlbus.beatBytes)) tlbus.toVariableWidthSlave(Some("clock-gater")) { gater.tlNode := TLBuffer() } gater.clockNode } diff --git a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala index b67371d5..9ea4bfd5 100644 --- a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala +++ b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.{Analog, IO} -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ @@ -39,16 +39,16 @@ class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], i }): _*) val tileMap = tileNames.zipWithIndex.map({ case (n, i) => - n -> (tile_async_resets(i), r_tile_resets(i).io.q) + n -> (tile_async_resets(i), r_tile_resets(i).io.q, address + i * 4) }) (clockNode.out zip clockNode.in).map { case ((o, _), (i, _)) => (o.member.elements zip i.member.elements).foreach { case ((name, oD), (_, iD)) => oD.clock := iD.clock oD.reset := iD.reset - for ((n, (rIn, rOut)) <- tileMap) { + for ((n, (rIn, rOut, addr)) <- tileMap) { if (name.contains(n)) { - println(name, n) + println(s"${addr.toString(16)}: Tile $name reset control") // Async because the reset coming out of the AsyncResetRegVec is // clocked to the bus this is attached to, not the clock in this // clock bundle. We expect a ClockGroupResetSynchronizer downstream diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index b084845e..4b179fd0 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -1,6 +1,6 @@ package chipyard.config -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} // -------------- // Chipyard abstract ("base") configuration @@ -12,17 +12,18 @@ import freechips.rocketchip.config.{Config} class AbstractConfig extends Config( // The HarnessBinders control generation of hardware in the TestHarness - new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present - new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled - new chipyard.harness.WithSimSerial ++ // add external serial-adapter and RAM - new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled - new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present - new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled - new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled - new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present - new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present - new chipyard.harness.WithCustomBootPinPlusArg ++ - new chipyard.harness.WithClockAndResetFromHarness ++ + new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present + new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled + new chipyard.harness.WithSimTSIOverSerialTL ++ // add external serial-adapter and RAM + new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled + new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present + new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled + new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled + new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present + new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present + new chipyard.harness.WithCustomBootPinPlusArg ++ // drive custom-boot pin with a plusarg, if custom-boot-pin is present + new chipyard.harness.WithClockAndResetFromHarness ++ // all Clock/Reset I/O in ChipTop should be driven by harnessClockInstantiator + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz // The IOBinders instantiate ChipTop IOs to match desired digital IOs // IOCells are generated for "Chip-like" IOs, while simulation-only IOs are directly punched through @@ -40,18 +41,24 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithTraceIOPunchthrough ++ new chipyard.iobinders.WithExtInterruptIOCells ++ new chipyard.iobinders.WithCustomBootPin ++ - new chipyard.iobinders.WithDividerOnlyClockGenerator ++ + // By default, punch out IOs to the Harness + new chipyard.clocking.WithPassthroughClockGenerator ++ + + new testchipip.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address + new testchipip.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM + new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set) - new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus - new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus + new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus + new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus + new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++ // Default 2 memory channels new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) @@ -60,4 +67,5 @@ class AbstractConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ // leave the bus clocks undriven by sbus new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 + new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ // custom device name for DTS new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 0de224c9..092da3c3 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} // --------------------- // BOOM Configs @@ -53,3 +53,18 @@ class MediumBoomCosimConfig extends Config( new chipyard.config.WithTraceIO ++ // enable the traceio new boom.common.WithNMediumBooms(1) ++ new chipyard.config.AbstractConfig) + +class dmiMediumBoomConfig extends Config( + new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tl + new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port + new boom.common.WithNMediumBooms(1) ++ + new chipyard.config.AbstractConfig) + +class dmiMediumBoomCosimConfig extends Config( + new chipyard.harness.WithCospike ++ // attach spike-cosim + new chipyard.config.WithTraceIO ++ // enable the traceio + new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anythint to serial-tl + new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port + new boom.common.WithNMediumBooms(1) ++ + new chipyard.config.AbstractConfig) + diff --git a/generators/chipyard/src/main/scala/config/CVA6Configs.scala b/generators/chipyard/src/main/scala/config/CVA6Configs.scala index 132a3009..7b4406c4 100644 --- a/generators/chipyard/src/main/scala/config/CVA6Configs.scala +++ b/generators/chipyard/src/main/scala/config/CVA6Configs.scala @@ -2,7 +2,7 @@ package chipyard import chisel3._ -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} // --------------------- // CVA6 Configs @@ -13,7 +13,7 @@ class CVA6Config extends Config( new chipyard.config.AbstractConfig) class dmiCVA6Config extends Config( - new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial + new chipyard.harness.WithSerialTLTiedOff ++ // Tie off the serial-tilelink port new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new cva6.WithNCVA6Cores(1) ++ // single CVA6 core new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala new file mode 100644 index 00000000..e51ac525 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -0,0 +1,38 @@ +package chipyard + +import org.chipsalliance.cde.config.{Config} +import freechips.rocketchip.diplomacy._ + +// A simple config demonstrating how to set up a basic chip in Chipyard +class ChipLikeQuadRocketConfig extends Config( + //================================== + // Set up TestHarness + //================================== + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute frequencies for simulations in the harness + // NOTE: This only simulates properly in VCS + + //================================== + // Set up tiles + //================================== + new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add rational crossings between RocketTile and uncore + new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles) + + //================================== + // Set up I/O + //================================== + new testchipip.WithSerialTLWidth(4) ++ + new chipyard.harness.WithSimAXIMemOverSerialTL ++ // Attach fast SimDRAM to TestHarness + new chipyard.config.WithSerialTLBackingMemory ++ // Backing memory is over serial TL protocol + new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel + + //================================== + // Set up clock./reset + //================================== + new chipyard.clocking.WithPLLSelectorDividerClockGenerator ++ // Use a PLL-based clock selector/divider generator structure + + // Create the uncore clock group + new chipyard.clocking.WithClockGroupsCombinedByName("uncore", "implicit", "sbus", "mbus", "cbus", "system_bus", "fbus", "pbus") ++ + + new chipyard.config.AbstractConfig) + diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala index 8e8c7fe9..206b086b 100644 --- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} // --------------------- // Heterogenous Configs diff --git a/generators/chipyard/src/main/scala/config/IbexConfigs.scala b/generators/chipyard/src/main/scala/config/IbexConfigs.scala index 63b7aa5d..6d1b6e4e 100644 --- a/generators/chipyard/src/main/scala/config/IbexConfigs.scala +++ b/generators/chipyard/src/main/scala/config/IbexConfigs.scala @@ -2,7 +2,7 @@ package chipyard import chisel3._ -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} // --------------------- // Ibex Configs diff --git a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala index fcb4804d..6a7710d9 100644 --- a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // ------------------------------ @@ -9,6 +9,7 @@ import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // DOC include start: FFTRocketConfig class FFTRocketConfig extends Config( + new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO: hack around dontTouch not working in SFC new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers. new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) @@ -58,6 +59,7 @@ class LargeNVDLARocketConfig extends Config( new chipyard.config.AbstractConfig) class ManyMMIOAcceleratorRocketConfig extends Config( + new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO: hack around dontTouch not working in SFC new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers. new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala index bd36fe04..0036e988 100644 --- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy.{AsynchronousCrossing} import freechips.rocketchip.subsystem.{SBUS, MBUS} diff --git a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala index 9d0c4132..10be8aca 100644 --- a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} // A empty config with no cores. Useful for testing class NoCoresConfig extends Config( diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala index d01bcd8d..029dd2bd 100644 --- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // --------------------------------------------------------- @@ -58,7 +58,7 @@ class LBWIFRocketConfig extends Config( // DOC include start: DmiRocket class dmiRocketConfig extends Config( - new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial + new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tl new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala index 7487a50e..4077fcbd 100644 --- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // ------------------------------ diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index b6677cb1..ea00f8b2 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // -------------- @@ -12,6 +12,7 @@ class RocketConfig extends Config( new chipyard.config.AbstractConfig) class TinyRocketConfig extends Config( + new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO FIX: Don't dontTouch the ports new chipyard.config.WithTLSerialLocation( freechips.rocketchip.subsystem.FBUS, freechips.rocketchip.subsystem.PBUS) ++ // attach TL serial adapter to f/p busses @@ -85,6 +86,7 @@ class MbusScratchpadRocketConfig extends Config( // DOC include end: mbusscratchpadrocket class MulticlockRocketConfig extends Config( + new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add async crossings between RocketTile and uncore new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Frequency specifications new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540 @@ -95,7 +97,6 @@ class MulticlockRocketConfig extends Config( // Crossing specifications new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS - new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS new chipyard.config.AbstractConfig) @@ -124,5 +125,12 @@ class MulticlockAXIOverSerialConfig extends Config( new chipyard.config.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory new freechips.rocketchip.subsystem.WithNBigCores(2) ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel new chipyard.config.AbstractConfig) // DOC include end: MulticlockAXIOverSerialConfig + +class CustomIOChipTopRocketConfig extends Config( + new chipyard.example.WithCustomChipTop ++ + new chipyard.example.WithCustomIOCells ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala b/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala index 3eb568ba..43ad1de3 100644 --- a/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala +++ b/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // -------------- diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index 3679ed07..24eb1f4d 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -2,7 +2,7 @@ package chipyard import chisel3._ -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} class Sodor1StageConfig extends Config( // Create a Sodor 1-stage core diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala index b45245c0..8caed688 100644 --- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} // Configs which instantiate a Spike-simulated // tile that interacts with the Chipyard SoC @@ -10,10 +10,47 @@ class SpikeConfig extends Config( new chipyard.WithNSpikeCores(1) ++ new chipyard.config.AbstractConfig) +class dmiSpikeConfig extends Config( + new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tilelink + new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port + new SpikeConfig) + // Avoids polling on the UART registers class SpikeFastUARTConfig extends Config( new chipyard.WithNSpikeCores(1) ++ new chipyard.config.WithUARTFIFOEntries(128, 128) ++ - new chipyard.config.WithMemoryBusFrequency(1) ++ - new chipyard.config.WithPeripheryBusFrequency(1) ++ + new chipyard.config.WithMemoryBusFrequency(2) ++ + new chipyard.config.WithPeripheryBusFrequency(2) ++ + new chipyard.config.AbstractConfig) + +// Makes the UART fast, also builds no L2 and a ludicrous L1D +class SpikeUltraFastConfig extends Config( + new chipyard.WithSpikeTCM ++ + new chipyard.WithNSpikeCores(1) ++ + new testchipip.WithSerialPBusMem ++ + new chipyard.config.WithUARTFIFOEntries(128, 128) ++ + new chipyard.config.WithMemoryBusFrequency(2) ++ + new chipyard.config.WithPeripheryBusFrequency(2) ++ + new chipyard.config.WithBroadcastManager ++ + new chipyard.config.AbstractConfig) + +class dmiSpikeUltraFastConfig extends Config( + new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tilelink + new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port + new SpikeUltraFastConfig) + +// Add the default firechip devices +class SpikeUltraFastDevicesConfig extends Config( + new chipyard.harness.WithSimBlockDevice ++ + new chipyard.harness.WithLoopbackNIC ++ + new icenet.WithIceNIC ++ + new testchipip.WithBlockDevice ++ + + new chipyard.WithSpikeTCM ++ + new chipyard.WithNSpikeCores(1) ++ + new testchipip.WithSerialPBusMem ++ + new chipyard.config.WithUARTFIFOEntries(128, 128) ++ + new chipyard.config.WithMemoryBusFrequency(2) ++ + new chipyard.config.WithPeripheryBusFrequency(2) ++ + new chipyard.config.WithBroadcastManager ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index 4ab51994..3c2b9a0c 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -1,15 +1,16 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.rocket.{DCacheParams} class AbstractTraceGenConfig extends Config( + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ new chipyard.harness.WithBlackBoxSimMem ++ new chipyard.harness.WithTraceGenSuccess ++ new chipyard.harness.WithClockAndResetFromHarness ++ new chipyard.iobinders.WithAXI4MemPunchthrough ++ new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ - new chipyard.iobinders.WithDividerOnlyClockGenerator ++ + new chipyard.clocking.WithPassthroughClockGenerator ++ new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index c9956b7a..daa08265 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -1,6 +1,6 @@ package chipyard -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import constellation.channel._ import constellation.routing._ import constellation.topology._ @@ -77,6 +77,7 @@ class TutorialSha3BlackBoxConfig extends Config( // Tutorial Phase 5: Map a multicore heterogeneous SoC with multiple cores and memory-mapped accelerators class TutorialNoCConfig extends Config( + new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // Try changing the dimensions of the Mesh topology new constellation.soc.WithGlobalNoC(constellation.soc.GlobalNoCParams( NoCParams( diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala index 0c79f6dc..6080c36f 100644 --- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala @@ -4,7 +4,7 @@ import scala.util.matching.Regex import chisel3._ import chisel3.util.{log2Up} -import freechips.rocketchip.config.{Field, Parameters, Config} +import org.chipsalliance.cde.config.{Field, Parameters, Config} import freechips.rocketchip.subsystem._ import freechips.rocketchip.prci._ import freechips.rocketchip.diplomacy._ @@ -13,7 +13,7 @@ import freechips.rocketchip.tilelink.{HasTLBusParams} import chipyard._ import chipyard.clocking._ - +import chipyard.harness.{DefaultClockFrequencyKey} // The default RocketChip BaseSubsystem drives its diplomatic clock graph // with the implicit clocks of Subsystem. Don't do that, instead we extend diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index ec9ff47c..56cd3bb6 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -4,7 +4,7 @@ import scala.util.matching.Regex import chisel3._ import chisel3.util.{log2Up} -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey} import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI} import freechips.rocketchip.stage.phases.TargetDirKey @@ -87,3 +87,7 @@ class WithExtMemIdBits(n: Int) extends Config((site, here, up) => { class WithNoPLIC extends Config((site, here, up) => { case PLICKey => None }) + +class WithDebugModuleAbstractDataWords(words: Int = 16) extends Config((site, here, up) => { + case DebugModuleKey => up(DebugModuleKey).map(_.copy(nAbstractDataWords=words)) +}) diff --git a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala index 774b23c2..4680eeeb 100644 --- a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala @@ -2,7 +2,7 @@ package chipyard.config import chisel3._ -import freechips.rocketchip.config.{Field, Parameters, Config} +import org.chipsalliance.cde.config.{Field, Parameters, Config} import freechips.rocketchip.tile._ import freechips.rocketchip.diplomacy._ diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala index c41e2716..40f18d5d 100644 --- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala @@ -1,6 +1,6 @@ package chipyard.config -import freechips.rocketchip.config.{Config} +import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper} import freechips.rocketchip.diplomacy.{DTSTimebase} diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala index f19759cb..56042c3d 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala @@ -2,7 +2,7 @@ package chipyard.config import chisel3._ -import freechips.rocketchip.config.{Field, Parameters, Config} +import org.chipsalliance.cde.config.{Field, Parameters, Config} import freechips.rocketchip.tile._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams} diff --git a/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala index 2e849c58..c8b4f828 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala @@ -1,6 +1,6 @@ package chipyard.config -import freechips.rocketchip.config.{Config, Field, Parameters} +import org.chipsalliance.cde.config.{Config, Field, Parameters} import tracegen.{TraceGenSystem} import chipyard.{BuildSystem} import chipyard.clocking.{HasChipyardPRCI} diff --git a/generators/chipyard/src/main/scala/example/CustomChipTop.scala b/generators/chipyard/src/main/scala/example/CustomChipTop.scala new file mode 100644 index 00000000..f2ebfc33 --- /dev/null +++ b/generators/chipyard/src/main/scala/example/CustomChipTop.scala @@ -0,0 +1,65 @@ +package chipyard.example + +import chisel3._ +import chipyard.iobinders._ + +import org.chipsalliance.cde.config._ +import freechips.rocketchip.diplomacy.{InModuleBody} +import barstools.iocell.chisel._ +import chipyard._ +import chipyard.harness.{BuildTop} + +// A "custom" IOCell with additional I/O +// The IO don't do anything here in this example +class CustomDigitalInIOCellBundle extends DigitalInIOCellBundle { + val custom_out = Output(Bool()) + val custom_in = Input(Bool()) +} + +// Using a custom digital in iocell instead of the default one +class CustomDigitalInIOCell extends RawModule with DigitalInIOCell { + val io = IO(new CustomDigitalInIOCellBundle) + io.i := io.pad + io.custom_out := io.pad +} + +case class CustomIOCellParams() extends IOCellTypeParams { + def analog() = Module(new GenericAnalogIOCell) + def gpio() = Module(new GenericDigitalGPIOCell) + def input() = Module(new CustomDigitalInIOCell) + def output() = Module(new GenericDigitalOutIOCell) +} + +class CustomChipTop(implicit p: Parameters) extends ChipTop { + // making the module name ChipTop instead of CustomChipTop means + // we don't have to set the TOP make variable to CustomChipTop + override lazy val desiredName = "ChipTop" + + // InModuleBody blocks are executed within the LazyModuleImp of this block + InModuleBody { + iocellMap.foreach { case (interface, cells) => { + cells.foreach { _ match { + case c: CustomDigitalInIOCell => { + c.io.custom_in := false.B + } + case c: GenericDigitalOutIOCell => { + // do nothing + } + case c => { + require(false, "Unsupported iocell type ${c.getClass}") + } + }} + }} + + // demonstrate accessing the iocellMap directly + val serialTLIOCells = iocellMap("interface testchipip.CanHavePeripheryTLSerial") + } +} + +class WithCustomIOCells extends Config((site, here, up) => { + case IOCellKey => CustomIOCellParams() +}) + +class WithCustomChipTop extends Config((site, here, up) => { + case BuildTop => (p: Parameters) => new CustomChipTop()(p) +}) diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala new file mode 100644 index 00000000..c10baab4 --- /dev/null +++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala @@ -0,0 +1,145 @@ +package chipyard.example + + +import chisel3._ +import org.chipsalliance.cde.config.{Field, Parameters} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.prci._ +import freechips.rocketchip.util._ +import freechips.rocketchip.devices.debug.{ExportDebug, JtagDTMKey, Debug} +import freechips.rocketchip.tilelink.{TLBuffer} +import chipyard.{BuildSystem, DigitalTop} +import chipyard.clocking._ +import chipyard.iobinders.{IOCellKey, JTAGChipIO} +import barstools.iocell.chisel._ + + +// This "FlatChipTop" uses no IOBinders, so all the IO have +// to be explicitly constructed. +// This only supports the base "DigitalTop" +class FlatChipTop(implicit p: Parameters) extends LazyModule { + override lazy val desiredName = "ChipTop" + val system = LazyModule(p(BuildSystem)(p)).suggestName("system").asInstanceOf[DigitalTop] + + //======================== + // Diplomatic clock stuff + //======================== + val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) + system.connectImplicitClockSinkNode(implicitClockSinkNode) + + val tlbus = system.locateTLBusWrapper(system.prciParams.slaveWhere) + val baseAddress = system.prciParams.baseAddress + val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes)) } + val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) } + val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) } + + tlbus.toVariableWidthSlave(Some("clock-div-ctrl")) { clockDivider.tlNode := TLBuffer() } + tlbus.toVariableWidthSlave(Some("clock-sel-ctrl")) { clockSelector.tlNode := TLBuffer() } + tlbus.toVariableWidthSlave(Some("pll-ctrl")) { pllCtrl.tlNode := TLBuffer() } + + system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode + + // Connect all other requested clocks + val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters())) + val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters())) + + // The order of the connections to clockSelector.clockNode configures the inputs + // of the clockSelector's clockMux. Default to using the slowClockSource, + // software should enable the PLL, then switch to the pllClockSource + clockSelector.clockNode := slowClockSource + clockSelector.clockNode := pllClockSource + + val pllCtrlSink = BundleBridgeSink[FakePLLCtrlBundle]() + pllCtrlSink := pllCtrl.ctrlNode + + val debugClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters())) + debugClockSinkNode := system.locateTLBusWrapper(p(ExportDebug).slaveWhere).fixedClockNode + def debugClockBundle = debugClockSinkNode.in.head._1 + + override lazy val module = new FlatChipTopImpl + class FlatChipTopImpl extends LazyRawModuleImp(this) { + //========================= + // Clock/reset + //========================= + val implicit_clock = implicitClockSinkNode.in.head._1.clock + val implicit_reset = implicitClockSinkNode.in.head._1.reset + system.module match { case l: LazyModuleImp => { + l.clock := implicit_clock + l.reset := implicit_reset + }} + + val clock_wire = Wire(Input(new ClockWithFreq(80))) + val reset_wire = Wire(Input(AsyncReset())) + val (clock_pad, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey)) + val (reset_pad, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey)) + + slowClockSource.out.unzip._1.map { o => + o.clock := clock_wire.clock + o.reset := reset_wire + } + + // For a real chip you should replace this ClockSourceAtFreqFromPlusArg + // with a blackbox of whatever PLL is being integrated + val fake_pll = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz")) + fake_pll.io.power := pllCtrlSink.in(0)._1.power + fake_pll.io.gate := pllCtrlSink.in(0)._1.gate + + pllClockSource.out.unzip._1.map { o => + o.clock := fake_pll.io.clk + o.reset := reset_wire + } + + //========================= + // Custom Boot + //========================= + val (custom_boot_pad, customBootIOCell) = IOCell.generateIOFromSignal(system.custom_boot_pin.get.getWrappedValue, "custom_boot", p(IOCellKey)) + + //========================= + // Serialized TileLink + //========================= + val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tl.get.getWrappedValue, "serial_tl", p(IOCellKey)) + + //========================= + // JTAG/Debug + //========================= + val debug = system.debug.get + // We never use the PSDIO, so tie it off on-chip + system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) } + system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := false.B } } + + // Tie off extTrigger + debug.extTrigger.foreach { t => + t.in.req := false.B + t.out.ack := t.out.req + } + // Tie off disableDebug + debug.disableDebug.foreach { d => d := false.B } + // Drive JTAG on-chip IOs + debug.systemjtag.map { j => + j.reset := ResetCatchAndSync(j.jtag.TCK, debugClockBundle.reset.asBool) + j.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) + j.part_number := p(JtagDTMKey).idcodePartNum.U(16.W) + j.version := p(JtagDTMKey).idcodeVersion.U(4.W) + } + + Debug.connectDebugClockAndReset(Some(debug), debugClockBundle.clock) + + // Add IOCells for the DMI/JTAG/APB ports + require(!debug.clockeddmi.isDefined) + require(!debug.apb.isDefined) + val (jtag_pad, jtagIOCells) = debug.systemjtag.map { j => + val jtag_wire = Wire(new JTAGChipIO) + j.jtag.TCK := jtag_wire.TCK + j.jtag.TMS := jtag_wire.TMS + j.jtag.TDI := jtag_wire.TDI + jtag_wire.TDO := j.jtag.TDO.data + IOCell.generateIOFromSignal(jtag_wire, "jtag", p(IOCellKey), abstractResetAsAsync = true) + }.get + + //========================== + // UART + //========================== + require(system.uarts.size == 1) + val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.module.uart.head, "uart_0", p(IOCellKey)) + } +} diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala new file mode 100644 index 00000000..55b414cf --- /dev/null +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -0,0 +1,85 @@ +package chipyard.example + +import chisel3._ + +import scala.collection.mutable.{ArrayBuffer, LinkedHashMap} + +import org.chipsalliance.cde.config.{Field, Parameters} +import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.prci.{ClockSourceAtFreqFromPlusArg, ClockBundle, ClockBundleParameters} +import freechips.rocketchip.util.{PlusArg} +import freechips.rocketchip.subsystem.{CacheBlockBytes} +import freechips.rocketchip.devices.debug.{SimJTAG} +import freechips.rocketchip.jtag.{JTAGIO} +import testchipip.{SerialTLKey, UARTAdapter, SimDRAM, TSIHarness, SimTSI} +import chipyard.harness.{BuildTop} + +// A "flat" TestHarness that doesn't use IOBinders +// use with caution. +// This example is hard-coded to work only for FlatChipTop, and the ChipLikeRocketConfig +class FlatTestHarness(implicit val p: Parameters) extends Module { + val io = IO(new Bundle { + val success = Output(Bool()) + }) + + // This only works with FlatChipTop + val lazyDut = LazyModule(new FlatChipTop).suggestName("chiptop") + val dut = Module(lazyDut.module) + + // Clock + val clock_source = Module(new ClockSourceAtFreqFromPlusArg("slow_clk_freq_mhz")) + clock_source.io.power := true.B + clock_source.io.gate := false.B + dut.clock_pad.clock := clock_source.io.clk + + // Reset + dut.reset_pad := reset.asAsyncReset + + // Custom boot + dut.custom_boot_pad := PlusArg("custom_boot_pin", width=1) + + // Serialized TL + val sVal = p(SerialTLKey).get + require(sVal.axiMemOverSerialTLParams.isDefined) + require(sVal.isMemoryDevice) + val axiDomainParams = sVal.axiMemOverSerialTLParams.get + val memFreq = axiDomainParams.getMemFrequency(lazyDut.system) + + withClockAndReset(clock, reset) { + val memOverSerialTLClockBundle = Wire(new ClockBundle(ClockBundleParameters())) + memOverSerialTLClockBundle.clock := clock + memOverSerialTLClockBundle.reset := reset + val serial_bits = dut.serial_tl_pad.bits + dut.serial_tl_pad.clock := clock + val harnessMultiClockAXIRAM = TSIHarness.connectMultiClockAXIRAM( + lazyDut.system.serdesser.get, + serial_bits, + memOverSerialTLClockBundle, + reset) + io.success := SimTSI.connect(Some(harnessMultiClockAXIRAM.module.io.tsi), clock, reset) + + // connect SimDRAM from the AXI port coming from the harness multi clock axi ram + (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) => + val memSize = sVal.memParams.size + val memBase = sVal.memParams.base + val lineSize = p(CacheBlockBytes) + val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram") + mem.io.axi <> axi_port.bits + mem.io.clock := axi_port.clock + mem.io.reset := axi_port.reset + } + } + + // JTAG + val jtag_wire = Wire(new JTAGIO) + jtag_wire.TDO.data := dut.jtag_pad.TDO + jtag_wire.TDO.driven := true.B + dut.jtag_pad.TCK := jtag_wire.TCK + dut.jtag_pad.TMS := jtag_wire.TMS + dut.jtag_pad.TDI := jtag_wire.TDI + val dtm_success = WireInit(false.B) + val jtag = Module(new SimJTAG(tickDelay=3)).connect(jtag_wire, clock, reset.asBool, ~(reset.asBool), dtm_success) + + // UART + UARTAdapter.connect(Seq(dut.uart_pad)) +} diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala index fe55f288..bf05ba9c 100644 --- a/generators/chipyard/src/main/scala/example/GCD.scala +++ b/generators/chipyard/src/main/scala/example/GCD.scala @@ -5,7 +5,7 @@ import chisel3.util._ import chisel3.experimental.{IntParam, BaseModule} import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.subsystem.BaseSubsystem -import freechips.rocketchip.config.{Parameters, Field, Config} +import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper.{HasRegMap, RegField} import freechips.rocketchip.tilelink._ diff --git a/generators/chipyard/src/main/scala/example/InitZero.scala b/generators/chipyard/src/main/scala/example/InitZero.scala index 5051c37d..bb6ecd72 100644 --- a/generators/chipyard/src/main/scala/example/InitZero.scala +++ b/generators/chipyard/src/main/scala/example/InitZero.scala @@ -3,7 +3,7 @@ package chipyard.example import chisel3._ import chisel3.util._ import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes} -import freechips.rocketchip.config.{Parameters, Field, Config} +import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange} import freechips.rocketchip.tilelink._ diff --git a/generators/chipyard/src/main/scala/example/NodeTypes.scala b/generators/chipyard/src/main/scala/example/NodeTypes.scala index cafc470f..1cdddd32 100644 --- a/generators/chipyard/src/main/scala/example/NodeTypes.scala +++ b/generators/chipyard/src/main/scala/example/NodeTypes.scala @@ -1,6 +1,6 @@ package chipyard.example -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ diff --git a/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala b/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala index cda91ffe..e7a8b0b8 100644 --- a/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala +++ b/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala @@ -2,7 +2,7 @@ import chisel3._ import chisel3.util._ -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink.TLRegisterNode diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 3d8e1ae1..1a9114b9 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -3,7 +3,7 @@ package chipyard.example import chisel3._ import chisel3.util._ -import freechips.rocketchip.config._ +import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ diff --git a/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala b/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala index b51e2223..9ad23a4c 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala @@ -5,7 +5,7 @@ import chisel3.util._ import dspblocks._ import dsptools.numbers._ import freechips.rocketchip.amba.axi4stream._ -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index f45b318c..15dfb992 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -8,7 +8,7 @@ import chisel3.util._ import dspblocks._ import dsptools.numbers._ import freechips.rocketchip.amba.axi4stream._ -import freechips.rocketchip.config.{Parameters, Field, Config} +import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala index c6ffaf42..2846277c 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala @@ -8,7 +8,7 @@ import chisel3.util._ import dspblocks._ import dsptools.numbers._ import freechips.rocketchip.amba.axi4stream._ -import freechips.rocketchip.config.{Parameters, Field, Config} +import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala similarity index 86% rename from generators/chipyard/src/main/scala/HarnessBinders.scala rename to generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 21dfe588..d78318f8 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction} -import freechips.rocketchip.config.{Field, Config, Parameters} +import org.chipsalliance.cde.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters} import freechips.rocketchip.devices.debug._ @@ -22,8 +22,8 @@ import barstools.iocell.chisel._ import testchipip._ import chipyard._ -import chipyard.clocking.{HasChipyardPRCI} -import chipyard.iobinders.{GetSystemParameters, JTAGChipIO, ClockWithFreq} +import chipyard.clocking.{HasChipyardPRCI, ClockWithFreq} +import chipyard.iobinders.{GetSystemParameters, JTAGChipIO} import tracegen.{TraceGenSystemModuleImp} import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} @@ -154,22 +154,24 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({ ports.map({ port => // DOC include start: HarnessClockInstantiatorEx withClockAndReset(th.buildtopClock, th.buildtopReset) { - val memOverSerialTLClockBundle = p(HarnessClockInstantiatorKey).requestClockBundle("mem_over_serial_tl_clock", memFreq) - val serial_bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) - val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM( + val memOverSerialTLClockBundle = th.harnessClockInstantiator.requestClockBundle("mem_over_serial_tl_clock", memFreq) + val serial_bits = port.bits + port.clock := th.buildtopClock + val harnessMultiClockAXIRAM = TSIHarness.connectMultiClockAXIRAM( system.serdesser.get, serial_bits, memOverSerialTLClockBundle, th.buildtopReset) // DOC include end: HarnessClockInstantiatorEx - val success = SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, th.buildtopClock, th.buildtopReset.asBool) + val success = SimTSI.connect(Some(harnessMultiClockAXIRAM.module.io.tsi), th.buildtopClock, th.buildtopReset.asBool) when (success) { th.success := true.B } // connect SimDRAM from the AXI port coming from the harness multi clock axi ram (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) => val memSize = sVal.memParams.size + val memBase = sVal.memParams.base val lineSize = p(CacheBlockBytes) - val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), edge.bundle)).suggestName("simdram") + val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram") mem.io.axi <> axi_port.bits mem.io.clock := axi_port.clock mem.io.reset := axi_port.reset @@ -184,10 +186,12 @@ class WithBlackBoxSimMem(additionalLatency: Int = 0) extends OverrideHarnessBind (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => + // TODO FIX: This currently makes each SimDRAM contain the entire memory space val memSize = p(ExtMem).get.master.size + val memBase = p(ExtMem).get.master.base val lineSize = p(CacheBlockBytes) val clockFreq = p(MemoryBusKey).dtsFrequency.get - val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, edge.bundle)).suggestName("simdram") + val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, memBase, edge.bundle)).suggestName("simdram") mem.io.axi <> port.bits // Bug in Chisel implementation. See https://github.com/chipsalliance/chisel3/pull/1781 def Decoupled[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = { @@ -252,7 +256,7 @@ class WithSimDebug extends OverrideHarnessBinder({ case d: ClockedDMIIO => val dtm_success = WireInit(false.B) when (dtm_success) { th.success := true.B } - val dtm = Module(new SimDTM).connect(th.buildtopClock, th.buildtopReset.asBool, d, dtm_success) + val dtm = Module(new TestchipSimDTM).connect(th.buildtopClock, th.buildtopReset.asBool, d, dtm_success) case j: JTAGChipIO => val dtm_success = WireInit(false.B) when (dtm_success) { th.success := true.B } @@ -262,7 +266,8 @@ class WithSimDebug extends OverrideHarnessBinder({ j.TCK := jtag_wire.TCK j.TMS := jtag_wire.TMS j.TDI := jtag_wire.TDI - val jtag = Module(new SimJTAG(tickDelay=3)).connect(jtag_wire, th.buildtopClock, th.buildtopReset.asBool, ~(th.buildtopReset.asBool), dtm_success) + val jtag = Module(new SimJTAG(tickDelay=3)) + jtag.connect(jtag_wire, th.buildtopClock, th.buildtopReset.asBool, ~(th.buildtopReset.asBool), dtm_success) } } }) @@ -294,27 +299,28 @@ class WithTiedOffDebug extends OverrideHarnessBinder({ }) -class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ +class WithSerialTLTiedOff extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => - val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) - withClockAndReset(th.buildtopClock, th.buildtopReset) { - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) - SerialAdapter.tieoff(ram.module.io.tsi_ser) - } + val bits = port.bits + port.clock := false.B.asClock + port.bits.out.ready := false.B + port.bits.in.valid := false.B + port.bits.in.bits := DontCare }) } }) -class WithSimSerial extends OverrideHarnessBinder({ +class WithSimTSIOverSerialTL extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => - val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) + val bits = port.bits + port.clock := th.buildtopClock withClockAndReset(th.buildtopClock, th.buildtopReset) { - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) - val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, th.buildtopClock, th.buildtopReset.asBool) + val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.buildtopReset) + val success = SimTSI.connect(Some(ram.module.io.tsi), th.buildtopClock, th.buildtopReset.asBool) when (success) { th.success := true.B } } }) @@ -326,13 +332,14 @@ class WithUARTSerial extends OverrideHarnessBinder({ implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => val freq = p(PeripheryBusKey).dtsFrequency.get - val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) + val bits = port.bits + port.clock := th.buildtopClock withClockAndReset(th.buildtopClock, th.buildtopReset) { - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) + val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.buildtopReset) val uart_to_serial = Module(new UARTToSerial(freq, UARTParams(0))) val serial_width_adapter = Module(new SerialWidthAdapter( - 8, SerialAdapter.SERIAL_TSI_WIDTH)) - ram.module.io.tsi_ser.flipConnect(serial_width_adapter.io.wide) + 8, TSI.WIDTH)) + ram.module.io.tsi.flipConnect(serial_width_adapter.io.wide) UARTAdapter.connect(Seq(uart_to_serial.io.uart), uart_to_serial.div) serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial) th.success := false.B @@ -365,7 +372,8 @@ class WithCospike extends ComposeHarnessBinder({ mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)), pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0), nharts = tiles.size, - bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse("") + bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse(""), + has_dtm = p(ExportDebug).protocols.contains(DMI) // assume that exposing clockeddmi means we will connect SimDTM ) ports.map { p => p.traces.zipWithIndex.map(t => SpikeCosim(t._1, t._2, cfg)) } } @@ -385,8 +393,8 @@ class WithClockAndResetFromHarness extends OverrideHarnessBinder({ implicit val p = GetSystemParameters(system) ports.map ({ case c: ClockWithFreq => { - th.setRefClockFreq(c.freqMHz) - c.clock := th.buildtopClock + val clock = th.harnessClockInstantiator.requestClockBundle(s"clock_${c.freqMHz}MHz", c.freqMHz * (1000 * 1000)) + c.clock := clock.clock } case r: AsyncReset => r := th.buildtopReset.asAsyncReset }) diff --git a/generators/chipyard/src/main/scala/harness/HarnessClocks.scala b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala new file mode 100644 index 00000000..4fb7ea9e --- /dev/null +++ b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala @@ -0,0 +1,100 @@ +package chipyard.harness + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.DoubleParam +import scala.collection.mutable.{ArrayBuffer, LinkedHashMap} +import freechips.rocketchip.diplomacy.{LazyModule} +import org.chipsalliance.cde.config.{Field, Parameters, Config} +import freechips.rocketchip.util.{ResetCatchAndSync} +import freechips.rocketchip.prci._ + +import chipyard.harness.{ApplyHarnessBinders, HarnessBinders, HarnessClockInstantiatorKey} +import chipyard.iobinders.HasIOBinders +import chipyard.clocking.{SimplePllConfiguration, ClockDividerN} + + +// HarnessClockInstantiators are classes which generate clocks that drive +// TestHarness simulation models and any Clock inputs to the ChipTop +trait HarnessClockInstantiator { + val _clockMap: LinkedHashMap[String, (Double, ClockBundle)] = LinkedHashMap.empty + + // request a clock bundle at a particular frequency + def requestClockBundle(name: String, freqRequested: Double): ClockBundle = { + if (_clockMap.contains(name)) { + require(freqRequested == _clockMap(name)._1, + s"Request clock freq = $freqRequested != previously requested ${_clockMap(name)._2} for requested clock $name") + _clockMap(name)._2 + } else { + val clockBundle = Wire(new ClockBundle(ClockBundleParameters())) + _clockMap(name) = (freqRequested, clockBundle) + clockBundle + } + } + + // refClock is the clock generated by TestDriver that is + // passed to the TestHarness as its implicit clock + def instantiateHarnessClocks(refClock: ClockBundle): Unit +} + +class ClockSourceAtFreqMHz(val freqMHz: Double) extends BlackBox(Map( + "PERIOD" -> DoubleParam(1000/freqMHz) +)) with HasBlackBoxInline { + val io = IO(new ClockSourceIO) + val moduleName = this.getClass.getSimpleName + + setInline(s"$moduleName.v", + s""" + |module $moduleName #(parameter PERIOD="") ( + | input power, + | input gate, + | output clk); + | timeunit 1ns/1ps; + | reg clk_i = 1'b0; + | always #(PERIOD/2.0) clk_i = ~clk_i & (power & ~gate); + | assign clk = clk_i; + |endmodule + |""".stripMargin) +} + + +// The AbsoluteFreqHarnessClockInstantiator uses a Verilog blackbox to +// provide the precise requested frequency. +// This ClockInstantiator cannot be synthesized, run in Verilator, or run in FireSim +// It is useful for VCS/Xcelium-driven RTL simulations +class AbsoluteFreqHarnessClockInstantiator extends HarnessClockInstantiator { + def instantiateHarnessClocks(refClock: ClockBundle): Unit = { + val sinks = _clockMap.map({ case (name, (freq, bundle)) => + ClockSinkParameters(take=Some(ClockParameters(freqMHz=freq / (1000 * 1000))), name=Some(name)) + }).toSeq + + // connect wires to clock source + for (sinkParams <- sinks) { + val source = Module(new ClockSourceAtFreqMHz(sinkParams.take.get.freqMHz)) + source.io.power := true.B + source.io.gate := false.B + + _clockMap(sinkParams.name.get)._2.clock := source.io.clk + _clockMap(sinkParams.name.get)._2.reset := refClock.reset + } + } +} + +class WithAbsoluteFreqHarnessClockInstantiator extends Config((site, here, up) => { + case HarnessClockInstantiatorKey => () => new AbsoluteFreqHarnessClockInstantiator +}) + +class AllClocksFromHarnessClockInstantiator extends HarnessClockInstantiator { + def instantiateHarnessClocks(refClock: ClockBundle): Unit = { + val freqs = _clockMap.map(_._2._1) + freqs.tail.foreach(t => require(t == freqs.head, s"Mismatching clocks $t != ${freqs.head}")) + for ((_, (_, bundle)) <- _clockMap) { + bundle.clock := refClock.clock + bundle.reset := refClock.reset + } + } +} + +class WithAllClocksFromHarnessClockInstantiator extends Config((site, here, up) => { + case HarnessClockInstantiatorKey => () => new AllClocksFromHarnessClockInstantiator +}) diff --git a/generators/chipyard/src/main/scala/harness/TestHarness.scala b/generators/chipyard/src/main/scala/harness/TestHarness.scala new file mode 100644 index 00000000..cb8cfe47 --- /dev/null +++ b/generators/chipyard/src/main/scala/harness/TestHarness.scala @@ -0,0 +1,64 @@ +package chipyard.harness + +import chisel3._ + +import scala.collection.mutable.{ArrayBuffer, LinkedHashMap} +import freechips.rocketchip.diplomacy.{LazyModule} +import org.chipsalliance.cde.config.{Field, Parameters} +import freechips.rocketchip.util.{ResetCatchAndSync} +import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters} + +import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} +import chipyard.iobinders.HasIOBinders +import chipyard.clocking.{SimplePllConfiguration, ClockDividerN} +import chipyard.{ChipTop} + +// ------------------------------- +// Chipyard Test Harness +// ------------------------------- + +case object BuildTop extends Field[Parameters => LazyModule]((p: Parameters) => new ChipTop()(p)) +case object DefaultClockFrequencyKey extends Field[Double](100.0) // MHz +case object HarnessClockInstantiatorKey extends Field[() => HarnessClockInstantiator]() + +trait HasHarnessSignalReferences { + implicit val p: Parameters + val harnessClockInstantiator = p(HarnessClockInstantiatorKey)() + // clock/reset of the chiptop reference clock (can be different than the implicit harness clock/reset) + var refClockFreq: Double = p(DefaultClockFrequencyKey) + def setRefClockFreq(freqMHz: Double) = { refClockFreq = freqMHz } + def getRefClockFreq: Double = refClockFreq + def buildtopClock: Clock + def buildtopReset: Reset + def success: Bool +} + +class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSignalReferences { + val io = IO(new Bundle { + val success = Output(Bool()) + }) + + val buildtopClock = Wire(Clock()) + val buildtopReset = Wire(Reset()) + + val lazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") + val dut = Module(lazyDut.module) + + io.success := false.B + + val success = io.success + + lazyDut match { case d: HasIOBinders => + ApplyHarnessBinders(this, d.lazySystem, d.portMap) + } + + val refClkBundle = harnessClockInstantiator.requestClockBundle("buildtop_reference_clock", getRefClockFreq * (1000 * 1000)) + + buildtopClock := refClkBundle.clock + buildtopReset := WireInit(refClkBundle.reset) + + val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters())) + implicitHarnessClockBundle.clock := clock + implicitHarnessClockBundle.reset := reset + harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle) +} diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index 03aa0b56..2258228e 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -6,7 +6,7 @@ package chipyard.stage.phases import scala.util.Try import scala.collection.mutable -import chipsalliance.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import chisel3.stage.phases.Elaborate import firrtl.AnnotationSeq import firrtl.annotations.{Annotation, NoTargetAnnotation} diff --git a/generators/chipyard/src/main/scala/unittest/TestHarness.scala b/generators/chipyard/src/main/scala/unittest/TestHarness.scala index 8bb4bbd9..a5ca5551 100644 --- a/generators/chipyard/src/main/scala/unittest/TestHarness.scala +++ b/generators/chipyard/src/main/scala/unittest/TestHarness.scala @@ -1,7 +1,7 @@ package chipyard.unittest import chisel3._ -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters class TestHarness(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val success = Output(Bool()) }) diff --git a/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala b/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala index 40e991a2..d3281dc1 100644 --- a/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala +++ b/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala @@ -1,6 +1,6 @@ package chipyard.unittest -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.{ElaborationArtefacts, PlusArgArtefacts} class UnitTestSuite(implicit p: Parameters) extends freechips.rocketchip.unittest.UnitTestSuite { diff --git a/generators/constellation b/generators/constellation index 4606ee19..e9f1c828 160000 --- a/generators/constellation +++ b/generators/constellation @@ -1 +1 @@ -Subproject commit 4606ee19b74d32d165b1708ef6f4ee98baa1c50d +Subproject commit e9f1c828ca5adb4fa46a242cd1798391fc9e6f62 diff --git a/generators/cva6 b/generators/cva6 index 6a6184f2..b2729b3b 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 6a6184f292ea2b81fcc5b3d5186fa31075c1d240 +Subproject commit b2729b3b1784538b3e546446bac74cecde354c93 diff --git a/generators/fft-generator b/generators/fft-generator index a31bd038..be8ab768 160000 --- a/generators/fft-generator +++ b/generators/fft-generator @@ -1 +1 @@ -Subproject commit a31bd038ddf3c941634cb830608edb0bdd6442db +Subproject commit be8ab768bd15824c69531df632478e4429078b94 diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 4d64a8ad..579c2d50 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -6,9 +6,9 @@ import chisel3._ import chisel3.experimental.annotate import chisel3.util.experimental.BoringUtils -import freechips.rocketchip.config.{Field, Config, Parameters} +import org.chipsalliance.cde.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebug} import freechips.rocketchip.amba.axi4.{AXI4Bundle} import freechips.rocketchip.subsystem._ import freechips.rocketchip.tile.{RocketTile} @@ -30,7 +30,6 @@ import cva6.CVA6Tile import boom.common.{BoomTile} import barstools.iocell.chisel._ import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters, IOCellKey} -import chipyard.{HasHarnessSignalReferences} import chipyard.harness._ object MainMemoryConsts { @@ -68,15 +67,16 @@ class WithFireSimIOCellModels extends Config((site, here, up) => { case IOCellKey => FireSimIOCellParams() }) -class WithSerialBridge extends OverrideHarnessBinder({ +class WithTSIBridgeAndHarnessRAMOverSerialTL extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { port => implicit val p = GetSystemParameters(system) - val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) + val bits = port.bits + port.clock := th.buildtopClock val ram = withClockAndReset(th.buildtopClock, th.buildtopReset) { - SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset) + TSIHarness.connectRAM(system.serdesser.get, bits, th.buildtopReset) } - SerialBridge(th.buildtopClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName), th.buildtopReset.asBool) + TSIBridge(th.buildtopClock, ram.module.io.tsi, p(ExtMem).map(_ => MainMemoryConsts.globalName), th.buildtopReset.asBool) } Nil } @@ -125,16 +125,16 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({ axiClockBundle.clock := axiClock axiClockBundle.reset := ResetCatchAndSync(axiClock, th.buildtopReset.asBool) - val serial_bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset) - + val serial_bits = port.bits + port.clock := th.buildtopClock val harnessMultiClockAXIRAM = withClockAndReset(th.buildtopClock, th.buildtopReset) { - SerialAdapter.connectHarnessMultiClockAXIRAM( + TSIHarness.connectMultiClockAXIRAM( system.serdesser.get, serial_bits, axiClockBundle, th.buildtopReset) } - SerialBridge(th.buildtopClock, harnessMultiClockAXIRAM.module.io.tsi_ser, Some(MainMemoryConsts.globalName), th.buildtopReset.asBool) + TSIBridge(th.buildtopClock, harnessMultiClockAXIRAM.module.io.tsi, Some(MainMemoryConsts.globalName), th.buildtopReset.asBool) // connect SimAxiMem (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi4, edge) => @@ -232,7 +232,7 @@ class WithFireSimFAME5 extends ComposeIOBinder({ // Shorthand to register all of the provided bridges above class WithDefaultFireSimBridges extends Config( - new WithSerialBridge ++ + new WithTSIBridgeAndHarnessRAMOverSerialTL ++ new WithNICBridge ++ new WithUARTBridge ++ new WithBlockDeviceBridge ++ @@ -245,7 +245,7 @@ class WithDefaultFireSimBridges extends Config( // Shorthand to register all of the provided mmio-only bridges above class WithDefaultMMIOOnlyFireSimBridges extends Config( - new WithSerialBridge ++ + new WithTSIBridgeAndHarnessRAMOverSerialTL ++ new WithUARTBridge ++ new WithBlockDeviceBridge ++ new WithFASEDBridge ++ diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index bd35341b..a62059e3 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -9,7 +9,7 @@ import chisel3.experimental.{IO} import freechips.rocketchip.prci._ import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} -import freechips.rocketchip.config.{Field, Config, Parameters} +import org.chipsalliance.cde.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName} import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap} diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 2ea848df..621a152c 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -4,7 +4,7 @@ import java.io.File import chisel3._ import chisel3.util.{log2Up} -import freechips.rocketchip.config.{Parameters, Config} +import org.chipsalliance.cde.config.{Parameters, Config} import freechips.rocketchip.groundtest.TraceGenParams import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ @@ -186,6 +186,22 @@ class FireSimRocketConfig extends Config( new chipyard.RocketConfig) // DOC include end: firesimconfig +class FireSimRocket1GiBDRAMConfig extends Config( + new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 1L) ++ + new FireSimRocketConfig) + +class FireSimRocketMMIOOnly1GiBDRAMConfig extends Config( + new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 1L) ++ + new FireSimRocketMMIOOnlyConfig) + +class FireSimRocket4GiBDRAMConfig extends Config( + new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ + new FireSimRocketConfig) + +class FireSimRocketMMIOOnly4GiBDRAMConfig extends Config( + new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ + new FireSimRocketMMIOOnlyConfig) + class FireSimQuadRocketConfig extends Config( new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ diff --git a/generators/gemmini b/generators/gemmini index 686cb15d..80e7376c 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 686cb15dad756887db62460968bc616392bc4341 +Subproject commit 80e7376cf554ed302975d72ed091ac86a9e553e8 diff --git a/generators/hwacha b/generators/hwacha index e1be8e2a..d01ca1e7 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit e1be8e2a41c6bc2239aed4e23355cf34a224f380 +Subproject commit d01ca1e7f8a3ba3f419509273dfef00e41095f6a diff --git a/generators/ibex b/generators/ibex index 626127f2..916fb7a6 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit 626127f229dd6dc926b7670eb4dd138f32a7940a +Subproject commit 916fb7a6ff4a65f989279bcc082676a565beee0c diff --git a/generators/icenet b/generators/icenet index 90d52a6a..ce1ec55c 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 90d52a6a8435c862e6435d04436f587c3b36c8c0 +Subproject commit ce1ec55c1fd9c4339e7c0eec3a82d86041fa5d20 diff --git a/generators/mempress b/generators/mempress index b9eaedc0..295ae085 160000 --- a/generators/mempress +++ b/generators/mempress @@ -1 +1 @@ -Subproject commit b9eaedc061adbbe488f4c094f0ddd2177852e11a +Subproject commit 295ae0854a429182e4a38b120c8771a4e898834e diff --git a/generators/nvdla b/generators/nvdla index 2b17011b..7130a5c0 160000 --- a/generators/nvdla +++ b/generators/nvdla @@ -1 +1 @@ -Subproject commit 2b17011b266025704b958efeeca2363c0cdd446d +Subproject commit 7130a5c0f7016cd177ec9cf908a18edd668660d1 diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 1b169845..92379541 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 1b169845e370e61f9cb765451a37ffc2323719bd +Subproject commit 92379541aaab577f0f3a91c2df747083f2a4ca59 diff --git a/generators/rocket-chip b/generators/rocket-chip index f5ebf26b..25e2c635 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit f5ebf26b369922b2924d71e185c473c0385bf54e +Subproject commit 25e2c63567689ebe1fc5e60fdfe3375a8dba071c diff --git a/generators/sha3 b/generators/sha3 index 8c5d2443..1fa5ef8a 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit 8c5d244303694311c4e63e51915a492491a3f5c7 +Subproject commit 1fa5ef8ae5b67126d709193896e75dba50c5fd28 diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 4273925f..534d3b74 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 4273925fdd5d8872d6b6a8dec6cee3330b9a68c7 +Subproject commit 534d3b74a0f22e67198aa361ae987042ee56dead diff --git a/generators/sifive-cache b/generators/sifive-cache index 850e1215..02e002b3 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit 850e12154c1de6baee9e40094d115e9b85d799b1 +Subproject commit 02e002b324c0e6316234045fa739fdb9d716170d diff --git a/generators/testchipip b/generators/testchipip index dead693f..ebf61569 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit dead693f8f317bfeeb4eb777c4d58c4427fbba31 +Subproject commit ebf61569c5a65ff46ac3ee77fcc3a8404441ab9d diff --git a/generators/tracegen/src/main/scala/Configs.scala b/generators/tracegen/src/main/scala/Configs.scala index ac2477a1..5d4f0211 100644 --- a/generators/tracegen/src/main/scala/Configs.scala +++ b/generators/tracegen/src/main/scala/Configs.scala @@ -2,7 +2,7 @@ package tracegen import chisel3._ import chisel3.util.log2Ceil -import freechips.rocketchip.config.{Config, Parameters} +import org.chipsalliance.cde.config.{Config, Parameters} import freechips.rocketchip.groundtest.{TraceGenParams, TraceGenTileAttachParams} import freechips.rocketchip.subsystem._ import freechips.rocketchip.system.BaseConfig diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index fceb0072..2a0ba3d5 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -1,9 +1,9 @@ package tracegen import chisel3._ -import freechips.rocketchip.config.{Field, Parameters} +import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams} -import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple} +import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple, NullIntSyncSource, IntSyncXbar} import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile} import freechips.rocketchip.subsystem._ import boom.lsu.BoomTraceGenTile @@ -17,6 +17,7 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem case t: GroundTestTile => t.statusNode.makeSink() case t: BoomTraceGenTile => t.statusNode.makeSink() } + lazy val debugNode = IntSyncXbar() := NullIntSyncSource() override lazy val module = new TraceGenSystemModuleImp(this) } diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh index aa78942b..02e1fd81 100755 --- a/scripts/build-setup.sh +++ b/scripts/build-setup.sh @@ -91,6 +91,7 @@ run_step() { # Check for this, since many users will be attempting to use this with gemmini if [ $TOOLCHAIN_TYPE == "esp-tools" ]; then while true; do + printf '\033[2J' read -p "WARNING: You are trying to install the esp-tools toolchain."$'\n'"This should ONLY be used for Hwacha development."$'\n'"Gemmini should be used with riscv-tools."$'\n'"Type \"y\" to continue if this is intended, or \"n\" if not: " validate case "$validate" in y | Y) @@ -113,11 +114,12 @@ if run_step "1"; then # note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154 CONDA_REQS=$CYDIR/conda-reqs CONDA_LOCK_REQS=$CONDA_REQS/conda-lock-reqs + # must match with the file generated by generate-conda-lockfile.sh LOCKFILE=$CONDA_LOCK_REQS/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml if [ "$USE_UNPINNED_DEPS" = true ]; then - # auto-gen the lockfile - conda-lock -f $CONDA_REQS/chipyard.yaml -f $CONDA_REQS/$TOOLCHAIN_TYPE.yaml --lockfile $LOCKFILE + # auto-gen the lockfiles + $CYDIR/scripts/generate-conda-lockfiles.sh fi # use conda-lock to create env @@ -137,7 +139,6 @@ fi # initialize all submodules (without the toolchain submodules) if run_step "2"; then $CYDIR/scripts/init-submodules-no-riscv-tools.sh $FORCE_FLAG - $CYDIR/scripts/init-fpga.sh $FORCE_FLAG fi # build extra toolchain collateral (i.e. spike, pk, riscv-tests, libgloss) diff --git a/scripts/config-finder.py b/scripts/config-finder.py deleted file mode 100755 index a7377939..00000000 --- a/scripts/config-finder.py +++ /dev/null @@ -1,76 +0,0 @@ -#!/usr/bin/env python3 - -import argparse -import subprocess -from collections import defaultdict -import re -from copy import deepcopy -import os - -cy_path = os.path.dirname(os.path.dirname(os.path.realpath(__file__))) - -# from https://gist.github.com/angstwad/bf22d1822c38a92ec0a9 -def deep_merge(a: dict, b: dict) -> dict: - """Merge two dicts and return a singular dict""" - result = deepcopy(a) - for bk, bv in b.items(): - av = result.get(bk) - if isinstance(av, dict) and isinstance(bv, dict): - result[bk] = deep_merge(av, bv) - else: - result[bk] = deepcopy(bv) - return result - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description='Pretty print all configs given a filelist of scala files') - parser.add_argument('FILE', type=str, help='Filelist of scala files to search within') - parser.add_argument('-l', '--levels', default=0, type=int, help='Number of levels to recursively look for configs') - args = parser.parse_args() - - files = [] - with open(args.FILE, 'r') as f: - files = f.read().splitlines() - - cmd = ['grep', '-o', r"class \+.* \+extends \+Config"] + files - r = subprocess.run(cmd, check=True, capture_output=True) - - base_file_path_dict = defaultdict(list) - for l in r.stdout.decode("UTF-8").splitlines(): - match = re.match(r"^(.*):class +([a-zA-Z_$][a-zA-Z\d_$]*).* +extends", l) - if match: - base_file_path_dict[match.group(1)].append(match.group(2)) - - levels = [] - for level in range(args.levels): - if level == 0: - # use the base - dict_to_use = base_file_path_dict - else: - # use the level-1 dict - assert len(levels) > 0 - dict_to_use = levels[-1] - - file_path_dict = defaultdict(list) - - for configs in dict_to_use.values(): - for config in configs: - cmd = ['grep', '-o', r"class \+.* \+extends \+" + f"{config}"] + files - r = subprocess.run(cmd, capture_output=True) - - for l in r.stdout.decode("UTF-8").splitlines(): - match = re.match(r"^(.*):class +([a-zA-Z_$][a-zA-Z\d_$]*).* +extends", l) - if match: - file_path_dict[match.group(1)].append(match.group(2)) - - levels.append(file_path_dict) - - final_dict = base_file_path_dict - for dct in levels: - final_dict = deep_merge(final_dict, dct) - - print(f"Finding all one-line config. fragments (up to {args.levels} levels)\n") - for k, v in final_dict.items(): - print(f"{k.replace(cy_path, 'chipyard')}:") - for e in v: - print(f" {e}") - print("") diff --git a/scripts/generate-ckpt.sh b/scripts/generate-ckpt.sh new file mode 100755 index 00000000..0f8b1e8b --- /dev/null +++ b/scripts/generate-ckpt.sh @@ -0,0 +1,141 @@ +#!/bin/bash + +set -e + +usage() { + echo "Usage: $0 [OPTIONS]" + echo "" + echo "Options" + echo " --help -h : Display this message" + echo " -n : Number of harts" + echo " -b : Binary to run in spike" + echo " -p : PC to take checkpoint at [default 0x80000000]" + echo " -i : Instructions after PC to take checkpoint at [default 0]" + echo " -m : ISA to pass to spike for checkpoint generation [default rv64gc]" + echo " -o : Output directory to store the checkpoint in. [default ...loadarch]" + exit "$1" +} + +NHARTS=1 +BINARY="" +PC="0x80000000" +INSNS=0 +ISA="rv64gc" +OUTPATH="" +while [ "$1" != "" ]; +do + case $1 in + -h | --help ) + usage 3 ;; + -n ) + shift + NHARTS=$1 ;; + -b ) + shift + BINARY=$1 ;; + -p ) + shift + PC=$1 ;; + -i ) + shift + INSNS=$1 ;; + -m ) + shift + ISA=$1 ;; + -o ) + shift + OUTPATH=$1 ;; + * ) + error "Invalid option $1" + usage 1 ;; + esac + shift +done + +BASEMEM="$((0x80000000)):$((0x10000000))" +SPIKEFLAGS="-p$NHARTS --pmpregions=0 --isa=$ISA -m$BASEMEM" +BASENAME=$(basename -- $BINARY) + +if [ -z "$OUTPATH" ] ; then + OUTPATH=$BASENAME.$PC.$INSNS.loadarch +fi + +echo "Generating loadarch directory $OUTPATH" +rm -rf $OUTPATH +mkdir -p $OUTPATH + +LOADARCH_FILE=$OUTPATH/loadarch +RAWMEM_ELF=$OUTPATH/raw.elf +LOADMEM_ELF=$OUTPATH/mem.elf +CMDS_FILE=$OUTPATH/cmds_tmp.txt +SPIKECMD_FILE=$OUTPATH/spikecmd.sh + +echo "Generating state capture spike interactive commands in $CMDS_FILE" +echo "until pc 0 $PC" >> $CMDS_FILE +echo "rs $INSNS" >> $CMDS_FILE +echo "dump" >> $CMDS_FILE +for (( h=0; h<$NHARTS; h++ )) +do + echo "pc $h" >> $CMDS_FILE + echo "priv $h" >> $CMDS_FILE + echo "reg $h fcsr" >> $CMDS_FILE + + echo "reg $h vstart" >> $CMDS_FILE + echo "reg $h vxsat" >> $CMDS_FILE + echo "reg $h vxrm" >> $CMDS_FILE + echo "reg $h vcsr" >> $CMDS_FILE + echo "reg $h vtype" >> $CMDS_FILE + + echo "reg $h stvec" >> $CMDS_FILE + echo "reg $h sscratch" >> $CMDS_FILE + echo "reg $h sepc" >> $CMDS_FILE + echo "reg $h scause" >> $CMDS_FILE + echo "reg $h stval" >> $CMDS_FILE + echo "reg $h satp" >> $CMDS_FILE + + echo "reg $h mstatus" >> $CMDS_FILE + echo "reg $h medeleg" >> $CMDS_FILE + echo "reg $h mideleg" >> $CMDS_FILE + echo "reg $h mie" >> $CMDS_FILE + echo "reg $h mtvec" >> $CMDS_FILE + echo "reg $h mscratch" >> $CMDS_FILE + echo "reg $h mepc" >> $CMDS_FILE + echo "reg $h mcause" >> $CMDS_FILE + echo "reg $h mtval" >> $CMDS_FILE + echo "reg $h mip" >> $CMDS_FILE + + echo "reg $h mcycle" >> $CMDS_FILE + echo "reg $h minstret" >> $CMDS_FILE + + echo "mtime" >> $CMDS_FILE + echo "mtimecmp $h" >> $CMDS_FILE + + for (( fr=0; fr<32; fr++ )) + do + echo "freg $h $fr" >> $CMDS_FILE + done + for (( xr=0; xr<32; xr++ )) + do + echo "reg $h $xr" >> $CMDS_FILE + done + echo "vreg $h" >> $CMDS_FILE +done +echo "quit" >> $CMDS_FILE + +echo "spike -d --debug-cmd=$CMDS_FILE $SPIKEFLAGS $BINARY" > $SPIKECMD_FILE + +echo "Capturing state at checkpoint to spikeout" +spike -d --debug-cmd=$CMDS_FILE $SPIKEFLAGS $BINARY 2> $LOADARCH_FILE + + +echo "Finding tohost/fromhost in elf file" +TOHOST=$(riscv64-unknown-elf-nm $BINARY | grep tohost | head -c 16) +FROMHOST=$(riscv64-unknown-elf-nm $BINARY | grep fromhost | head -c 16) + +echo "Compiling memory to elf" +riscv64-unknown-elf-objcopy -I binary -O elf64-littleriscv mem.0x80000000.bin $RAWMEM_ELF +rm -rf mem.0x80000000.bin + +riscv64-unknown-elf-ld -Tdata=0x80000000 -nmagic --defsym tohost=0x$TOHOST --defsym fromhost=0x$FROMHOST -o $LOADMEM_ELF $RAWMEM_ELF +rm -rf $RAWMEM_ELF + diff --git a/scripts/generate-conda-lockfiles.sh b/scripts/generate-conda-lockfiles.sh new file mode 100755 index 00000000..f2e81106 --- /dev/null +++ b/scripts/generate-conda-lockfiles.sh @@ -0,0 +1,18 @@ +#!/usr/bin/env bash + +set -ex + +CUR_DIR=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd ) + +REQS_DIR="$CUR_DIR/../conda-reqs" +if [ ! -d "$REQS_DIR" ]; then + echo "$REQS_DIR does not exist, make sure you're calling this script from chipyard/" + exit 1 +fi + +for TOOLCHAIN_TYPE in riscv-tools esp-tools; do + # note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154 + LOCKFILE=$REQS_DIR/conda-lock-reqs/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml + + conda-lock -f "$REQS_DIR/chipyard.yaml" -f "$REQS_DIR/$TOOLCHAIN_TYPE.yaml" -p linux-64 --lockfile $LOCKFILE +done diff --git a/scripts/init-fpga.sh b/scripts/init-fpga.sh deleted file mode 100755 index 0182bd4b..00000000 --- a/scripts/init-fpga.sh +++ /dev/null @@ -1,12 +0,0 @@ -#!/usr/bin/env bash - -# exit script if any command fails -set -e -set -o pipefail - -# Enable submodule update for FPGA tools. -git config --unset submodule.fpga/fpga-shells.update || : -# Initialize local FPGA tools. -git submodule update --init --recursive fpga/fpga-shells -# Disable submodule update for FPGA tools. -git config submodule.fpga/fpga-shells.update none diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index 3f939bc2..bd723595 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -65,6 +65,7 @@ restore_bash_options if [ "$git_tag_rc" -ne 0 ]; then if [ "$FORCE" == false ]; then while true; do + printf '\033[2J' read -p "WARNING: You are not on an official release of Chipyard."$'\n'"Type \"y\" to continue if this is intended or \"n\" if not: " validate case "$validate" in y | Y) @@ -106,8 +107,7 @@ cd "$RDIR" software/coremark \ software/firemarshal \ software/spec2017 \ - vlsi/hammer-mentor-plugins \ - fpga/fpga-shells + vlsi/hammer-mentor-plugins do "$1" "${name%/}" done diff --git a/scripts/repo-clean.sh b/scripts/repo-clean.sh index 9c6d0389..0ecdbb27 100755 --- a/scripts/repo-clean.sh +++ b/scripts/repo-clean.sh @@ -21,7 +21,7 @@ rm -rf $RDIR/toolchains/esp-tools/riscv-tests/build.log popd ) ( - pushd $RDIR/tools/api-config-chipsalliance + pushd $RDIR/tools/cde git config --local status.showUntrackedFiles no popd ) diff --git a/scripts/smartelf2hex.sh b/scripts/smartelf2hex.sh deleted file mode 100755 index cc2ea2f8..00000000 --- a/scripts/smartelf2hex.sh +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env bash - -# This script find the appropriate arguments to pass to elf2hex by inspecting the given RISC-V elf binary -# First and only argument is the binary to be converted. -# The output of this script should be redirected to a file (as with normal elf2hex). - -binary=$1 -segments=`readelf --segments --wide $binary` -entry_hex=`echo -e "$segments" | grep "Entry point" | cut -f3 -d' ' | sed 's/0x//' | tr [:lower:] [:upper:]` -entry_dec=`bc <<< "ibase=16;$entry_hex"` -length_hex=`echo "$segments" | grep "LOAD\|TLS" | tail -n 1 | tr -s [:space:] | cut -f4,7 -d' '` -length_dec=`echo $length_hex | tr -d x | tr [:lower:] [:upper:] | tr ' ' + | sed 's/^/ibase=16;/' | sed "s/$/-$entry_hex/" | bc` -power_2_length=`echo "x=l($length_dec)/l(2); scale=0; 2^((x+1)/1)" | bc -l` -width=64 -depth=$((power_2_length / width)) -elf2hex $width $depth $binary $entry_dec diff --git a/scripts/split-bb-files.py b/scripts/split-bb-files.py deleted file mode 100755 index 959a10a2..00000000 --- a/scripts/split-bb-files.py +++ /dev/null @@ -1,82 +0,0 @@ -#!/usr/bin/env python3 - -import json -import argparse -from collections import defaultdict - -# Schema of *.f emitted by circt -""" -//gen-collateral/SimUART.cc -//gen-collateral/AsyncQueueSource.sv -//gen-collateral/AsyncQueueSink.sv -//gen-collateral/AsyncQueueSource_1.sv -//gen-collateral/AsyncQueueSink_1.sv -//gen-collateral/AsyncQueueSource_2.sv -//gen-collateral/AsyncQueueSink_2.sv -//gen-collateral/AsyncResetSynchronizerShiftReg_w4_d3_i0.sv -""" - -def bfs_collect_submodules(tree): - output = set() - q = [(tree['instance_name'], tree['module_name'], tree['instances'])] - - while len(q) != 0: - front = q[0] - q.pop(0) - - (inst, mod, child) = front - output.add(mod) - for c in child: - q.append((c['instance_name'], c['module_name'], c['instances'])) - return output - -def write_lines_to_file(lines, file_path): - with open(file_path, "w") as fp: - for line in lines: - fp.write("%s\n" % line) - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description='Create *.model.bb.f and *.top.bb.f blackbox filelists') - parser.add_argument('--in-bb-f', type=str, required=True, help='All blackbox files filelist (includes both MODEL/TOP files)') - parser.add_argument('--in-top-hrchy-json', type=str, required=True, help='List containing hierarchy of top modules (top-module-hierarchy.json)') - parser.add_argument('--in-anno-json', type=str, required=True, help='Anno. file with blackbox annotations') - parser.add_argument('--out-top-bb-f', type=str, required=True, help='List of blackbox files for TOP') - parser.add_argument('--out-model-bb-f', type=str, required=True, help='List of blackbox files for MODEL') - args = parser.parse_args() - - # module_path -> list of bb paths (not fully resolved paths) - mod_bb_dict = defaultdict(list) - with open(args.in_anno_json, "r") as f: - anno_data = json.load(f) - for anno in anno_data: - if 'BlackBoxInlineAnno' in anno['class']: - mod_bb_dict[anno['target']].append(anno['name']) - if 'BlackBoxPathAnno' in anno['class']: - mod_bb_dict[anno['target']].append(anno['path']) - - with open(args.in_top_hrchy_json) as ihj: - ihj_data = json.load(ihj) - top_inner_modules = bfs_collect_submodules(ihj_data) - - with open(args.in_bb_f) as ibf: - lines = ibf.read().splitlines() - - tbfs = set() - for mod_path, bb_files in mod_bb_dict.items(): - leaf_mod = mod_path.split('.')[-1] - - # if matched, add the fully resolved path to the top bb filelist - if leaf_mod in top_inner_modules: - for line in lines: - for bb_file in bb_files: - if bb_file in line: - tbfs.add(line) - - # now tbfs should be complete (need to remove tbf files from original bb file for model bb) - mbfs = set() - for line in lines: - if not line in tbfs: - mbfs.add(line) - - write_lines_to_file(tbfs, args.out_top_bb_f) - write_lines_to_file(mbfs, args.out_model_bb_f) diff --git a/scripts/split-module-files.py b/scripts/split-module-files.py deleted file mode 100755 index 64fe5707..00000000 --- a/scripts/split-module-files.py +++ /dev/null @@ -1,111 +0,0 @@ -#!/usr/bin/env python3 - -import json -import argparse -from typing import List, Optional - -# Schema of json emitted by circt -""" -{ - "instance_name": "TestHarness", - "module_name": "TestHarness", - "instances": [ - { - "instance_name": "chiptop", - "module_name": "ChipTop", - "instances": [ - { - "instance_name": "system", - "module_name": "DigitalTop", - "instances": [ ] - }, ... - ] - }, - { - "instance_name": "simdram", - "module_name": "SimDRAM", - "instances": [] - }, - ] -} -""" - -def get_modules(js: dict) -> List[str]: - if 'instances' not in js: - return js['module_name'] - else: - mods = [] - for mod in js['instances']: - mods.extend(get_modules(mod)) - return [js['module_name']] + mods - -def find_mod_by_name(js: dict, name: str) -> Optional[List[dict]]: - if 'instances' not in js: - return None - else: - mods = [] - for mod in js['instances']: - if mod['module_name'] == name: - mods.append(mod) - other_mods = find_mod_by_name(mod, name) - if other_mods is not None: - mods.extend(other_mods) - return mods - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description='Convert CIRCT (firtool) hierarchy JSON into DUT and test harness filelists') - parser.add_argument('--model-hier-json', type=str, required=True, help='Path to hierarchy JSON emitted by firtool. Must include DUT as a module.') - parser.add_argument('--dut', type=str, required=True, help='Name of the DUT module.') - parser.add_argument('--out-dut-filelist', type=str, required=True, help='Path to output filelist including all modules under the DUT.') - parser.add_argument('--out-model-filelist', type=str, required=True, help='Path to output filelist including all modules under the top-most module but not modules under the DUT.') - parser.add_argument('--in-all-filelist', type=str, required=True, help='Path to input filelist that has all modules (relative paths).') - parser.add_argument('--target-dir', type=str, required=True, help='Path to where module sources are located (combined with --in-all-filelist gives the absolute path to module sources).') - args = parser.parse_args() - - with open(args.model_hier_json) as f: - j = json.load(f) - - dut_tops = find_mod_by_name(j, args.dut) - assert dut_tops is not None - assert len(dut_tops) == 1 - dut_top = dut_tops[0] - - dut_mods = set(get_modules(dut_top)) - model_mods = set(get_modules(j)) - dut_mods - both_mods = dut_mods.intersection(model_mods) - - assert len(both_mods) == 0 - - with open(args.out_dut_filelist, 'w') as df, \ - open(args.in_all_filelist) as fl: - # add paths that correspond to modules to output file - for path in fl: - writeOut = False - for dm in dut_mods: - if dm in path: - writeOut = True - break - - # prepend the target directory to get filelist with absolute paths - if writeOut: - if not args.target_dir in path: - df.write(f"{args.target_dir}/{path}") - else: - df.write(f"{path}") - - with open(args.out_model_filelist, 'w') as df, \ - open(args.in_all_filelist) as fl: - # add paths that correspond to modules to output file - for path in fl: - writeOut = False - for dm in model_mods: - if dm in path: - writeOut = True - break - - # prepend the target directory to get filelist with absolute paths - if writeOut: - if not args.target_dir in path: - df.write(f"{args.target_dir}/{path}") - else: - df.write(f"{path}") diff --git a/scripts/uniquify-module-names.py b/scripts/uniquify-module-names.py new file mode 100755 index 00000000..75fc8c85 --- /dev/null +++ b/scripts/uniquify-module-names.py @@ -0,0 +1,207 @@ +#!/usr/bin/env python3 + +import json +import argparse +import shutil +import os +import sys + + +parser = argparse.ArgumentParser(description="") +parser.add_argument("--model-hier-json", type=str, required=True, help="Path to hierarchy JSON emitted by firtool. Must include DUT as a module.") +parser.add_argument("--top-hier-json", type=str, required=True, help="Path to hierarchy JSON emitted by firtool. Must include DUT as a module.") +parser.add_argument('--in-all-filelist', type=str, required=True, help='Path to input filelist that has all modules (relative paths).') +parser.add_argument("--dut", type=str, required=True, help="Name of the DUT module.") +parser.add_argument("--model", type=str, required=True, help="Name of the Model module.") +parser.add_argument('--out-dut-filelist', type=str, required=True, help='Path to output filelist including all modules under the DUT.') +parser.add_argument('--out-model-filelist', type=str, required=True, help='Path to output filelist including all modules under the MODEL.') +parser.add_argument("--out-model-hier-json", type=str, required=True, help="Path to updated hierarchy JSON emitted by this script.") +parser.add_argument('--target-dir', type=str, required=True, help='Path to where module sources are located (combined with --in-all-filelist gives the absolute path to module sources).') +parser.add_argument("--gcpath", type=str, required=True, help="Path to gen-collateral") +args = parser.parse_args() + +MODEL_SFX=args.model + "_UNIQUIFIED" + + +def bash(cmd): + fail = os.system(cmd) + if fail: + print(f'[*] failed to execute {cmd}') + sys.exit(1) + else: + print(cmd) + +def bfs_collect_modules(tree, child_to_ignore = None): + q = [(tree['instance_name'], tree['module_name'], tree['instances'])] + + modules = list() + while len(q) != 0: + front = q[0] + q.pop(0) + + (inst, mod, child) = front + modules.append(mod) + for c in child: + if c['module_name'] != child_to_ignore: + q.append((c['instance_name'], c['module_name'], c['instances'])) + return modules + +def get_modules_in_verilog_file(file): + module_names = list() + with open(file) as f: + lines = f.readlines() + for line in lines: + words = line.split() + if len(words) > 0 and words[0] == "module": + module_names.append(words[1].replace("(", "").replace(")", "").replace(";", "")) + return module_names + +def get_modules_in_filelist(verilog_module_filename, cc_filelist): + with open(args.in_all_filelist) as fl: + lines = fl.readlines() + for line in lines: + path = line.strip() + basepath = os.path.basename(path) + ext = basepath.split(".")[-1] + + if (ext == "v") or (ext == "sv"): + modules = get_modules_in_verilog_file(os.path.join(args.gcpath, basepath)) + for module in modules: + verilog_module_filename[module] = basepath + else: + cc_filelist.append(basepath) + return (verilog_module_filename, cc_filelist) + +def get_modules_under_hier(hier, child_to_ignore=None): + with open(hier) as hj: + hj_data = json.load(hj) + modules_under_hier = set(bfs_collect_modules(hj_data, child_to_ignore=child_to_ignore)) + return modules_under_hier + +def write_verilog_filelist(modules, verilog_module_filename, out_filelist): + written_files = set() + existing_modules = verilog_module_filename.keys() + + with open(out_filelist, "w") as df: + for module in modules: + if module in existing_modules: + verilog_filename = verilog_module_filename[module] + if verilog_filename not in written_files: + written_files.add(verilog_filename) + if args.target_dir in verilog_filename: + df.write(f"{verilog_filename}\n") + else: + df.write(f"{args.target_dir}/{verilog_filename}\n") + return written_files + +def write_cc_filelist(filelist, out_filelist): + with open(out_filelist, "a") as df: + for path in filelist: + file = os.path.basename(path) + df.write(f"{args.target_dir}/{file}\n") + +def generate_copy(c, sfx): + (cur_name, ext) = os.path.splitext(c) + new_name = cur_name + "_" + sfx + new_file = new_name + ext + + cur_file = os.path.join(args.gcpath, c) + new_file = os.path.join(args.gcpath, new_file) + + shutil.copy(cur_file, new_file) + bash(f"sed -i s/\"module {cur_name}\"/\"module {new_name}\"/ {new_file}") + return new_file + +def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename): + q = [(tree['instance_name'], tree['module_name'], tree['instances'], None)] + updated_submodule = set() + existing_modules = verilog_module_filename.keys() + + while len(q) != 0: + front = q[0] + q.pop(0) + (inst, mod, child, parent) = front + + # external module + if mod not in existing_modules: + assert(len(child) == 0) + continue + + cur_file = verilog_module_filename[mod] + + # if the module is common, make a copy & update its instance in its parent + new_mod = mod + if mod in common_fnames: + try: + new_file = generate_copy(cur_file, MODEL_SFX) + if parent is not None and ((parent, mod) not in updated_submodule): + parent_file = os.path.join(args.gcpath, verilog_module_filename[parent]) + bash(f"sed -i s/\"{mod} \"/\"{mod}_{MODEL_SFX} \"/ {parent_file}") + updated_submodule.add((parent, mod)) + + # add the uniquified module to the verilog_modul_filename dict + new_mod = mod + "_" + MODEL_SFX + verilog_module_filename[new_mod] = new_file + except: + print(f"No corresponding file for {cur_file}") + + # traverse its children + for c in child: + if c['module_name'] != args.dut: + q.append((c['instance_name'], c['module_name'], c['instances'], new_mod)) + +def dfs_update_modules(tree, common_fnames, visited): + # List of direct submodules to update + childs_to_update = list() + for child in tree['instances']: + # We don't have to change stuff that are under the dut + if (child['module_name'] == args.dut): + continue + if dfs_update_modules(child, common_fnames, visited): + childs_to_update.append(child['module_name']) + if (child['module_name']) in common_fnames: + child['module_name'] = child['module_name'] + "_" + MODEL_SFX + + cur_module = tree['module_name'] + new_file = None + + # cur_file is in the common list, or is a ancestor of of them, generate a new file + if (cur_module in common_fnames) or len(childs_to_update) > 0: + new_file = 1 + + visited.add(cur_module) + return (new_file is not None) + +def uniquify_modules_under_model(modules_under_model, common_modules, verilog_module_filename): + with open(args.model_hier_json) as imhj: + imhj_data = json.load(imhj) + visited = set() + bfs_uniquify_modules(imhj_data, common_modules, verilog_module_filename) + dfs_update_modules (imhj_data, common_modules, visited) + + with open(args.out_model_hier_json, "w+") as out_file: + json.dump(imhj_data, out_file, indent=2) + +def main(): + verilog_module_filename = dict() + cc_filelist = list() + get_modules_in_filelist(verilog_module_filename, cc_filelist) + + modules_under_model = get_modules_under_hier(args.model_hier_json, args.dut) + modules_under_top = get_modules_under_hier(args.top_hier_json) + common_modules = modules_under_top.intersection(modules_under_model) + + # write top filelist + write_verilog_filelist(modules_under_top, verilog_module_filename, args.out_dut_filelist) + + # rename modules that are common + uniquify_modules_under_model(modules_under_model, common_modules, verilog_module_filename) + uniquified_modules_under_model = get_modules_under_hier(args.out_model_hier_json, args.dut) + + # write model filelist + write_verilog_filelist(uniquified_modules_under_model, verilog_module_filename, args.out_model_filelist) + write_cc_filelist (cc_filelist, args.out_model_filelist) + + +if __name__=="__main__": + main() diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk index 0736b43c..c2ae022c 100644 --- a/sims/common-sim-flags.mk +++ b/sims/common-sim-flags.mk @@ -33,3 +33,17 @@ SIM_LDFLAGS = \ -lfesvr \ -ldramsim \ $(EXTRA_SIM_LDFLAGS) + +CLOCK_PERIOD ?= 1.0 +RESET_DELAY ?= 777.7 + +SIM_PREPROC_DEFINES = \ + +define+CLOCK_PERIOD=$(CLOCK_PERIOD) \ + +define+RESET_DELAY=$(RESET_DELAY) \ + +define+PRINTF_COND=$(TB).printf_cond \ + +define+STOP_COND=!$(TB).reset \ + +define+MODEL=$(MODEL) \ + +define+RANDOMIZE_MEM_INIT \ + +define+RANDOMIZE_REG_INIT \ + +define+RANDOMIZE_GARBAGE_ASSIGN \ + +define+RANDOMIZE_INVALID_ASSIGN diff --git a/sims/firesim b/sims/firesim index 68e51138..966e0990 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 68e5113887d36e87bb6202e7fd1e7e51e786a91b +Subproject commit 966e09907cde52f0ce68eb654bf6020b5b97a6c3 diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index b6f11a80..fc0a9fdb 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -25,7 +25,7 @@ sim_prefix = simv sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -include $(base_dir)/vcs.mk +include $(sim_dir)/vcs.mk .PHONY: default debug default: $(sim) @@ -56,7 +56,7 @@ include $(base_dir)/common.mk ######################################################################################### VCS = vcs -full64 -VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(PREPROC_DEFINES) +VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(SIM_PREPROC_DEFINES) $(VCS_PREPROC_DEFINES) ######################################################################################### # vcs build paths diff --git a/vcs.mk b/sims/vcs/vcs.mk similarity index 80% rename from vcs.mk rename to sims/vcs/vcs.mk index edd19f8c..f816f102 100644 --- a/vcs.mk +++ b/sims/vcs/vcs.mk @@ -53,18 +53,9 @@ VCS_NONCC_OPTS = \ -debug_pp \ +incdir+$(GEN_COLLATERAL_DIR) -PREPROC_DEFINES = \ - +define+VCS \ - +define+CLOCK_PERIOD=$(CLOCK_PERIOD) \ - +define+RESET_DELAY=$(RESET_DELAY) \ - +define+PRINTF_COND=$(TB).printf_cond \ - +define+STOP_COND=!$(TB).reset \ - +define+MODEL=$(MODEL) \ - +define+RANDOMIZE_MEM_INIT \ - +define+RANDOMIZE_REG_INIT \ - +define+RANDOMIZE_GARBAGE_ASSIGN \ - +define+RANDOMIZE_INVALID_ASSIGN +VCS_PREPROC_DEFINES = \ + +define+VCS ifndef USE_VPD -PREPROC_DEFINES += +define+FSDB +VCS_PREPROC_DEFINES += +define+FSDB endif diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 098326be..11b80331 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -28,8 +28,6 @@ sim_prefix = simulator sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -WAVEFORM_FLAG=-v$(sim_out_name).vcd - include $(base_dir)/sims/common-sim-flags.mk # If verilator seed unspecified, verilator uses srand as random seed @@ -47,23 +45,7 @@ debug: $(sim_debug) # simulaton requirements ######################################################################################### SIM_FILE_REQS += \ - $(CHIPYARD_RSRCS_DIR)/csrc/cy-emulator.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \ - -# the following files are needed for emulator.cc to compile (even if they aren't part of the RTL build) -SIM_FILE_REQS += \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \ - $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \ - $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc + $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v # copy files and add -FI for *.h files in *.f $(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(GEN_COLLATERAL_DIR) @@ -87,12 +69,15 @@ HELP_COMPILATION_VARIABLES += \ " 'all' if full verilator runtime profiling" \ " 'threads' if runtime thread profiling only" \ " VERILATOR_THREADS = how many threads the simulator will use (default 1)" \ -" VERILATOR_FST_MODE = enable FST waveform instead of VCD. use with debug build" +" USE_FST = set to '1' to build Verilator simulator to emit FST instead of VCD." + +HELP_SIMULATION_VARIABLES += \ +" USE_FST = set to '1' to run Verilator simulator emitting FST instead of VCD." ######################################################################################### # verilator/cxx binary and flags ######################################################################################### -VERILATOR := verilator --cc --exe +VERILATOR := verilator --main --timing --cc --exe #---------------------------------------------------------------------------------------- # user configs @@ -107,10 +92,11 @@ RUNTIME_PROFILING_VFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),\ VERILATOR_THREADS ?= 1 RUNTIME_THREADS := --threads $(VERILATOR_THREADS) --threads-dpi all -VERILATOR_FST_MODE ?= 0 -TRACING_OPTS := $(if $(filter $(VERILATOR_FST_MODE),0),\ +USE_FST ?= 0 +TRACING_OPTS := $(if $(filter $(USE_FST),0),\ --trace,--trace-fst --trace-threads 1) -TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE) +# TODO: consider renaming +vcdfile in TestDriver.v to +waveformfile (or similar) +WAVEFORM_FLAG := +vcdfile=$(sim_out_name).$(if $(filter $(USE_FST),0),vcd,fst) #---------------------------------------------------------------------------------------- # verilation configuration/optimization @@ -153,9 +139,8 @@ TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 # see: https://github.com/ucb-bar/riscv-mini/issues/31 MAX_WIDTH_OPTS = $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 > 4.016) { print "--max-num-width 1048576"; }') -PREPROC_DEFINES := \ - +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ - +define+STOP_COND=\$$c\(\"done_reset\"\) +VERILATOR_PREPROC_DEFINES = \ + +define+VERILATOR VERILATOR_NONCC_OPTS = \ $(RUNTIME_PROFILING_VFLAGS) \ @@ -165,8 +150,9 @@ VERILATOR_NONCC_OPTS = \ -Wno-fatal \ $(TIMESCALE_OPTS) \ $(MAX_WIDTH_OPTS) \ - $(PREPROC_DEFINES) \ - --top-module $(VLOG_MODEL) \ + $(SIM_PREPROC_DEFINES) \ + $(VERILATOR_PREPROC_DEFINES) \ + --top-module $(TB) \ --vpi \ -f $(sim_common_files) @@ -176,12 +162,8 @@ VERILATOR_NONCC_OPTS = \ VERILATOR_CXXFLAGS = \ $(SIM_CXXFLAGS) \ $(RUNTIME_PROFILING_CFLAGS) \ - $(TRACING_CFLAGS) \ - -D__STDC_FORMAT_MACROS \ - -DTEST_HARNESS=V$(VLOG_MODEL) \ -DVERILATOR \ - -include $(build_dir)/$(long_name).plusArgs \ - -include $(GEN_COLLATERAL_DIR)/verilator.h + -include $(build_dir)/$(long_name).plusArgs VERILATOR_LDFLAGS = $(SIM_LDFLAGS) @@ -200,11 +182,11 @@ VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) model_dir = $(build_dir)/$(long_name) model_dir_debug = $(build_dir)/$(long_name).debug -model_header = $(model_dir)/V$(VLOG_MODEL).h -model_header_debug = $(model_dir_debug)/V$(VLOG_MODEL).h +model_header = $(model_dir)/V$(TB).h +model_header_debug = $(model_dir_debug)/V$(TB).h -model_mk = $(model_dir)/V$(VLOG_MODEL).mk -model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk +model_mk = $(model_dir)/V$(TB).mk +model_mk_debug = $(model_dir_debug)/V$(TB).mk ######################################################################################### # build makefile fragment that builds the verilator sim rules @@ -218,17 +200,17 @@ $(model_mk): $(sim_common_files) $(EXTRA_SIM_REQS) $(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(model_dir_debug) mkdir -p $(model_dir_debug) - $(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" + $(VERILATOR) $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" touch $@ ######################################################################################### # invoke make to make verilator sim rules ######################################################################################### $(sim): $(model_mk) $(dramsim_lib) - $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(VLOG_MODEL).mk + $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(TB).mk $(sim_debug): $(model_mk_debug) $(dramsim_lib) - $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(VLOG_MODEL).mk + $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(TB).mk ######################################################################################### # create a verilator vpd rule diff --git a/software/embench/build.sh b/software/embench/build.sh new file mode 100755 index 00000000..2d22166c --- /dev/null +++ b/software/embench/build.sh @@ -0,0 +1,23 @@ +#!/usr/bin/env bash + +set -e + +echo "Building embench-iot for riscv64" +BUILDDIR=$(pwd)/build +mkdir -p $BUILDDIR + +cd embench-iot +# use the riscv32 target, but use riscv64 compiler +./build_all.py --arch riscv32 --chip generic --board ri5cyverilator --cc riscv64-unknown-elf-gcc --cflags="-c -O2 -ffunction-sections -mabi=lp64d -specs=htif_nano.specs" --ldflags="-Wl,-gc-sections -specs=htif_nano.specs" --user-libs="-lm" --clean -v + +echo "Copying binaries to $BUILDDIR" +bmarks=("aha-mont64" "crc32" "cubic" "edn" "huffbench" + "matmult-int" "minver" "nbody" "nettle-aes" + "nettle-sha256" "nsichneu" "picojpeg" + "qrduino" "sglib-combined" "slre" "st" + "statemate" "ud" "wikisort") +for bmark in "${bmarks[@]}" +do + cp bd/src/$bmark/$bmark $BUILDDIR/ +done + diff --git a/software/embench/embench-iot b/software/embench/embench-iot new file mode 160000 index 00000000..d9b30cdf --- /dev/null +++ b/software/embench/embench-iot @@ -0,0 +1 @@ +Subproject commit d9b30cdf805133bef9db5f7ecf84ae1ce8124291 diff --git a/software/firemarshal b/software/firemarshal index 12784a42..fb93e311 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 12784a42cb1b2188536ef5bfc123f800374d3177 +Subproject commit fb93e3116fed07191e669291b941e9eabb565ee3 diff --git a/software/tutorial/.gitignore b/software/tutorial/.gitignore new file mode 100644 index 00000000..08047cf6 --- /dev/null +++ b/software/tutorial/.gitignore @@ -0,0 +1 @@ +overlay diff --git a/software/tutorial/build.sh b/software/tutorial/build.sh new file mode 100755 index 00000000..d84c5c3b --- /dev/null +++ b/software/tutorial/build.sh @@ -0,0 +1,21 @@ +#!/bin/bash + +set -ex + +CYDIR=$(git rev-parse --show-toplevel) +G_DIR=$CYDIR/generators/gemmini/software/gemmini-rocc-tests +O_DIR=$CYDIR/software/tutorial/overlay/root + +echo "Building Gemmini RoCC tests" +cd $G_DIR + +./build.sh imagenet +cd build +rm -rf $O_DIR +mkdir -p $O_DIR +cp -r imagenet/resnet50-baremetal $O_DIR/ +cp -r imagenet/resnet50-linux $O_DIR/ +cp -r imagenet/mobilenet-baremetal $O_DIR/ +cp -r imagenet/mobilenet-linux $O_DIR/ + +echo "Complete!" diff --git a/software/tutorial/marshal-configs/mobilenet-baremetal.yaml b/software/tutorial/marshal-configs/mobilenet-baremetal.yaml new file mode 100644 index 00000000..3b2df3e6 --- /dev/null +++ b/software/tutorial/marshal-configs/mobilenet-baremetal.yaml @@ -0,0 +1,8 @@ +{ + "name" : "mobilenet-baremetal", + "base" : "bare-base.json", + "workdir" : "..", + "host-init" : "build.sh", + "bin" : "overlay/root/mobilenet-baremetal", + "spike-args" : "--extension=gemmini" +} diff --git a/software/tutorial/marshal-configs/resnet50-baremetal.yaml b/software/tutorial/marshal-configs/resnet50-baremetal.yaml new file mode 100644 index 00000000..f4b00630 --- /dev/null +++ b/software/tutorial/marshal-configs/resnet50-baremetal.yaml @@ -0,0 +1,8 @@ +{ + "name" : "resnet50-baremetal", + "base" : "bare-base.json", + "workdir" : "..", + "host-init" : "build.sh", + "bin" : "overlay/root/resnet50-baremetal", + "spike-args" : "--extension=gemmini" +} diff --git a/software/tutorial/marshal-configs/resnet50-linux-interactive.yaml b/software/tutorial/marshal-configs/resnet50-linux-interactive.yaml new file mode 100644 index 00000000..4dff0843 --- /dev/null +++ b/software/tutorial/marshal-configs/resnet50-linux-interactive.yaml @@ -0,0 +1,8 @@ +{ + "name" : "resnet50-linux-interactive", + "base" : "br-base.json", + "workdir" : "..", + "host-init" : "build.sh", + "overlay" : "overlay", + "spike-args" : "--extension=gemmini" +} diff --git a/software/tutorial/marshal-configs/resnet50-linux.yaml b/software/tutorial/marshal-configs/resnet50-linux.yaml new file mode 100644 index 00000000..372e1e2b --- /dev/null +++ b/software/tutorial/marshal-configs/resnet50-linux.yaml @@ -0,0 +1,9 @@ +{ + "name" : "resnet50-linux", + "base" : "br-base.json", + "workdir" : "..", + "host-init" : "build.sh", + "overlay" : "overlay", + "command" : "/root/resnet50-linux", + "spike-args" : "--extension=gemmini" +} diff --git a/tests/Makefile b/tests/Makefile index 54959bf0..28976a6a 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -1,23 +1,46 @@ -GCC=riscv64-unknown-elf-gcc -OBJDUMP=riscv64-unknown-elf-objdump -CFLAGS= -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall -LDFLAGS= -static +################################# +# RISCV Toolchain +################################# + +PREFIX = riscv64-unknown-elf- + +GCC = $(PREFIX)gcc +CXX = $(PREFIX)g++ +CP = $(PREFIX)objcopy +OBJDUMP = $(PREFIX)objdump +DG = $(PREFIX)gdb +SIZE = $(PREFIX)size + + +################################# +# Flags +################################# + +# SoC Settings +ARCH = rv64imafdc +ABI = lp64d +ARCHFLAGS = -march=$(ARCH) -mabi=$(ABI) + +CFLAGS = -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall +CFLAGS += $(ARCHFLAGS) +LDFLAGS = -static include libgloss.mk PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd \ - streaming-passthrough streaming-fir nvdla spiflashread spiflashwrite fft gcd + streaming-passthrough streaming-fir nvdla spiflashread spiflashwrite fft gcd \ + hello mt-hello -spiflash.img: spiflash.py - python3 $< .DEFAULT_GOAL := default -.PHONY: default -default: $(addsuffix .riscv,$(PROGRAMS)) spiflash.img -.PHONY: dumps -dumps: $(addsuffix .dump,$(PROGRAMS)) +################################# +# Build +################################# + +spiflash.img: spiflash.py + python3 $< %.o: %.S $(GCC) $(CFLAGS) -D__ASSEMBLY__=1 -c $< -o $@ @@ -32,7 +55,17 @@ dumps: $(addsuffix .dump,$(PROGRAMS)) $(OBJDUMP) -D $< > $@ +################################# +# Recipes +################################# + .PHONY: clean clean: rm -f *.riscv *.o *.dump $(if $(libgloss),rm -rf $(libgloss_builddir)/) + +.PHONY: default +default: $(addsuffix .riscv, $(PROGRAMS)) spiflash.img + +.PHONY: dumps +dumps: $(addsuffix .dump, $(PROGRAMS)) diff --git a/tests/hello.c b/tests/hello.c new file mode 100644 index 00000000..626cd930 --- /dev/null +++ b/tests/hello.c @@ -0,0 +1,10 @@ +#include +#include +#include "marchid.h" + +int main(void) { + uint64_t marchid = read_csr(marchid); + const char* march = get_march(marchid); + printf("Hello world from core 0, a %s\n", march); + return 0; +} diff --git a/tests/marchid.h b/tests/marchid.h new file mode 100644 index 00000000..5dfb2a3c --- /dev/null +++ b/tests/marchid.h @@ -0,0 +1,17 @@ +#ifndef MARCHID_H +#define MARCHID_H + +const char* get_march(size_t marchid) { + switch (marchid) { + case 1: + return "rocket"; + case 2: + return "sonicboom"; + case 5: + return "spike"; + default: + return "unknown"; + } +} + +#endif diff --git a/tests/mt-hello.c b/tests/mt-hello.c new file mode 100644 index 00000000..f0f521c7 --- /dev/null +++ b/tests/mt-hello.c @@ -0,0 +1,48 @@ +#include +#include +#include "marchid.h" + +// EDIT THIS +static size_t n_cores = 4; + +static void __attribute__((noinline)) barrier() +{ + static volatile int sense; + static volatile int count; + static __thread int threadsense; + + __sync_synchronize(); + + threadsense = !threadsense; + if (__sync_fetch_and_add(&count, 1) == n_cores-1) + { + count = 0; + sense = threadsense; + } + else while(sense != threadsense) + ; + + __sync_synchronize(); +} + +void __main(void) { + size_t mhartid = read_csr(mhartid); + + if (mhartid >= n_cores) while (1); + + const char* march = get_march(read_csr(marchid)); + for (size_t i = 0; i < n_cores; i++) { + if (mhartid == i) { + printf("Hello world from core %lu, a %s\n", mhartid, march); + } + barrier(); + } + + // Spin if not core 0 + if (mhartid > 0) while (1); +} + +int main(void) { + __main(); + return 0; +} diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index 34bebfe3..fcbdbe79 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 34bebfe31183289b5428b9a363a4596750030d3f +Subproject commit fcbdbe7946079650d0e656fa3d353e3f652d471f diff --git a/tools/DRAMSim2 b/tools/DRAMSim2 index 49ec2f32..44322e2f 160000 --- a/tools/DRAMSim2 +++ b/tools/DRAMSim2 @@ -1 +1 @@ -Subproject commit 49ec2f32eea6687a36acdb8d1d636d992d9e8daa +Subproject commit 44322e2f935d7dac83b7adf8dd270b41a54c6acb diff --git a/tools/api-config-chipsalliance b/tools/api-config-chipsalliance deleted file mode 160000 index fd8df110..00000000 --- a/tools/api-config-chipsalliance +++ /dev/null @@ -1 +0,0 @@ -Subproject commit fd8df1105a92065425cd353b6855777e35bd79b4 diff --git a/tools/cde b/tools/cde new file mode 160000 index 00000000..384c06b8 --- /dev/null +++ b/tools/cde @@ -0,0 +1 @@ +Subproject commit 384c06b8d45c8184ca2f3fba2f8e78f79d2c1b51 diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils index 46d6ed77..dcd9eb21 160000 --- a/tools/rocket-dsp-utils +++ b/tools/rocket-dsp-utils @@ -1 +1 @@ -Subproject commit 46d6ed77981ef18789636426cc23f0bd7edc64d9 +Subproject commit dcd9eb212aefd8040cdf9c50adffbbf975422a1d diff --git a/variables.mk b/variables.mk index 8e171712..1862ecb6 100644 --- a/variables.mk +++ b/variables.mk @@ -25,6 +25,8 @@ HELP_PROJECT_VARIABLES = \ HELP_SIMULATION_VARIABLES = \ " BINARY = riscv elf binary that the simulator will run when using the run-binary* targets" \ +" LOADMEM = riscv elf binary that should be loaded directly into simulated DRAM. LOADMEM=1 will load the BINARY elf" \ +" LOADARCH = path to a architectural checkpoint directory that should end in .loadarch/, for restoring from a checkpoint" \ " VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" \ " timeout_cycles = number of clock cycles before simulator times out, defaults to 10000000" \ " bmark_timeout_cycles = number of clock cycles before benchmark simulator times out, defaults to 100000000" @@ -68,7 +70,7 @@ ifeq ($(SUB_PROJECT),chipyard) SBT_PROJECT ?= chipyard MODEL ?= TestHarness VLOG_MODEL ?= $(MODEL) - MODEL_PACKAGE ?= $(SBT_PROJECT) + MODEL_PACKAGE ?= chipyard.harness CONFIG ?= RocketConfig CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT) @@ -169,6 +171,7 @@ SFC_ANNO_FILE ?= $(build_dir)/$(long_name).sfc.anno.json # firtool compiler outputs MFC_TOP_HRCHY_JSON ?= $(build_dir)/top_module_hierarchy.json MFC_MODEL_HRCHY_JSON ?= $(build_dir)/model_module_hierarchy.json +MFC_MODEL_HRCHY_JSON_UNIQUIFIED ?= $(build_dir)/model_module_hierarchy.uniquified.json MFC_SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf # hardcoded firtool outputs MFC_FILELIST = $(GEN_COLLATERAL_DIR)/filelist.f @@ -192,10 +195,6 @@ MODEL_MODS_FILELIST ?= $(build_dir)/$(long_name).model.f # list of all blackbox files (may be included in the top/model.f files) # this has the build_dir appended BB_MODS_FILELIST ?= $(build_dir)/$(long_name).bb.f -# top blackbox module files to include -TOP_BB_MODS_FILELIST ?= $(build_dir)/$(long_name).top.bb.f -# model blackbox module files to include (not including top blackbox modules) -MODEL_BB_MODS_FILELIST ?= $(build_dir)/$(long_name).model.bb.f # all module files to include (top, model, bb included) ALL_MODS_FILELIST ?= $(build_dir)/$(long_name).all.f @@ -250,15 +249,28 @@ output_dir=$(sim_dir)/output/$(long_name) PERMISSIVE_ON=+permissive PERMISSIVE_OFF=+permissive-off BINARY ?= -LOADMEM ?= -LOADMEM_ADDR ?= 81000000 override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles) -ifneq ($(LOADMEM),) -override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) -endif VERBOSE_FLAGS ?= +verbose -sim_out_name = $(output_dir)/$(subst $() $(),_,$(notdir $(basename $(BINARY)))) -binary_hex= $(sim_out_name).loadmem_hex +OUT_NAME ?= $(subst $() $(),_,$(notdir $(basename $(BINARY)))) +LOADMEM ?= +LOADARCH ?= + +ifneq ($(LOADARCH),) +override BINARY = $(LOADARCH)/mem.elf +override OUT_NAME = $(shell basename $(LOADARCH)) +override LOADMEM = 1 +override SIM_FLAGS += +loadarch=$(LOADARCH)/loadarch +endif + +ifeq ($(LOADMEM),1) +# If LOADMEM=1, assume BINARY is the loadmem elf +override SIM_FLAGS += +loadmem=$(BINARY) +else ifneq ($(LOADMEM),) +# Otherwise, assume the variable points to an elf file +override SIM_FLAGS += +loadmem=$(LOADMEM) +endif + +sim_out_name = $(output_dir)/$(OUT_NAME) ######################################################################################### # build output directory for compilation diff --git a/vlsi/Makefile b/vlsi/Makefile index 8259e7a6..8ca74d31 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -72,7 +72,7 @@ VLSI_RTL = $(build_dir)/syn.f ifneq ($(CUSTOM_VLOG), ) RTL_DEPS = $(CUSTOM_VLOG) else - RTL_DEPS = $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) $(TOP_SMEMS_FILE) + RTL_DEPS = $(TOP_MODS_FILELIST) $(TOP_SMEMS_FILE) endif $(VLSI_RTL): $(RTL_DEPS) @@ -80,7 +80,7 @@ ifneq ($(CUSTOM_VLOG), ) > $(VLSI_RTL) $(foreach file,$^,echo $(file) >> $(VLSI_RTL)) else - cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) | sort -u > $(VLSI_RTL) + cat $(TOP_MODS_FILELIST) | sort -u > $(VLSI_RTL) echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL) endif @@ -134,7 +134,7 @@ $(SYN_CONF): $(VLSI_RTL) ######################################################################################### # simulation and power input configuration ######################################################################################### -include $(base_dir)/vcs.mk +include $(base_dir)/sims/vcs/vcs.mk SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v diff --git a/vlsi/sim.mk b/vlsi/sim.mk index 1f5b530d..291c93ad 100644 --- a/vlsi/sim.mk +++ b/vlsi/sim.mk @@ -10,7 +10,7 @@ $(SIM_CONF): $(sim_common_files) echo " top_module: $(VLSI_TOP)" >> $@ echo " tb_name: ''" >> $@ # don't specify -top echo " input_files:" >> $@ - for x in $$(comm -23 <(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) <(sort $(VLSI_RTL))) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \ + for x in $$(cat $(MODEL_MODS_FILELIST) | sort -u) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \ echo ' - "'$$x'"' >> $@; \ done echo " input_files_meta: 'append'" >> $@