Move example/utilities to generator directory

generators/utilities/src/main/resources/bootrom

@@ -0,0 +1 @@
+../../../../generators/rocket-chip/bootrom/

generators/utilities/src/main/resources/csrc/emulator.cc

@@ -0,0 +1,356 @@
+// See LICENSE.SiFive for license details.
+// See LICENSE.Berkeley for license details.
+
+#include "verilated.h"
+#if VM_TRACE
+#include <memory>
+#include "verilated_vcd_c.h"
+#endif
+#include <fesvr/dtm.h>
+#include <fesvr/tsi.h>
+#include "remote_bitbang.h"
+#include <iostream>
+#include <fcntl.h>
+#include <signal.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <getopt.h>
+
+// For option parsing, which is split across this file, Verilog, and
+// FESVR's HTIF, a few external files must be pulled in. The list of
+// files and what they provide is enumerated:
+//
+// $RISCV/include/fesvr/htif.h:
+//   defines:
+//     - HTIF_USAGE_OPTIONS
+//     - HTIF_LONG_OPTIONS_OPTIND
+//     - HTIF_LONG_OPTIONS
+// $(ROCKETCHIP_DIR)/generated-src(-debug)?/$(CONFIG).plusArgs:
+//   defines:
+//     - PLUSARG_USAGE_OPTIONS
+//   variables:
+//     - static const char * verilog_plusargs
+
+extern tsi_t* tsi;
+extern dtm_t* dtm;
+extern remote_bitbang_t * jtag;
+
+static uint64_t trace_count = 0;
+bool verbose;
+bool done_reset;
+
+void handle_sigterm(int sig)
+{
+  dtm->stop();
+}
+
+double sc_time_stamp()
+{
+  return trace_count;
+}
+
+extern "C" int vpi_get_vlog_info(void* arg)
+{
+  return 0;
+}
+
+static void usage(const char * program_name)
+{
+  printf("Usage: %s [EMULATOR OPTION]... [VERILOG PLUSARG]... [HOST OPTION]... BINARY [TARGET OPTION]...\n",
+         program_name);
+  fputs("\
+Run a BINARY on the Rocket Chip emulator.\n\
+\n\
+Mandatory arguments to long options are mandatory for short options too.\n\
+\n\
+EMULATOR OPTIONS\n\
+  -c, --cycle-count        Print the cycle count before exiting\n\
+       +cycle-count\n\
+  -h, --help               Display this help and exit\n\
+  -m, --max-cycles=CYCLES  Kill the emulation after CYCLES\n\
+       +max-cycles=CYCLES\n\
+  -s, --seed=SEED          Use random number seed SEED\n\
+  -r, --rbb-port=PORT      Use PORT for remote bit bang (with OpenOCD and GDB) \n\
+                           If not specified, a random port will be chosen\n\
+                           automatically.\n\
+  -V, --verbose            Enable all Chisel printfs (cycle-by-cycle info)\n\
+       +verbose\n\
+", stdout);
+#if VM_TRACE == 0
+  fputs("\
+\n\
+EMULATOR DEBUG OPTIONS (only supported in debug build -- try `make debug`)\n",
+        stdout);
+#endif
+  fputs("\
+  -v, --vcd=FILE,          Write vcd trace to FILE (or '-' for stdout)\n\
+  -x, --dump-start=CYCLE   Start VCD tracing at CYCLE\n\
+       +dump-start\n\
+", stdout);
+  fputs("\n" PLUSARG_USAGE_OPTIONS, stdout);
+  fputs("\n" HTIF_USAGE_OPTIONS, stdout);
+  printf("\n"
+"EXAMPLES\n"
+"  - run a bare metal test:\n"
+"    %s $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add\n"
+"  - run a bare metal test showing cycle-by-cycle information:\n"
+"    %s +verbose $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add 2>&1 | spike-dasm\n"
+#if VM_TRACE
+"  - run a bare metal test to generate a VCD waveform:\n"
+"    %s -v rv64ui-p-add.vcd $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add\n"
+#endif
+"  - run an ELF (you wrote, called 'hello') using the proxy kernel:\n"
+"    %s pk hello\n",
+         program_name, program_name, program_name
+#if VM_TRACE
+         , program_name
+#endif
+         );
+}
+
+int main(int argc, char** argv)
+{
+  unsigned random_seed = (unsigned)time(NULL) ^ (unsigned)getpid();
+  uint64_t max_cycles = -1;
+  int ret = 0;
+  bool print_cycles = false;
+  // Port numbers are 16 bit unsigned integers. 
+  uint16_t rbb_port = 0;
+#if VM_TRACE
+  FILE * vcdfile = NULL;
+  uint64_t start = 0;
+#endif
+  char ** htif_argv = NULL;
+  int verilog_plusargs_legal = 1;
+
+  while (1) {
+    static struct option long_options[] = {
+      {"cycle-count", no_argument,       0, 'c' },
+      {"help",        no_argument,       0, 'h' },
+      {"max-cycles",  required_argument, 0, 'm' },
+      {"seed",        required_argument, 0, 's' },
+      {"rbb-port",    required_argument, 0, 'r' },
+      {"verbose",     no_argument,       0, 'V' },
+#if VM_TRACE
+      {"vcd",         required_argument, 0, 'v' },
+      {"dump-start",  required_argument, 0, 'x' },
+#endif
+      HTIF_LONG_OPTIONS
+    };
+    int option_index = 0;
+#if VM_TRACE
+    int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:", long_options, &option_index);
+#else
+    int c = getopt_long(argc, argv, "-chm:s:r:V", long_options, &option_index);
+#endif
+    if (c == -1) break;
+ retry:
+    switch (c) {
+      // Process long and short EMULATOR options
+      case '?': usage(argv[0]);             return 1;
+      case 'c': print_cycles = true;        break;
+      case 'h': usage(argv[0]);             return 0;
+      case 'm': max_cycles = atoll(optarg); break;
+      case 's': random_seed = atoi(optarg); break;
+      case 'r': rbb_port = atoi(optarg);    break;
+      case 'V': verbose = true;             break;
+#if VM_TRACE
+      case 'v': {
+        vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w");
+        if (!vcdfile) {
+          std::cerr << "Unable to open " << optarg << " for VCD write\n";
+          return 1;
+        }
+        break;
+      }
+      case 'x': start = atoll(optarg);      break;
+#endif
+      // Process legacy '+' EMULATOR arguments by replacing them with
+      // their getopt equivalents
+      case 1: {
+        std::string arg = optarg;
+        if (arg.substr(0, 1) != "+") {
+          optind--;
+          goto done_processing;
+        }
+        if (arg == "+verbose")
+          c = 'V';
+        else if (arg.substr(0, 12) == "+max-cycles=") {
+          c = 'm';
+          optarg = optarg+12;
+        }
+#if VM_TRACE
+        else if (arg.substr(0, 12) == "+dump-start=") {
+          c = 'x';
+          optarg = optarg+12;
+        }
+#endif
+        else if (arg.substr(0, 12) == "+cycle-count")
+          c = 'c';
+        // If we don't find a legacy '+' EMULATOR argument, it still could be
+        // a VERILOG_PLUSARG and not an error.
+        else if (verilog_plusargs_legal) {
+          const char ** plusarg = &verilog_plusargs[0];
+          int legal_verilog_plusarg = 0;
+          while (*plusarg && (legal_verilog_plusarg == 0)){
+            if (arg.substr(1, strlen(*plusarg)) == *plusarg) {
+              legal_verilog_plusarg = 1;
+            }
+            plusarg ++;
+          }
+          if (!legal_verilog_plusarg) {
+            verilog_plusargs_legal = 0;
+          } else {
+            c = 'P';
+          }
+          goto retry;
+        }
+        // If we STILL don't find a legacy '+' argument, it still could be
+        // an HTIF (HOST) argument and not an error. If this is the case, then
+        // we're done processing EMULATOR and VERILOG arguments.
+        else {
+          static struct option htif_long_options [] = { HTIF_LONG_OPTIONS };
+          struct option * htif_option = &htif_long_options[0];
+          while (htif_option->name) {
+            if (arg.substr(1, strlen(htif_option->name)) == htif_option->name) {
+              optind--;
+              goto done_processing;
+            }
+            htif_option++;
+          }
+          std::cerr << argv[0] << ": invalid plus-arg (Verilog or HTIF) \""
+                    << arg << "\"\n";
+          c = '?';
+        }
+        goto retry;
+      }
+      case 'P': break; // Nothing to do here, Verilog PlusArg
+      // Realize that we've hit HTIF (HOST) arguments or error out
+      default:
+        if (c >= HTIF_LONG_OPTIONS_OPTIND) {
+          optind--;
+          goto done_processing;
+        }
+        c = '?';
+        goto retry;
+    }
+  }
+
+done_processing:
+  if (optind == argc) {
+    std::cerr << "No binary specified for emulator\n";
+    usage(argv[0]);
+    return 1;
+  }
+  int htif_argc = 1 + argc - optind;
+  htif_argv = (char **) malloc((htif_argc) * sizeof (char *));
+  htif_argv[0] = argv[0];
+  for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++];
+
+  if (verbose)
+    fprintf(stderr, "using random seed %u\n", random_seed);
+
+  srand(random_seed);
+  srand48(random_seed);
+
+  Verilated::randReset(2);
+  Verilated::commandArgs(argc, argv);
+  TEST_HARNESS *tile = new TEST_HARNESS;
+
+#if VM_TRACE
+  Verilated::traceEverOn(true); // Verilator must compute traced signals
+  std::unique_ptr<VerilatedVcdFILE> vcdfd(new VerilatedVcdFILE(vcdfile));
+  std::unique_ptr<VerilatedVcdC> tfp(new VerilatedVcdC(vcdfd.get()));
+  if (vcdfile) {
+    tile->trace(tfp.get(), 99);  // Trace 99 levels of hierarchy
+    tfp->open("");
+  }
+#endif
+
+  jtag = new remote_bitbang_t(rbb_port);
+  dtm = new dtm_t(htif_argc, htif_argv);
+  tsi = new tsi_t(htif_argc, htif_argv);
+
+  signal(SIGTERM, handle_sigterm);
+
+  bool dump;
+  // reset for several cycles to handle pipelined reset
+  for (int i = 0; i < 10; i++) {
+    tile->reset = 1;
+    tile->clock = 0;
+    tile->eval();
+#if VM_TRACE
+    dump = tfp && trace_count >= start;
+    if (dump)
+      tfp->dump(static_cast<vluint64_t>(trace_count * 2));
+#endif
+    tile->clock = 1;
+    tile->eval();
+#if VM_TRACE
+    if (dump)
+      tfp->dump(static_cast<vluint64_t>(trace_count * 2 + 1));
+#endif
+    trace_count ++;
+  }
+  tile->reset = 0;
+  done_reset = true;
+
+  while (!dtm->done() && !jtag->done() && !tsi->done() &&
+         !tile->io_success && trace_count < max_cycles) {
+    tile->clock = 0;
+    tile->eval();
+#if VM_TRACE
+    dump = tfp && trace_count >= start;
+    if (dump)
+      tfp->dump(static_cast<vluint64_t>(trace_count * 2));
+#endif
+
+    tile->clock = 1;
+    tile->eval();
+#if VM_TRACE
+    if (dump)
+      tfp->dump(static_cast<vluint64_t>(trace_count * 2 + 1));
+#endif
+    trace_count++;
+  }
+
+#if VM_TRACE
+  if (tfp)
+    tfp->close();
+  if (vcdfile)
+    fclose(vcdfile);
+#endif
+
+  if (dtm->exit_code())
+  {
+    fprintf(stderr, "*** FAILED *** via dtm (code = %d, seed %d) after %ld cycles\n", dtm->exit_code(), random_seed, trace_count);
+    ret = dtm->exit_code();
+  }
+  else if (tsi->exit_code())
+  {
+    fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %ld cycles\n", tsi->exit_code(), random_seed, trace_count);
+    ret = tsi->exit_code();
+  }
+  else if (jtag->exit_code())
+  {
+    fprintf(stderr, "*** FAILED *** via jtag (code = %d, seed %d) after %ld cycles\n", jtag->exit_code(), random_seed, trace_count);
+    ret = jtag->exit_code();
+  }
+  else if (trace_count == max_cycles)
+  {
+    fprintf(stderr, "*** FAILED *** via trace_count (timeout, seed %d) after %ld cycles\n", random_seed, trace_count);
+    ret = 2;
+  }
+  else if (verbose || print_cycles)
+  {
+    fprintf(stderr, "*** PASSED *** Completed after %ld cycles\n", trace_count);
+  }
+
+  if (dtm) delete dtm;
+  if (tsi) delete tsi;
+  if (jtag) delete jtag;
+  if (tile) delete tile;
+  if (htif_argv) free(htif_argv);
+  return ret;
+}

generators/utilities/src/main/scala/Simulator.scala

@@ -0,0 +1,119 @@
+package utilities
+
+import java.io.File
+
+case class GenerateSimConfig(
+  targetDir: String = ".",
+  dotFName: String = "sim_files.f",
+  simulator: Simulator = VerilatorSimulator,
+)
+
+sealed trait Simulator
+object VerilatorSimulator extends Simulator
+object VCSSimulator extends Simulator
+
+trait HasGenerateSimConfig {
+  val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") {
+    head("GenerateSimFiles", "0.1")
+
+    opt[String]("simulator")
+      .abbr("sim")
+      .valueName("<simulator-name>")
+      .action((x, c) => x match {
+        case "verilator" => c.copy(simulator = VerilatorSimulator)
+        case "vcs" => c.copy(simulator = VCSSimulator)
+        case _ => throw new Exception(s"Unrecognized simulator $x")
+      })
+      .text("Name of simulator to generate files for (verilator, vcs)")
+
+    opt[String]("target-dir")
+      .abbr("td")
+      .valueName("<target-directory>")
+      .action((x, c) => c.copy(targetDir = x))
+      .text("Target director to put files")
+
+    opt[String]("dotFName")
+      .abbr("df")
+      .valueName("<dot-f filename>")
+      .action((x, c) => c.copy(dotFName = x))
+      .text("Name of generated dot-f file")
+  }
+}
+
+object GenerateSimFiles extends App with HasGenerateSimConfig {
+  def addOption(file: File, cfg: GenerateSimConfig): String = {
+    val fname = file.getCanonicalPath
+    // deal with header files
+    if (fname.takeRight(2) == ".h") {
+      cfg.simulator match {
+        // verilator needs to explicitly include verilator.h, so use the -FI option
+        case VerilatorSimulator => s"-FI ${fname}"
+        // vcs pulls headers in with +incdir, doesn't have anything like verilator.h
+        case VCSSimulator => ""
+      }
+    } else { // do nothing otherwise
+      fname
+    }
+  }
+  def writeDotF(lines: Seq[String], cfg: GenerateSimConfig): Unit = {
+    writeTextToFile(lines.mkString("\n"), new File(cfg.targetDir, cfg.dotFName))
+  }
+  // From FIRRTL
+  def safeFile[A](fileName: String)(code: => A) = try { code } catch {
+    case e@ (_: java.io.FileNotFoundException | _: NullPointerException) => throw new Exception(fileName, e)
+    case t: Throwable                                            => throw t
+  }
+  // From FIRRTL
+  def writeResource(name: String, targetDir: String): File = {
+    val in = getClass.getResourceAsStream(name)
+    val p = java.nio.file.Paths.get(name)
+    val fname = p.getFileName().toString();
+
+    val f = new File(targetDir, fname)
+    val out = new java.io.FileOutputStream(f)
+    safeFile(name)(Iterator.continually(in.read).takeWhile(-1 != _).foreach(out.write))
+    out.close()
+    f
+  }
+  // From FIRRTL
+  def writeTextToFile(text: String, file: File) {
+    val out = new java.io.PrintWriter(file)
+    out.write(text)
+    out.close()
+  }
+  def resources(sim: Simulator): Seq[String] = Seq(
+    "/testchipip/csrc/SimSerial.cc",
+    "/csrc/SimDTM.cc",
+    "/csrc/SimJTAG.cc",
+    "/csrc/remote_bitbang.h",
+    "/csrc/remote_bitbang.cc",
+    "/vsrc/EICG_wrapper.v",
+  ) ++ (sim match { // simulator specific files to include
+    case VerilatorSimulator => Seq(
+      "/project-template/csrc/emulator.cc",
+      "/csrc/verilator.h",
+    )
+    case VCSSimulator => Seq(
+      "/vsrc/TestDriver.v",
+    )
+  })
+
+  def writeBootrom(): Unit = {
+    firrtl.FileUtils.makeDirectory("./bootrom/")
+    writeResource("/testchipip/bootrom/bootrom.rv64.img", "./bootrom/")
+    writeResource("/testchipip/bootrom/bootrom.rv32.img", "./bootrom/")
+    writeResource("/bootrom/bootrom.img", "./bootrom/")
+  }
+
+  def writeFiles(cfg: GenerateSimConfig): Unit = {
+    writeBootrom()
+    firrtl.FileUtils.makeDirectory(cfg.targetDir)
+    val files = resources(cfg.simulator).map { writeResource(_, cfg.targetDir) }
+    writeDotF(files.map(addOption(_, cfg)), cfg)
+  }
+
+  parser.parse(args, GenerateSimConfig()) match {
+    case Some(cfg) => writeFiles(cfg)
+    case _ => // error message already shown
+  }
+}