Move example/utilities to generator directory
This commit is contained in:
Jerry Zhao
170
generators/example/src/main/scala/ConfigMixins.scala
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170
generators/example/src/main/scala/ConfigMixins.scala
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package example
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import chisel3._
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import freechips.rocketchip.config.{Parameters, Config}
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import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
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import freechips.rocketchip.diplomacy.{LazyModule, ValName}
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import freechips.rocketchip.devices.tilelink.BootROMParams
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import freechips.rocketchip.tile.XLen
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import testchipip._
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import sifive.blocks.devices.gpio._
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/**
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* TODO: Why do we need this?
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*/
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object ConfigValName {
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implicit val valName = ValName("TestHarness")
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}
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import ConfigValName._
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// -----------------------
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// Common Parameter Mixins
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// -----------------------
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/**
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* Class to specify where the BootRom file is (from `rebar` top)
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*/
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class WithBootROM extends Config((site, here, up) => {
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case BootROMParams => BootROMParams(
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contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
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})
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/**
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* Class to add in GPIO
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*/
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class WithGPIO extends Config((site, here, up) => {
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case PeripheryGPIOKey => List(
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GPIOParams(address = 0x10012000, width = 4, includeIOF = false))
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})
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// ----------------------------------------
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// Rocket Top Level System Parameter Mixins
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// ----------------------------------------
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/**
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* Class to specify a "plain" top level rocket-chip system
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*/
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class WithNormalRocketTop extends Config((site, here, up) => {
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case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
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Module(LazyModule(new RocketTop()(p)).module)
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}
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})
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/**
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* Class to specify a top level rocket-chip system with PWM
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*/
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class WithPWMRocketTop extends Config((site, here, up) => {
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case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) =>
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Module(LazyModule(new RocketTopWithPWMTL()(p)).module)
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})
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/**
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* Class to specify a top level rocket-chip system with a PWM AXI4
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*/
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class WithPWMAXI4RocketTop extends Config((site, here, up) => {
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case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) =>
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Module(LazyModule(new RocketTopWithPWMAXI4()(p)).module)
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})
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/**
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* Class to specify a top level rocket-chip system with a block device
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*/
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class WithBlockDeviceModelRocketTop extends Config((site, here, up) => {
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case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
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val top = Module(LazyModule(new RocketTopWithBlockDevice()(p)).module)
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top.connectBlockDeviceModel()
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top
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}
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})
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/**
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* Class to specify a top level rocket-chip system with a simulator block device
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*/
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class WithSimBlockDeviceRocketTop extends Config((site, here, up) => {
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case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
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val top = Module(LazyModule(new RocketTopWithBlockDevice()(p)).module)
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top.connectSimBlockDevice(clock, reset)
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top
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}
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})
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/**
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* Class to specify a top level rocket-chip system with GPIO
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*/
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class WithGPIORocketTop extends Config((site, here, up) => {
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case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
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val top = Module(LazyModule(new RocketTopWithGPIO()(p)).module)
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for (gpio <- top.gpio) {
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for (pin <- gpio.pins) {
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pin.i.ival := false.B
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}
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}
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top
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}
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})
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// --------------------------------------
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// BOOM Top Level System Parameter Mixins
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// --------------------------------------
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/**
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* Class to specify a "plain" top level BOOM system
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*/
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class WithNormalBoomTop extends Config((site, here, up) => {
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case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => {
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Module(LazyModule(new BoomTop()(p)).module)
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}
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})
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/**
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* Class to specify a top level BOOM system with PWM
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*/
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class WithPWMBoomTop extends Config((site, here, up) => {
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case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) =>
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Module(LazyModule(new BoomTopWithPWMTL()(p)).module)
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})
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/**
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* Class to specify a top level BOOM system with a PWM AXI4
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*/
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class WithPWMAXI4BoomTop extends Config((site, here, up) => {
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case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) =>
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Module(LazyModule(new BoomTopWithPWMAXI4()(p)).module)
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})
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/**
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* Class to specify a top level BOOM system with a block device
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*/
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class WithBlockDeviceModelBoomTop extends Config((site, here, up) => {
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case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => {
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val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module)
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top.connectBlockDeviceModel()
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top
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}
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})
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/**
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* Class to specify a top level BOOM system with a simulator block device
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*/
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class WithSimBlockDeviceBoomTop extends Config((site, here, up) => {
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case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => {
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val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module)
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top.connectSimBlockDevice(clock, reset)
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top
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}
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})
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/**
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* Class to specify a top level BOOM system with GPIO
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*/
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class WithGPIOBoomTop extends Config((site, here, up) => {
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case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => {
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val top = Module(LazyModule(new BoomTopWithGPIO()(p)).module)
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for (gpio <- top.gpio) {
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for (pin <- gpio.pins) {
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pin.i.ival := false.B
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}
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}
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top
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}
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})
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113
generators/example/src/main/scala/Configs.scala
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113
generators/example/src/main/scala/Configs.scala
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@@ -0,0 +1,113 @@
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package example
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import chisel3._
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import freechips.rocketchip.config.{Config}
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import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize}
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import testchipip._
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// --------------
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// Rocket Configs
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// --------------
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class BaseRocketConfig extends Config(
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new WithBootROM ++
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new freechips.rocketchip.system.DefaultConfig)
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class DefaultRocketConfig extends Config(
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new WithNormalRocketTop ++
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new BaseRocketConfig)
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class HwachaConfig extends Config(
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new hwacha.DefaultHwachaConfig ++
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new DefaultRocketConfig)
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class RoccRocketConfig extends Config(
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new WithRoccExample ++
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new DefaultRocketConfig)
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class PWMRocketConfig extends Config(
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new WithPWMRocketTop ++
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new BaseRocketConfig)
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class PWMAXI4RocketConfig extends Config(
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new WithPWMAXI4RocketTop ++
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new BaseRocketConfig)
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class SimBlockDeviceRocketConfig extends Config(
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new WithBlockDevice ++
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new WithSimBlockDeviceRocketTop ++
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new BaseRocketConfig)
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class BlockDeviceModelRocketConfig extends Config(
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new WithBlockDevice ++
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new WithBlockDeviceModelRocketTop ++
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new BaseRocketConfig)
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class DualCoreRocketConfig extends Config(
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new WithNBigCores(2) ++
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new DefaultRocketConfig)
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class RV32RocketConfig extends Config(
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new WithRV32 ++
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new DefaultRocketConfig)
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class GPIORocketConfig extends Config(
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new WithGPIO ++
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new WithGPIORocketTop ++
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new BaseRocketConfig)
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class GB1MemoryConfig extends Config(
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new WithExtMemSize((1<<30) * 1L) ++
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new DefaultRocketConfig)
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// ------------
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// BOOM Configs
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// ------------
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class BaseBoomConfig extends Config(
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new WithBootROM ++
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new boom.system.BoomConfig)
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class DefaultBoomConfig extends Config(
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new WithNormalBoomTop ++
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new BaseBoomConfig)
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class HwachaBoomConfig extends Config(
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new hwacha.DefaultHwachaConfig ++
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new DefaultBoomConfig)
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class RoccBoomConfig extends Config(
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new WithRoccExample ++
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new DefaultBoomConfig)
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class PWMBoomConfig extends Config(
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new WithPWMBoomTop ++
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new BaseBoomConfig)
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class PWMAXI4BoomConfig extends Config(
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new WithPWMAXI4BoomTop ++
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new BaseBoomConfig)
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class SimBlockDeviceBoomConfig extends Config(
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new WithBlockDevice ++
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new WithSimBlockDeviceBoomTop ++
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new BaseBoomConfig)
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class BlockDeviceModelBoomConfig extends Config(
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new WithBlockDevice ++
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new WithBlockDeviceModelBoomTop ++
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new BaseBoomConfig)
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class DualCoreBoomConfig extends Config(
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// Core gets tacked onto existing list
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new boom.system.WithNBoomCores(2) ++
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new DefaultBoomConfig)
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class RV32BoomConfig extends Config(
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new WithBootROM ++
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new boom.system.SmallRV32UnifiedBoomConfig)
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class GPIOBoomConfig extends Config(
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new WithGPIO ++
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new WithGPIOBoomTop ++
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new BaseBoomConfig)
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138
generators/example/src/main/scala/Generator.scala
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138
generators/example/src/main/scala/Generator.scala
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@@ -0,0 +1,138 @@
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package example
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import scala.collection.mutable.LinkedHashSet
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import chisel3._
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import chisel3.experimental._
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import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper}
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import freechips.rocketchip.subsystem.{RocketTilesKey}
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import freechips.rocketchip.diplomacy.{LazyModule}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.util.{GeneratorApp}
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import freechips.rocketchip.tile.{XLen}
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import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
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import boom.system.{BoomTilesKey, BoomTestSuites}
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object Generator extends GeneratorApp {
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val rv64RegrTestNames = LinkedHashSet(
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"rv64ud-v-fcvt",
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"rv64ud-p-fdiv",
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"rv64ud-v-fadd",
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"rv64uf-v-fadd",
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"rv64um-v-mul",
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"rv64mi-p-breakpoint",
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"rv64uc-v-rvc",
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"rv64ud-v-structural",
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"rv64si-p-wfi",
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"rv64um-v-divw",
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"rv64ua-v-lrsc",
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"rv64ui-v-fence_i",
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"rv64ud-v-fcvt_w",
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"rv64uf-v-fmin",
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"rv64ui-v-sb",
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"rv64ua-v-amomax_d",
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"rv64ud-v-move",
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"rv64ud-v-fclass",
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"rv64ua-v-amoand_d",
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"rv64ua-v-amoxor_d",
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"rv64si-p-sbreak",
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"rv64ud-v-fmadd",
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"rv64uf-v-ldst",
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"rv64um-v-mulh",
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"rv64si-p-dirty")
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val rv32RegrTestNames = LinkedHashSet(
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"rv32mi-p-ma_addr",
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"rv32mi-p-csr",
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"rv32ui-p-sh",
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"rv32ui-p-lh",
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"rv32uc-p-rvc",
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"rv32mi-p-sbreak",
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"rv32ui-p-sll")
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override def addTestSuites {
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import freechips.rocketchip.system.DefaultTestSuites._
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val xlen = params(XLen)
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// TODO: for now only generate tests for the first rocket/boom tile in the subsystem
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// TODO: support heterogenous systems?
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// rocket specific tests
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params(RocketTilesKey).headOption.map { tileParams =>
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val coreParams = tileParams.core
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val vm = coreParams.useVM
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val env = if (vm) List("p","v") else List("p")
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coreParams.fpu foreach { case cfg =>
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if (xlen == 32) {
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TestGeneration.addSuites(env.map(rv32uf))
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if (cfg.fLen >= 64)
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TestGeneration.addSuites(env.map(rv32ud))
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} else {
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TestGeneration.addSuite(rv32udBenchmarks)
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TestGeneration.addSuites(env.map(rv64uf))
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if (cfg.fLen >= 64)
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TestGeneration.addSuites(env.map(rv64ud))
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}
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}
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if (coreParams.useAtomics) {
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if (tileParams.dcache.flatMap(_.scratch).isEmpty)
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TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
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else
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TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
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}
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if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
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val (rvi, rvu) =
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if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
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else ((if (vm) rv32i else rv32pi), rv32u)
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TestGeneration.addSuites(rvi.map(_("p")))
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TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
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TestGeneration.addSuite(benchmarks)
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TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
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}
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// boom specific tests
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params(BoomTilesKey).headOption.map { tileParams =>
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val coreParams = tileParams.core
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val vm = coreParams.useVM
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val env = if (vm) List("p","v") else List("p")
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coreParams.fpu foreach { case cfg =>
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if (xlen == 32) {
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TestGeneration.addSuites(env.map(rv32uf))
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if (cfg.fLen >= 64) {
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TestGeneration.addSuites(env.map(rv32ud))
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}
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} else if (cfg.fLen >= 64) {
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TestGeneration.addSuites(env.map(rv64ud))
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TestGeneration.addSuites(env.map(rv64uf))
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TestGeneration.addSuite(rv32udBenchmarks)
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}
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}
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if (coreParams.useAtomics) {
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if (tileParams.dcache.flatMap(_.scratch).isEmpty) {
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TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
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} else {
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TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
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}
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}
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if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
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// Include our BOOM-specific overrides.
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val (rvi, rvu) =
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if (xlen == 64) ((if (vm) BoomTestSuites.rv64i else BoomTestSuites.rv64pi), rv64u)
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else ((if (vm) rv32i else rv32pi), rv32u)
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TestGeneration.addSuites(rvi.map(_("p")))
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TestGeneration.addSuites(rvu.map(_("p")))
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TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
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TestGeneration.addSuite(benchmarks)
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rv64RegrTestNames -= "rv64mi-p-breakpoint" // TODO: breakpoints not implemented yet
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TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
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}
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}
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||||
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val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
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generateFirrtl
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generateAnno
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generateTestSuiteMakefrags
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generateArtefacts
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}
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126
generators/example/src/main/scala/PWM.scala
Normal file
126
generators/example/src/main/scala/PWM.scala
Normal file
@@ -0,0 +1,126 @@
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package example
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||||
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||||
import chisel3._
|
||||
import chisel3.util._
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||||
import freechips.rocketchip.amba.axi4._
|
||||
import freechips.rocketchip.subsystem.BaseSubsystem
|
||||
import freechips.rocketchip.config.{Parameters, Field}
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.regmapper.{HasRegMap, RegField}
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.util.UIntIsOneOf
|
||||
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||||
case class PWMParams(address: BigInt, beatBytes: Int)
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||||
|
||||
class PWMBase(w: Int) extends Module {
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||||
val io = IO(new Bundle {
|
||||
val pwmout = Output(Bool())
|
||||
val period = Input(UInt(w.W))
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||||
val duty = Input(UInt(w.W))
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val enable = Input(Bool())
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||||
})
|
||||
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||||
// The counter should count up until period is reached
|
||||
val counter = Reg(UInt(w.W))
|
||||
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||||
when (counter >= (io.period - 1.U)) {
|
||||
counter := 0.U
|
||||
} .otherwise {
|
||||
counter := counter + 1.U
|
||||
}
|
||||
|
||||
// If PWM is enabled, pwmout is high when counter < duty
|
||||
// If PWM is not enabled, it will always be low
|
||||
io.pwmout := io.enable && (counter < io.duty)
|
||||
}
|
||||
|
||||
trait PWMBundle extends Bundle {
|
||||
val pwmout = Output(Bool())
|
||||
}
|
||||
|
||||
trait PWMModule extends HasRegMap {
|
||||
val io: PWMBundle
|
||||
implicit val p: Parameters
|
||||
def params: PWMParams
|
||||
|
||||
// How many clock cycles in a PWM cycle?
|
||||
val period = Reg(UInt(32.W))
|
||||
// For how many cycles should the clock be high?
|
||||
val duty = Reg(UInt(32.W))
|
||||
// Is the PWM even running at all?
|
||||
val enable = RegInit(false.B)
|
||||
|
||||
val base = Module(new PWMBase(32))
|
||||
io.pwmout := base.io.pwmout
|
||||
base.io.period := period
|
||||
base.io.duty := duty
|
||||
base.io.enable := enable
|
||||
|
||||
regmap(
|
||||
0x00 -> Seq(
|
||||
RegField(32, period)),
|
||||
0x04 -> Seq(
|
||||
RegField(32, duty)),
|
||||
0x08 -> Seq(
|
||||
RegField(1, enable)))
|
||||
}
|
||||
|
||||
class PWMTL(c: PWMParams)(implicit p: Parameters)
|
||||
extends TLRegisterRouter(
|
||||
c.address, "pwm", Seq("ucbbar,pwm"),
|
||||
beatBytes = c.beatBytes)(
|
||||
new TLRegBundle(c, _) with PWMBundle)(
|
||||
new TLRegModule(c, _, _) with PWMModule)
|
||||
|
||||
class PWMAXI4(c: PWMParams)(implicit p: Parameters)
|
||||
extends AXI4RegisterRouter(c.address, beatBytes = c.beatBytes)(
|
||||
new AXI4RegBundle(c, _) with PWMBundle)(
|
||||
new AXI4RegModule(c, _, _) with PWMModule)
|
||||
|
||||
trait HasPeripheryPWMTL { this: BaseSubsystem =>
|
||||
implicit val p: Parameters
|
||||
|
||||
private val address = 0x2000
|
||||
private val portName = "pwm"
|
||||
|
||||
val pwm = LazyModule(new PWMTL(
|
||||
PWMParams(address, pbus.beatBytes))(p))
|
||||
|
||||
pbus.toVariableWidthSlave(Some(portName)) { pwm.node }
|
||||
}
|
||||
|
||||
trait HasPeripheryPWMTLModuleImp extends LazyModuleImp {
|
||||
implicit val p: Parameters
|
||||
val outer: HasPeripheryPWMTL
|
||||
|
||||
val pwmout = IO(Output(Bool()))
|
||||
|
||||
pwmout := outer.pwm.module.io.pwmout
|
||||
}
|
||||
|
||||
trait HasPeripheryPWMAXI4 { this: BaseSubsystem =>
|
||||
implicit val p: Parameters
|
||||
|
||||
private val address = 0x2000
|
||||
private val portName = "pwm"
|
||||
|
||||
val pwm = LazyModule(new PWMAXI4(
|
||||
PWMParams(address, pbus.beatBytes))(p))
|
||||
|
||||
pbus.toSlave(Some(portName)) {
|
||||
pwm.node :=
|
||||
AXI4Buffer () :=
|
||||
TLToAXI4() :=
|
||||
// toVariableWidthSlave doesn't use holdFirstDeny, which TLToAXI4() needs
|
||||
TLFragmenter(pbus.beatBytes, pbus.blockBytes, holdFirstDeny = true)
|
||||
}
|
||||
}
|
||||
|
||||
trait HasPeripheryPWMAXI4ModuleImp extends LazyModuleImp {
|
||||
implicit val p: Parameters
|
||||
val outer: HasPeripheryPWMAXI4
|
||||
|
||||
val pwmout = IO(Output(Bool()))
|
||||
|
||||
pwmout := outer.pwm.module.io.pwmout
|
||||
}
|
||||
79
generators/example/src/main/scala/TestHarness.scala
Normal file
79
generators/example/src/main/scala/TestHarness.scala
Normal file
@@ -0,0 +1,79 @@
|
||||
package example
|
||||
|
||||
import chisel3._
|
||||
import chisel3.experimental._
|
||||
import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper}
|
||||
import freechips.rocketchip.diplomacy.LazyModule
|
||||
import freechips.rocketchip.config.{Field, Parameters}
|
||||
import freechips.rocketchip.util.GeneratorApp
|
||||
|
||||
// -------------------
|
||||
// Rocket Test Harness
|
||||
// -------------------
|
||||
|
||||
case object BuildRocketTop extends Field[(Clock, Bool, Parameters) => RocketTopModule[RocketTop]]
|
||||
|
||||
class RocketTestHarness(implicit val p: Parameters) extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val success = Output(Bool())
|
||||
})
|
||||
|
||||
// force Chisel to rename module
|
||||
override def desiredName = "TestHarness"
|
||||
|
||||
val dut = p(BuildRocketTop)(clock, reset.toBool, p)
|
||||
dut.debug := DontCare
|
||||
dut.connectSimAXIMem()
|
||||
dut.connectSimAXIMMIO()
|
||||
dut.dontTouchPorts()
|
||||
dut.tieOffInterrupts()
|
||||
dut.l2_frontend_bus_axi4.foreach(axi => {
|
||||
axi.tieoff()
|
||||
experimental.DataMirror.directionOf(axi.ar.ready) match {
|
||||
case core.ActualDirection.Input =>
|
||||
axi.r.bits := DontCare
|
||||
axi.b.bits := DontCare
|
||||
case core.ActualDirection.Output =>
|
||||
axi.aw.bits := DontCare
|
||||
axi.ar.bits := DontCare
|
||||
axi.w.bits := DontCare
|
||||
}
|
||||
})
|
||||
|
||||
io.success := dut.connectSimSerial()
|
||||
}
|
||||
|
||||
// -----------------
|
||||
// BOOM Test Harness
|
||||
// -----------------
|
||||
|
||||
case object BuildBoomTop extends Field[(Clock, Bool, Parameters) => BoomTopModule[BoomTop]]
|
||||
|
||||
class BoomTestHarness(implicit val p: Parameters) extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val success = Output(Bool())
|
||||
})
|
||||
|
||||
// force Chisel to rename module
|
||||
override def desiredName = "TestHarness"
|
||||
|
||||
val dut = p(BuildBoomTop)(clock, reset.toBool, p)
|
||||
dut.debug := DontCare
|
||||
dut.connectSimAXIMem()
|
||||
dut.connectSimAXIMMIO()
|
||||
dut.dontTouchPorts()
|
||||
dut.tieOffInterrupts()
|
||||
dut.l2_frontend_bus_axi4.foreach(axi => {
|
||||
axi.tieoff()
|
||||
experimental.DataMirror.directionOf(axi.ar.ready) match {
|
||||
case core.ActualDirection.Input =>
|
||||
axi.r.bits := DontCare
|
||||
axi.b.bits := DontCare
|
||||
case core.ActualDirection.Output =>
|
||||
axi.aw.bits := DontCare
|
||||
axi.ar.bits := DontCare
|
||||
axi.w.bits := DontCare
|
||||
}
|
||||
})
|
||||
io.success := dut.connectSimSerial()
|
||||
}
|
||||
129
generators/example/src/main/scala/Top.scala
Normal file
129
generators/example/src/main/scala/Top.scala
Normal file
@@ -0,0 +1,129 @@
|
||||
package example
|
||||
|
||||
import chisel3._
|
||||
import freechips.rocketchip.subsystem._
|
||||
import freechips.rocketchip.system._
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.devices.tilelink._
|
||||
import freechips.rocketchip.util.DontTouch
|
||||
import testchipip._
|
||||
import sifive.blocks.devices.gpio._
|
||||
|
||||
// ------------------------
|
||||
// Rocket Top Level Systems
|
||||
// ------------------------
|
||||
|
||||
class RocketTop(implicit p: Parameters) extends ExampleRocketSystem
|
||||
with CanHaveMasterAXI4MemPort
|
||||
with HasPeripheryBootROM
|
||||
with HasNoDebug
|
||||
with HasPeripherySerial {
|
||||
override lazy val module = new RocketTopModule(this)
|
||||
}
|
||||
|
||||
class RocketTopModule[+L <: RocketTop](l: L) extends ExampleRocketSystemModuleImp(l)
|
||||
with HasRTCModuleImp
|
||||
with CanHaveMasterAXI4MemPortModuleImp
|
||||
with HasPeripheryBootROMModuleImp
|
||||
with HasNoDebugModuleImp
|
||||
with HasPeripherySerialModuleImp
|
||||
with DontTouch
|
||||
|
||||
//---------------------------------------------------------------------------------------------------------
|
||||
|
||||
class RocketTopWithPWMTL(implicit p: Parameters) extends RocketTop
|
||||
with HasPeripheryPWMTL {
|
||||
override lazy val module = new RocketTopWithPWMTLModule(this)
|
||||
}
|
||||
|
||||
class RocketTopWithPWMTLModule(l: RocketTopWithPWMTL)
|
||||
extends RocketTopModule(l) with HasPeripheryPWMTLModuleImp
|
||||
|
||||
//---------------------------------------------------------------------------------------------------------
|
||||
|
||||
class RocketTopWithPWMAXI4(implicit p: Parameters) extends RocketTop
|
||||
with HasPeripheryPWMAXI4 {
|
||||
override lazy val module = new RocketTopWithPWMAXI4Module(this)
|
||||
}
|
||||
|
||||
class RocketTopWithPWMAXI4Module(l: RocketTopWithPWMAXI4)
|
||||
extends RocketTopModule(l) with HasPeripheryPWMAXI4ModuleImp
|
||||
|
||||
//---------------------------------------------------------------------------------------------------------
|
||||
|
||||
class RocketTopWithBlockDevice(implicit p: Parameters) extends RocketTop
|
||||
with HasPeripheryBlockDevice {
|
||||
override lazy val module = new RocketTopWithBlockDeviceModule(this)
|
||||
}
|
||||
|
||||
class RocketTopWithBlockDeviceModule(l: RocketTopWithBlockDevice)
|
||||
extends RocketTopModule(l)
|
||||
with HasPeripheryBlockDeviceModuleImp
|
||||
|
||||
//---------------------------------------------------------------------------------------------------------
|
||||
|
||||
class RocketTopWithGPIO(implicit p: Parameters) extends RocketTop
|
||||
with HasPeripheryGPIO {
|
||||
override lazy val module = new RocketTopWithGPIOModule(this)
|
||||
}
|
||||
|
||||
class RocketTopWithGPIOModule(l: RocketTopWithGPIO)
|
||||
extends RocketTopModule(l)
|
||||
with HasPeripheryGPIOModuleImp
|
||||
|
||||
// ----------------------
|
||||
// BOOM Top Level Systems
|
||||
// ----------------------
|
||||
|
||||
class BoomTop(implicit p: Parameters) extends boom.system.ExampleBoomSystem
|
||||
with HasNoDebug
|
||||
with HasPeripherySerial {
|
||||
override lazy val module = new BoomTopModule(this)
|
||||
}
|
||||
|
||||
class BoomTopModule[+L <: BoomTop](l: L) extends boom.system.ExampleBoomSystemModule(l)
|
||||
with HasRTCModuleImp
|
||||
with HasNoDebugModuleImp
|
||||
with HasPeripherySerialModuleImp
|
||||
with DontTouch
|
||||
|
||||
//---------------------------------------------------------------------------------------------------------
|
||||
|
||||
class BoomTopWithPWMTL(implicit p: Parameters) extends BoomTop
|
||||
with HasPeripheryPWMTL {
|
||||
override lazy val module = new BoomTopWithPWMTLModule(this)
|
||||
}
|
||||
|
||||
class BoomTopWithPWMTLModule(l: BoomTopWithPWMTL) extends BoomTopModule(l)
|
||||
with HasPeripheryPWMTLModuleImp
|
||||
|
||||
//---------------------------------------------------------------------------------------------------------
|
||||
|
||||
class BoomTopWithPWMAXI4(implicit p: Parameters) extends BoomTop
|
||||
with HasPeripheryPWMAXI4 {
|
||||
override lazy val module = new BoomTopWithPWMAXI4Module(this)
|
||||
}
|
||||
|
||||
class BoomTopWithPWMAXI4Module(l: BoomTopWithPWMAXI4) extends BoomTopModule(l)
|
||||
with HasPeripheryPWMAXI4ModuleImp
|
||||
|
||||
//---------------------------------------------------------------------------------------------------------
|
||||
|
||||
class BoomTopWithBlockDevice(implicit p: Parameters) extends BoomTop
|
||||
with HasPeripheryBlockDevice {
|
||||
override lazy val module = new BoomTopWithBlockDeviceModule(this)
|
||||
}
|
||||
|
||||
class BoomTopWithBlockDeviceModule(l: BoomTopWithBlockDevice) extends BoomTopModule(l)
|
||||
with HasPeripheryBlockDeviceModuleImp
|
||||
|
||||
//---------------------------------------------------------------------------------------------------------
|
||||
|
||||
class BoomTopWithGPIO(implicit p: Parameters) extends BoomTop
|
||||
with HasPeripheryGPIO {
|
||||
override lazy val module = new BoomTopWithGPIOModule(this)
|
||||
}
|
||||
|
||||
class BoomTopWithGPIOModule(l: BoomTopWithGPIO)
|
||||
extends BoomTopModule(l)
|
||||
with HasPeripheryGPIOModuleImp
|
||||
Reference in New Issue
Block a user