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Add BootROM | Fix ResetWrangler for DDR | Add scripts

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This commit is contained in:
Abraham Gonzalez
2020-10-20 21:20:11 -07:00
parent dd358f45ab
commit db73cab164
25 changed files with 1223 additions and 5 deletions
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3
fpga/src/main/scala/vcu118/bringup/TestHarness.scala
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@@ -134,8 +134,7 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends
/*** DDR ***/
val ddrWrangler = LazyModule(new ResetWrangler)
val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, ddrWrangler.node, harnessSysPLL))
val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL))
// connect 1 mem. channel to the FPGA DDR
val inParams = topDesign match { case td: ChipTop =>