Add BootROM | Fix ResetWrangler for DDR | Add scripts
This commit is contained in:
Abraham Gonzalez
36
fpga/src/main/resources/vcu118/sdboot/include/bits.h
Normal file
36
fpga/src/main/resources/vcu118/sdboot/include/bits.h
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@@ -0,0 +1,36 @@
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// See LICENSE for license details.
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#ifndef _RISCV_BITS_H
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#define _RISCV_BITS_H
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#define likely(x) __builtin_expect((x), 1)
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#define unlikely(x) __builtin_expect((x), 0)
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#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
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#define ROUNDDOWN(a, b) ((a)/(b)*(b))
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#define MAX(a, b) ((a) > (b) ? (a) : (b))
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#define MIN(a, b) ((a) < (b) ? (a) : (b))
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#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
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#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
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#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
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#define STR(x) XSTR(x)
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#define XSTR(x) #x
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#if __riscv_xlen == 64
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# define SLL32 sllw
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# define STORE sd
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# define LOAD ld
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# define LWU lwu
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# define LOG_REGBYTES 3
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#else
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# define SLL32 sll
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# define STORE sw
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# define LOAD lw
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# define LWU lw
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# define LOG_REGBYTES 2
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#endif
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#define REGBYTES (1 << LOG_REGBYTES)
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#endif
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18
fpga/src/main/resources/vcu118/sdboot/include/const.h
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18
fpga/src/main/resources/vcu118/sdboot/include/const.h
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@@ -0,0 +1,18 @@
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// See LICENSE for license details.
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/* Derived from <linux/const.h> */
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#ifndef _SIFIVE_CONST_H
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#define _SIFIVE_CONST_H
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#ifdef __ASSEMBLER__
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#define _AC(X,Y) X
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#define _AT(T,X) X
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#else
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#define _AC(X,Y) (X##Y)
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#define _AT(T,X) ((T)(X))
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#endif /* !__ASSEMBLER__*/
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#define _BITUL(x) (_AC(1,UL) << (x))
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#define _BITULL(x) (_AC(1,ULL) << (x))
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#endif /* _SIFIVE_CONST_H */
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@@ -0,0 +1,14 @@
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// See LICENSE for license details.
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#ifndef _SIFIVE_CLINT_H
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#define _SIFIVE_CLINT_H
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#define CLINT_MSIP 0x0000
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#define CLINT_MSIP_size 0x4
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#define CLINT_MTIMECMP 0x4000
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#define CLINT_MTIMECMP_size 0x8
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#define CLINT_MTIME 0xBFF8
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#define CLINT_MTIME_size 0x8
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#endif /* _SIFIVE_CLINT_H */
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24
fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h
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24
fpga/src/main/resources/vcu118/sdboot/include/devices/gpio.h
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@@ -0,0 +1,24 @@
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// See LICENSE for license details.
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#ifndef _SIFIVE_GPIO_H
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#define _SIFIVE_GPIO_H
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#define GPIO_INPUT_VAL (0x00)
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#define GPIO_INPUT_EN (0x04)
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#define GPIO_OUTPUT_EN (0x08)
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#define GPIO_OUTPUT_VAL (0x0C)
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#define GPIO_PULLUP_EN (0x10)
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#define GPIO_DRIVE (0x14)
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#define GPIO_RISE_IE (0x18)
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#define GPIO_RISE_IP (0x1C)
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#define GPIO_FALL_IE (0x20)
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#define GPIO_FALL_IP (0x24)
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#define GPIO_HIGH_IE (0x28)
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#define GPIO_HIGH_IP (0x2C)
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#define GPIO_LOW_IE (0x30)
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#define GPIO_LOW_IP (0x34)
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#define GPIO_IOF_EN (0x38)
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#define GPIO_IOF_SEL (0x3C)
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#define GPIO_OUTPUT_XOR (0x40)
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#endif /* _SIFIVE_GPIO_H */
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31
fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h
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31
fpga/src/main/resources/vcu118/sdboot/include/devices/plic.h
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@@ -0,0 +1,31 @@
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// See LICENSE for license details.
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#ifndef PLIC_H
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#define PLIC_H
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#include <const.h>
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// 32 bits per source
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#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL)
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#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2
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// 1 bit per source (1 address)
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#define PLIC_PENDING_OFFSET _AC(0x1000,UL)
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#define PLIC_PENDING_SHIFT_PER_SOURCE 0
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//0x80 per target
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#define PLIC_ENABLE_OFFSET _AC(0x2000,UL)
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#define PLIC_ENABLE_SHIFT_PER_TARGET 7
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#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL)
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#define PLIC_CLAIM_OFFSET _AC(0x200004,UL)
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#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
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#define PLIC_CLAIM_SHIFT_PER_TARGET 12
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#define PLIC_MAX_SOURCE 1023
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#define PLIC_SOURCE_MASK 0x3FF
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#define PLIC_MAX_TARGET 15871
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#define PLIC_TARGET_MASK 0x3FFF
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#endif /* PLIC_H */
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79
fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h
Normal file
79
fpga/src/main/resources/vcu118/sdboot/include/devices/spi.h
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@@ -0,0 +1,79 @@
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// See LICENSE for license details.
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#ifndef _SIFIVE_SPI_H
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#define _SIFIVE_SPI_H
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/* Register offsets */
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#define SPI_REG_SCKDIV 0x00
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#define SPI_REG_SCKMODE 0x04
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#define SPI_REG_CSID 0x10
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#define SPI_REG_CSDEF 0x14
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#define SPI_REG_CSMODE 0x18
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#define SPI_REG_DCSSCK 0x28
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#define SPI_REG_DSCKCS 0x2a
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#define SPI_REG_DINTERCS 0x2c
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#define SPI_REG_DINTERXFR 0x2e
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#define SPI_REG_FMT 0x40
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#define SPI_REG_TXFIFO 0x48
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#define SPI_REG_RXFIFO 0x4c
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#define SPI_REG_TXCTRL 0x50
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#define SPI_REG_RXCTRL 0x54
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#define SPI_REG_FCTRL 0x60
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#define SPI_REG_FFMT 0x64
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#define SPI_REG_IE 0x70
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#define SPI_REG_IP 0x74
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/* Fields */
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#define SPI_SCK_POL 0x1
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#define SPI_SCK_PHA 0x2
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#define SPI_FMT_PROTO(x) ((x) & 0x3)
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#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
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#define SPI_FMT_DIR(x) (((x) & 0x1) << 3)
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#define SPI_FMT_LEN(x) (((x) & 0xf) << 16)
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/* TXCTRL register */
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#define SPI_TXWM(x) ((x) & 0xffff)
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/* RXCTRL register */
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#define SPI_RXWM(x) ((x) & 0xffff)
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#define SPI_IP_TXWM 0x1
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#define SPI_IP_RXWM 0x2
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#define SPI_FCTRL_EN 0x1
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#define SPI_INSN_CMD_EN 0x1
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#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)
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#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)
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#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)
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#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)
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#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)
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#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)
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#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
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#define SPI_TXFIFO_FULL (1 << 31)
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#define SPI_RXFIFO_EMPTY (1 << 31)
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/* Values */
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#define SPI_CSMODE_AUTO 0
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#define SPI_CSMODE_HOLD 2
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#define SPI_CSMODE_OFF 3
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#define SPI_DIR_RX 0
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#define SPI_DIR_TX 1
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#define SPI_PROTO_S 0
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#define SPI_PROTO_D 1
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#define SPI_PROTO_Q 2
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#define SPI_ENDIAN_MSB 0
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#define SPI_ENDIAN_LSB 1
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#endif /* _SIFIVE_SPI_H */
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28
fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h
Normal file
28
fpga/src/main/resources/vcu118/sdboot/include/devices/uart.h
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@@ -0,0 +1,28 @@
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// See LICENSE for license details.
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#ifndef _SIFIVE_UART_H
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#define _SIFIVE_UART_H
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/* Register offsets */
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#define UART_REG_TXFIFO 0x00
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#define UART_REG_RXFIFO 0x04
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#define UART_REG_TXCTRL 0x08
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#define UART_REG_RXCTRL 0x0c
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#define UART_REG_IE 0x10
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#define UART_REG_IP 0x14
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#define UART_REG_DIV 0x18
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/* TXCTRL register */
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#define UART_TXEN 0x1
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#define UART_TXNSTOP 0x2
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#define UART_TXWM(x) (((x) & 0xffff) << 16)
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/* RXCTRL register */
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#define UART_RXEN 0x1
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#define UART_RXWM(x) (((x) & 0xffff) << 16)
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/* IP register */
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#define UART_IP_TXWM 0x1
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#define UART_IP_RXWM 0x2
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#endif /* _SIFIVE_UART_H */
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108
fpga/src/main/resources/vcu118/sdboot/include/platform.h
Normal file
108
fpga/src/main/resources/vcu118/sdboot/include/platform.h
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@@ -0,0 +1,108 @@
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// See LICENSE for license details.
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#ifndef _EAGLE_PLATFORM_H
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#define _EAGLE_PLATFORM_H
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#include "const.h"
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#include "riscv_test_defaults.h"
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#include "devices/clint.h"
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#include "devices/gpio.h"
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#include "devices/plic.h"
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#include "devices/spi.h"
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#include "devices/uart.h"
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// Some things missing from the official encoding.h
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#if __riscv_xlen == 32
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#define MCAUSE_INT 0x80000000UL
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#define MCAUSE_CAUSE 0x7FFFFFFFUL
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#else
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#define MCAUSE_INT 0x8000000000000000UL
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#define MCAUSE_CAUSE 0x7FFFFFFFFFFFFFFFUL
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#endif
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/****************************************************************************
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* Platform definitions
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*****************************************************************************/
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// CPU info
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#define NUM_CORES 1
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#define GLOBAL_INT_SIZE 38
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#define GLOBAL_INT_MAX_PRIORITY 7
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// Memory map
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#define CLINT_CTRL_ADDR _AC(0x2000000,UL)
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#define CLINT_CTRL_SIZE _AC(0x10000,UL)
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#define DEBUG_CTRL_ADDR _AC(0x0,UL)
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#define DEBUG_CTRL_SIZE _AC(0x1000,UL)
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#define ERROR_MEM_ADDR _AC(0x3000,UL)
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#define ERROR_MEM_SIZE _AC(0x1000,UL)
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#define GPIO_CTRL_ADDR _AC(0x64002000,UL)
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#define GPIO_CTRL_SIZE _AC(0x1000,UL)
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#define MASKROM_MEM_ADDR _AC(0x10000,UL)
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#define MASKROM_MEM_SIZE _AC(0x10000,UL)
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#define MEMORY_MEM_ADDR _AC(0x80000000,UL)
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#define MEMORY_MEM_SIZE _AC(0x10000000,UL)
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#define PLIC_CTRL_ADDR _AC(0xc000000,UL)
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#define PLIC_CTRL_SIZE _AC(0x4000000,UL)
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#define SPI_CTRL_ADDR _AC(0x64001000,UL)
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#define SPI_CTRL_SIZE _AC(0x1000,UL)
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#define SPI1_CTRL_ADDR _AC(0x64004000,UL)
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#define SPI1_CTRL_SIZE _AC(0x1000,UL)
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#define TEST_CTRL_ADDR _AC(0x4000,UL)
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#define TEST_CTRL_SIZE _AC(0x1000,UL)
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#define UART_CTRL_ADDR _AC(0x64000000,UL)
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#define UART_CTRL_SIZE _AC(0x1000,UL)
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#define UART1_CTRL_ADDR _AC(0x64003000,UL)
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#define UART1_CTRL_SIZE _AC(0x1000,UL)
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#define I2C_CTRL_ADDR _AC(0x64005000,UL)
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#define I2C_CTRL_SIZE _AC(0x1000,UL)
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// IOF masks
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// Interrupt numbers
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#define UART_INT_BASE 1
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#define UART1_INT_BASE 2
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#define I2C_INT_BASE 3
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#define GPIO_INT_BASE 4
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#define SPI_INT_BASE 36
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#define SPI1_INT_BASE 37
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// Helper functions
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#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i)))
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#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
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#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i)))
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// Bulk set bits in `reg` to either 0 or 1.
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// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7
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// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7
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#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); }
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#define AXI_PCIE_HOST_1_00_A_REG(offset) _REG32(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset)
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#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
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#define DEBUG_REG(offset) _REG32(DEBUG_CTRL_ADDR, offset)
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#define ERROR_REG(offset) _REG32(ERROR_CTRL_ADDR, offset)
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#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
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#define MASKROM_REG(offset) _REG32(MASKROM_CTRL_ADDR, offset)
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#define MEMORY_REG(offset) _REG32(MEMORY_CTRL_ADDR, offset)
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#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
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#define SPI_REG(offset) _REG32(SPI_CTRL_ADDR, offset)
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#define TEST_REG(offset) _REG32(TEST_CTRL_ADDR, offset)
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#define UART_REG(offset) _REG32(UART_CTRL_ADDR, offset)
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#define AXI_PCIE_HOST_1_00_A_REG64(offset) _REG64(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset)
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#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset)
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#define DEBUG_REG64(offset) _REG64(DEBUG_CTRL_ADDR, offset)
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#define ERROR_REG64(offset) _REG64(ERROR_CTRL_ADDR, offset)
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#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset)
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#define MASKROM_REG64(offset) _REG64(MASKROM_CTRL_ADDR, offset)
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#define MEMORY_REG64(offset) _REG64(MEMORY_CTRL_ADDR, offset)
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#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset)
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#define SPI_REG64(offset) _REG64(SPI_CTRL_ADDR, offset)
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#define SPI1_REG64(offset) _REG64(SPI1_CTRL_ADDR, offset)
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#define TEST_REG64(offset) _REG64(TEST_CTRL_ADDR, offset)
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#define UART_REG64(offset) _REG64(UART_CTRL_ADDR, offset)
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#define UART1_REG64(offset) _REG64(UART1_CTRL_ADDR, offset)
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#define I2C_REG64(offset) _REG64(I2C_CTRL_ADDR, offset)
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// Misc
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||||
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#endif /* _SIFIVE_PLATFORM_H */
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||||
@@ -0,0 +1,81 @@
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||||
// See LICENSE for license details.
|
||||
#ifndef _RISCV_TEST_DEFAULTS_H
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||||
#define _RISCV_TEST_DEFAULTS_H
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||||
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||||
#define TESTNUM x28
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#define TESTBASE 0x4000
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#define RVTEST_RV32U \
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.macro init; \
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||||
.endm
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#define RVTEST_RV64U \
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.macro init; \
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.endm
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#define RVTEST_RV32UF \
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.macro init; \
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/* If FPU exists, initialize FCSR. */ \
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||||
csrr t0, misa; \
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andi t0, t0, 1 << ('F' - 'A'); \
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||||
beqz t0, 1f; \
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||||
/* Enable FPU if it exists. */ \
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||||
li t0, MSTATUS_FS; \
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csrs mstatus, t0; \
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fssr x0; \
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||||
1: ; \
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||||
.endm
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#define RVTEST_RV64UF \
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.macro init; \
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/* If FPU exists, initialize FCSR. */ \
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||||
csrr t0, misa; \
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andi t0, t0, 1 << ('F' - 'A'); \
|
||||
beqz t0, 1f; \
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||||
/* Enable FPU if it exists. */ \
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||||
li t0, MSTATUS_FS; \
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||||
csrs mstatus, t0; \
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||||
fssr x0; \
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||||
1: ; \
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||||
.endm
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||||
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||||
#define RVTEST_CODE_BEGIN \
|
||||
.section .text.init; \
|
||||
.globl _prog_start; \
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||||
_prog_start: \
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||||
init;
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||||
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||||
#define RVTEST_CODE_END \
|
||||
unimp
|
||||
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||||
#define RVTEST_PASS \
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||||
fence; \
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||||
li t0, TESTBASE; \
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||||
li t1, 0x5555; \
|
||||
sw t1, 0(t0); \
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||||
1: \
|
||||
j 1b;
|
||||
|
||||
#define RVTEST_FAIL \
|
||||
li t0, TESTBASE; \
|
||||
li t1, 0x3333; \
|
||||
slli a0, a0, 16; \
|
||||
add a0, a0, t1; \
|
||||
sw a0, 0(t0); \
|
||||
1: \
|
||||
j 1b;
|
||||
|
||||
#define EXTRA_DATA
|
||||
|
||||
#define RVTEST_DATA_BEGIN \
|
||||
EXTRA_DATA \
|
||||
.align 4; .global begin_signature; begin_signature:
|
||||
|
||||
#define RVTEST_DATA_END \
|
||||
_msg_init: .asciz "RUN\r\n"; \
|
||||
_msg_pass: .asciz "PASS"; \
|
||||
_msg_fail: .asciz "FAIL "; \
|
||||
_msg_end: .asciz "\r\n"; \
|
||||
.align 4; .global end_signature; end_signature:
|
||||
|
||||
#endif /* _RISCV_TEST_DEFAULTS_H */
|
||||
17
fpga/src/main/resources/vcu118/sdboot/include/sections.h
Normal file
17
fpga/src/main/resources/vcu118/sdboot/include/sections.h
Normal file
@@ -0,0 +1,17 @@
|
||||
// See LICENSE for license details.
|
||||
#ifndef _SECTIONS_H
|
||||
#define _SECTIONS_H
|
||||
|
||||
extern unsigned char _rom[];
|
||||
extern unsigned char _rom_end[];
|
||||
|
||||
extern unsigned char _ram[];
|
||||
extern unsigned char _ram_end[];
|
||||
|
||||
extern unsigned char _ftext[];
|
||||
extern unsigned char _etext[];
|
||||
extern unsigned char _fbss[];
|
||||
extern unsigned char _ebss[];
|
||||
extern unsigned char _end[];
|
||||
|
||||
#endif /* _SECTIONS_H */
|
||||
142
fpga/src/main/resources/vcu118/sdboot/include/smp.h
Normal file
142
fpga/src/main/resources/vcu118/sdboot/include/smp.h
Normal file
@@ -0,0 +1,142 @@
|
||||
#ifndef SIFIVE_SMP
|
||||
#define SIFIVE_SMP
|
||||
#include "platform.h"
|
||||
|
||||
// The maximum number of HARTs this code supports
|
||||
#ifndef MAX_HARTS
|
||||
#define MAX_HARTS 32
|
||||
#endif
|
||||
#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4)
|
||||
#define CLINT1_END_HART_IPI CLINT1_CTRL_ADDR + (MAX_HARTS*4)
|
||||
|
||||
// The hart that non-SMP tests should run on
|
||||
#ifndef NONSMP_HART
|
||||
#define NONSMP_HART 0
|
||||
#endif
|
||||
|
||||
/* If your test cannot handle multiple-threads, use this:
|
||||
* smp_disable(reg1)
|
||||
*/
|
||||
#define smp_disable(reg1, reg2) \
|
||||
csrr reg1, mhartid ;\
|
||||
li reg2, NONSMP_HART ;\
|
||||
beq reg1, reg2, hart0_entry ;\
|
||||
42: ;\
|
||||
wfi ;\
|
||||
j 42b ;\
|
||||
hart0_entry:
|
||||
|
||||
/* If your test needs to temporarily block multiple-threads, do this:
|
||||
* smp_pause(reg1, reg2)
|
||||
* ... single-threaded work ...
|
||||
* smp_resume(reg1, reg2)
|
||||
* ... multi-threaded work ...
|
||||
*/
|
||||
|
||||
#define smp_pause(reg1, reg2) \
|
||||
li reg2, 0x8 ;\
|
||||
csrw mie, reg2 ;\
|
||||
li reg1, NONSMP_HART ;\
|
||||
csrr reg2, mhartid ;\
|
||||
bne reg1, reg2, 42f
|
||||
|
||||
#ifdef CLINT1_CTRL_ADDR
|
||||
// If a second CLINT exists, then make sure we:
|
||||
// 1) Trigger a software interrupt on all harts of both CLINTs.
|
||||
// 2) Locate your own hart's software interrupt pending register and clear it.
|
||||
// 3) Wait for all harts on both CLINTs to clear their software interrupt
|
||||
// pending register.
|
||||
// WARNING: This code makes these assumptions, which are only true for Fadu as
|
||||
// of now:
|
||||
// 1) hart0 uses CLINT0 at offset 0
|
||||
// 2) hart2 uses CLINT1 at offset 0
|
||||
// 3) hart3 uses CLINT1 at offset 1
|
||||
// 4) There are no other harts or CLINTs in the system.
|
||||
#define smp_resume(reg1, reg2) \
|
||||
/* Trigger software interrupt on CLINT0 */ \
|
||||
li reg1, CLINT_CTRL_ADDR ;\
|
||||
41: ;\
|
||||
li reg2, 1 ;\
|
||||
sw reg2, 0(reg1) ;\
|
||||
addi reg1, reg1, 4 ;\
|
||||
li reg2, CLINT_END_HART_IPI ;\
|
||||
blt reg1, reg2, 41b ;\
|
||||
/* Trigger software interrupt on CLINT1 */ \
|
||||
li reg1, CLINT1_CTRL_ADDR ;\
|
||||
41: ;\
|
||||
li reg2, 1 ;\
|
||||
sw reg2, 0(reg1) ;\
|
||||
addi reg1, reg1, 4 ;\
|
||||
li reg2, CLINT1_END_HART_IPI ;\
|
||||
blt reg1, reg2, 41b ;\
|
||||
/* Wait to receive software interrupt */ \
|
||||
42: ;\
|
||||
wfi ;\
|
||||
csrr reg2, mip ;\
|
||||
andi reg2, reg2, 0x8 ;\
|
||||
beqz reg2, 42b ;\
|
||||
/* Clear own software interrupt bit */ \
|
||||
csrr reg2, mhartid ;\
|
||||
bnez reg2, 41f; \
|
||||
/* hart0 case: Use CLINT0 */ \
|
||||
li reg1, CLINT_CTRL_ADDR ;\
|
||||
slli reg2, reg2, 2 ;\
|
||||
add reg2, reg2, reg1 ;\
|
||||
sw zero, 0(reg2) ;\
|
||||
j 42f; \
|
||||
41: \
|
||||
/* hart 2, 3 case: Use CLINT1 and remap hart IDs to 0 and 1 */ \
|
||||
li reg1, CLINT1_CTRL_ADDR ;\
|
||||
addi reg2, reg2, -2; \
|
||||
slli reg2, reg2, 2 ;\
|
||||
add reg2, reg2, reg1 ;\
|
||||
sw zero, 0(reg2) ; \
|
||||
42: \
|
||||
/* Wait for all software interrupt bits to be cleared on CLINT0 */ \
|
||||
li reg1, CLINT_CTRL_ADDR ;\
|
||||
41: ;\
|
||||
lw reg2, 0(reg1) ;\
|
||||
bnez reg2, 41b ;\
|
||||
addi reg1, reg1, 4 ;\
|
||||
li reg2, CLINT_END_HART_IPI ;\
|
||||
blt reg1, reg2, 41b; \
|
||||
/* Wait for all software interrupt bits to be cleared on CLINT1 */ \
|
||||
li reg1, CLINT1_CTRL_ADDR ;\
|
||||
41: ;\
|
||||
lw reg2, 0(reg1) ;\
|
||||
bnez reg2, 41b ;\
|
||||
addi reg1, reg1, 4 ;\
|
||||
li reg2, CLINT1_END_HART_IPI ;\
|
||||
blt reg1, reg2, 41b; \
|
||||
/* End smp_resume() */
|
||||
|
||||
#else
|
||||
|
||||
#define smp_resume(reg1, reg2) \
|
||||
li reg1, CLINT_CTRL_ADDR ;\
|
||||
41: ;\
|
||||
li reg2, 1 ;\
|
||||
sw reg2, 0(reg1) ;\
|
||||
addi reg1, reg1, 4 ;\
|
||||
li reg2, CLINT_END_HART_IPI ;\
|
||||
blt reg1, reg2, 41b ;\
|
||||
42: ;\
|
||||
wfi ;\
|
||||
csrr reg2, mip ;\
|
||||
andi reg2, reg2, 0x8 ;\
|
||||
beqz reg2, 42b ;\
|
||||
li reg1, CLINT_CTRL_ADDR ;\
|
||||
csrr reg2, mhartid ;\
|
||||
slli reg2, reg2, 2 ;\
|
||||
add reg2, reg2, reg1 ;\
|
||||
sw zero, 0(reg2) ;\
|
||||
41: ;\
|
||||
lw reg2, 0(reg1) ;\
|
||||
bnez reg2, 41b ;\
|
||||
addi reg1, reg1, 4 ;\
|
||||
li reg2, CLINT_END_HART_IPI ;\
|
||||
blt reg1, reg2, 41b
|
||||
|
||||
#endif /* ifdef CLINT1_CTRL_ADDR */
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user