wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

This file seems to have missed a scalafmt pass

Browse Source
This commit is contained in:
chick
2021-08-17 16:14:32 -07:00
parent 143af1aa04
commit db54d55074
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/barstools/macros/Utils.scala
View File

@@ -55,8 +55,8 @@ class Macro(srcMacro: SRAMMacro) {
val firrtlPorts: Seq[FirrtlMacroPort] = srcMacro.ports.map { new FirrtlMacroPort(_) } val firrtlPorts: Seq[FirrtlMacroPort] = srcMacro.ports.map { new FirrtlMacroPort(_) }
val writers: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isWriter) val writers: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isWriter)
val readers: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isReader) val readers: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isReader)
val readwriters: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isReadWriter) val readwriters: Seq[FirrtlMacroPort] = firrtlPorts.filter(p => p.isReadWriter)
val sortedPorts: Seq[FirrtlMacroPort] = writers ++ readers ++ readwriters val sortedPorts: Seq[FirrtlMacroPort] = writers ++ readers ++ readwriters