From db1d84d9f8e52878c47f29a89cfbf871d08dda4f Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 25 Sep 2019 17:57:49 -0700 Subject: [PATCH] typo --- docs/Generators/Rocket.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Generators/Rocket.rst b/docs/Generators/Rocket.rst index 50da2777..96796738 100644 --- a/docs/Generators/Rocket.rst +++ b/docs/Generators/Rocket.rst @@ -1,7 +1,7 @@ Rocket Core ==================================== -`Rocket `__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley an currently supported by `SiFive `__. The `Rocket core` is used as a component within the `Rocket Chip SoC generator`. A Rocket core combined with L1 caches (data and instruction caches) form a `Rocket tile`. The `Rocket tile` is the replicable component of the `Rocket Chip SoC generator`. +`Rocket `__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley and currently supported by `SiFive `__. The `Rocket core` is used as a component within the `Rocket Chip SoC generator`. A Rocket core combined with L1 caches (data and instruction caches) form a `Rocket tile`. The `Rocket tile` is the replicable component of the `Rocket Chip SoC generator`. The Rocket core supports the open source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language. It has an MMU that supports page-based virtual memory, a non-blocking data cache, and a front-end with branch prediction.