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expose functional pins and ports

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This commit is contained in:
Haoan Li
2022-12-13 16:53:31 +09:00
parent 0724431873
commit dab5720445
2 changed files with 15 additions and 3 deletions
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16
fpga/src/main/scala/vc707/TestHarness.scala
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@@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLClientNode}
import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay} import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay}
import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly} import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
import sifive.fpgashells.shell.{ClockInputOverlayKey, ClockInputDesignInput, UARTOverlayKey, UARTDesignInput, UARTShellInput, SPIOverlayKey, SPIDesignInput, PCIeOverlayKey, PCIeDesignInput, PCIeShellInput, DDROverlayKey, DDRDesignInput} import sifive.fpgashells.shell.{ClockInputOverlayKey, ClockInputDesignInput, UARTOverlayKey, UARTDesignInput, UARTShellInput, LEDOverlayKey, LEDDesignInput, SwitchOverlayKey, SwitchDesignInput, ButtonOverlayKey, ButtonDesignInput, SPIOverlayKey, SPIDesignInput, ChipLinkOverlayKey, ChipLinkDesignInput, PCIeOverlayKey, PCIeDesignInput, PCIeShellInput, DDROverlayKey, DDRDesignInput, JTAGDebugOverlayKey, JTAGDebugDesignInput}
import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler} import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{XilinxVC707PCIeX1IO} import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{XilinxVC707PCIeX1IO}
@@ -31,7 +31,7 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
// place all clocks in the shell // place all clocks in the shell
require(dp(ClockInputOverlayKey).size >= 1) require(dp(ClockInputOverlayKey).size >= 1)
val sysClkNode = dp(ClockInputOverlayKey)(0).place(ClockInputDesignInput()).overlayOutput.node val sysClkNode = dp(ClockInputOverlayKey).head.place(ClockInputDesignInput()).overlayOutput.node
/*** Connect/Generate clocks ***/ /*** Connect/Generate clocks ***/
@@ -46,6 +46,18 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
val dutGroup = ClockGroup() val dutGroup = ClockGroup()
dutClock := dutWrangler.node := dutGroup := harnessSysPLL dutClock := dutWrangler.node := dutGroup := harnessSysPLL
/*** LED ***/
val ledModule = dp(LEDOverlayKey).map(_.place(LEDDesignInput()).overlayOutput.led)
/*** Switch ***/
val switchModule = dp(SwitchOverlayKey).map(_.place(SwitchDesignInput()).overlayOutput.sw)
/*** Button ***/
val buttonModule = dp(ButtonOverlayKey).map(_.place(ButtonDesignInput()).overlayOutput.but)
/*** JTAG ***/
val jtagModule = dp(JTAGDebugOverlayKey).head.place(JTAGDebugDesignInput()).overlayOutput.jtag
/*** UART ***/ /*** UART ***/
// 1st UART goes to the VC707 dedicated UART // 1st UART goes to the VC707 dedicated UART