diff --git a/build.sbt b/build.sbt
index fd9638b1..83a5f93f 100644
--- a/build.sbt
+++ b/build.sbt
@@ -13,9 +13,8 @@ lazy val commonSettings = Seq(
   libraryDependencies ++= Seq("chisel3","chisel-iotesters").map {
     dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep))
   },
-  libraryDependencies in Test ++= Seq(
-    "org.scalatest" %% "scalatest" % "2.2.5" % "test",
-    "org.scalacheck" %% "scalacheck" % "1.12.4" % "test"
+  libraryDependencies ++= Seq(
+    "org.scalatest" %% "scalatest" % "3.2.2" % "test",
   ),
   resolvers ++= Seq(
     Resolver.sonatypeRepo("snapshots"),
@@ -31,9 +30,6 @@ lazy val macros = (project in file("macros"))
   .dependsOn(mdf)
   .settings(commonSettings)
   .settings(
-    libraryDependencies ++= Seq(
-      "edu.berkeley.cs" %% "firrtl-interpreter" % "1.4.+" % Test
-    ),
     mainClass := Some("barstools.macros.MacroCompiler")
   )
   .enablePlugins(sbtassembly.AssemblyPlugin)
diff --git a/macros/src/test/scala/barstools/macros/MacroCompilerSpec.scala b/macros/src/test/scala/barstools/macros/MacroCompilerSpec.scala
index 9140ce24..2b239227 100644
--- a/macros/src/test/scala/barstools/macros/MacroCompilerSpec.scala
+++ b/macros/src/test/scala/barstools/macros/MacroCompilerSpec.scala
@@ -6,10 +6,12 @@ import firrtl.Parser.parse
 import firrtl.ir.{Circuit, NoInfo}
 import firrtl.passes.RemoveEmpty
 import mdf.macrolib.SRAMMacro
+import org.scalatest.flatspec.AnyFlatSpec
+import org.scalatest.matchers.should.Matchers
 
 import java.io.File
 
-abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalatest.Matchers {
+abstract class MacroCompilerSpec extends AnyFlatSpec with Matchers {
   import scala.language.implicitConversions
   implicit def String2SomeString(i: String): Option[String] = Some(i)
   val testDir: String = "test_run_dir/macros"
diff --git a/tapeout/src/test/scala/barstools/tapeout/transforms/ResetInverterSpec.scala b/tapeout/src/test/scala/barstools/tapeout/transforms/ResetInverterSpec.scala
index d74360b7..701c7845 100644
--- a/tapeout/src/test/scala/barstools/tapeout/transforms/ResetInverterSpec.scala
+++ b/tapeout/src/test/scala/barstools/tapeout/transforms/ResetInverterSpec.scala
@@ -5,7 +5,8 @@ package barstools.tapeout.transforms
 import chisel3._
 import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import firrtl.{EmittedFirrtlCircuitAnnotation, EmittedFirrtlModuleAnnotation}
-import org.scalatest.{FreeSpec, Matchers}
+import org.scalatest.freespec.AnyFreeSpec
+import org.scalatest.matchers.should.Matchers
 
 class ExampleModuleNeedsResetInverted extends Module with ResetInverter {
   val io = IO(new Bundle {
@@ -19,7 +20,7 @@ class ExampleModuleNeedsResetInverted extends Module with ResetInverter {
   invert(this)
 }
 
-class ResetNSpec extends FreeSpec with Matchers {
+class ResetNSpec extends AnyFreeSpec with Matchers {
   "Inverting reset needs to be done throughout module in Chirrtl" in {
     val chirrtl = (new ChiselStage).emitChirrtl(new ExampleModuleNeedsResetInverted)
     chirrtl should include("input reset :")
diff --git a/tapeout/src/test/scala/barstools/tapeout/transforms/retime/RetimeSpec.scala b/tapeout/src/test/scala/barstools/tapeout/transforms/retime/RetimeSpec.scala
index 0e164521..a086b0b9 100644
--- a/tapeout/src/test/scala/barstools/tapeout/transforms/retime/RetimeSpec.scala
+++ b/tapeout/src/test/scala/barstools/tapeout/transforms/retime/RetimeSpec.scala
@@ -6,9 +6,10 @@ import chisel3._
 import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import firrtl.{EmittedFirrtlCircuitAnnotation, EmittedFirrtlModuleAnnotation, FileUtils}
 import logger.Logger
-import org.scalatest.{FlatSpec, Matchers}
+import org.scalatest.flatspec.AnyFlatSpec
+import org.scalatest.matchers.should.Matchers
 
-class RetimeSpec extends FlatSpec with Matchers {
+class RetimeSpec extends AnyFlatSpec with Matchers {
   def normalized(s: String): String = {
     require(!s.contains("\n"))
     s.replaceAll("\\s+", " ").trim