diff --git a/barstools b/barstools
index 1f58ea1e..9d505d60 160000
--- a/barstools
+++ b/barstools
@@ -1 +1 @@
-Subproject commit 1f58ea1e141c69276ae1680a9ece6c42a31653e5
+Subproject commit 9d505d6063f07f7750686f67d2cda49b17f6d898
diff --git a/testchipip b/testchipip
index 1fa12ec9..4775caf9 160000
--- a/testchipip
+++ b/testchipip
@@ -1 +1 @@
-Subproject commit 1fa12ec97974dcb04e1e588e799d349c6580095b
+Subproject commit 4775caf9f23826fed9e2400c48ca0cfb88f9eb8f
diff --git a/verisim/Makefile b/verisim/Makefile
index d4ca59a1..48aef887 100644
--- a/verisim/Makefile
+++ b/verisim/Makefile
@@ -6,6 +6,7 @@ MODEL ?= TestHarness
 CONFIG ?= DefaultExampleConfig
 CFG_PROJECT ?= $(PROJECT)
 TB ?= TestDriver
+TOP ?= ExampleTop
 
 sim = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)
 sim_debug = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)-debug
@@ -20,12 +21,12 @@ LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesv
 include $(base_dir)/Makefrag
 include $(sim_dir)/Makefrag-verilator
 
-long_name = $(PROJECT).$(MODEL).$(CONFIG)
-
 rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
 
 sim_vsrcs = \
-	$(build_dir)/$(long_name).v \
+	$(VERILOG_FILE) \
+	$(HARNESS_FILE) \
+	$(SMEMS_FILE) \
 	$(rocketchip_vsrc_dir)/AsyncResetReg.v \
 	$(rocketchip_vsrc_dir)/plusarg_reader.v \
 	$(testchip_vsrcs)
@@ -47,7 +48,7 @@ $(model_mk): $(sim_vsrcs) $(INSTALLED_VERILATOR)
 	rm -rf $(build_dir)/$(long_name)
 	mkdir -p $(build_dir)/$(long_name)
 	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
-	-o $(sim) $< $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
+	-o $(sim) $(sim_vsrcs) $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
 	-CFLAGS "-I$(build_dir) -include $(model_header)"
 	touch $@
 
diff --git a/verisim/Makefrag-verilator b/verisim/Makefrag-verilator
index b16cd60f..01928f75 100644
--- a/verisim/Makefrag-verilator
+++ b/verisim/Makefrag-verilator
@@ -29,9 +29,8 @@ rocketchip_csrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/csrc
 # Run Verilator to produce a fast binary to emulate this circuit.
 VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
 VERILATOR_FLAGS := --top-module $(MODEL) \
-  +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
-  +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
-  --output-split 20000 \
+	+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
+	+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
+	--output-split 20000 \
 	-Wno-STMTDLY --x-assign unique \
-  -I$(base_dir)/testchipip/vsrc -I$(base_dir)/rocket-chip/vsrc \
-  -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(rocketchip_csrc_dir)/verilator.h"
+	-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(rocketchip_csrc_dir)/verilator.h"