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Fix TLMemPort comment | Use Option instead of NoSimulator

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This commit is contained in:
abejgonzalez
2020-11-15 15:44:38 -08:00
parent c8add488ad
commit d94a8efd43
2 changed files with 13 additions and 14 deletions
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2
fpga/src/main/scala/vcu118/DigitalTop.scala
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@@ -69,7 +69,7 @@ class VCU118ChipyardSystemModule[+L <: VCU118ChipyardSystem](_outer: L) extends
// VCU118 Mem Port Mixin // VCU118 Mem Port Mixin
// ------------------------------------ // ------------------------------------
/** Adds a TileLink port to the system intended to master an MMIO device bus */ /** Adds a port to the system intended to master an TL DRAM controller. */
trait CanHaveMasterTLMemPort { this: BaseSubsystem => trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
private val memPortParamsOpt = p(ExtMem) private val memPortParamsOpt = p(ExtMem)
private val portName = "tl_mem" private val portName = "tl_mem"

25
generators/utilities/src/main/scala/Simulator.scala
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@@ -5,13 +5,12 @@ import java.io.File
case class GenerateSimConfig( case class GenerateSimConfig(
targetDir: String = ".", targetDir: String = ".",
dotFName: String = "sim_files.f", dotFName: String = "sim_files.f",
simulator: Simulator = VerilatorSimulator, simulator: Option[Simulator] = Some(VerilatorSimulator)
) )
sealed trait Simulator sealed trait Simulator
object VerilatorSimulator extends Simulator object VerilatorSimulator extends Simulator
object VCSSimulator extends Simulator object VCSSimulator extends Simulator
object NoSimulator extends Simulator
trait HasGenerateSimConfig { trait HasGenerateSimConfig {
val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") { val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") {
@@ -21,9 +20,9 @@ trait HasGenerateSimConfig {
.abbr("sim") .abbr("sim")
.valueName("<simulator-name>") .valueName("<simulator-name>")
.action((x, c) => x match { .action((x, c) => x match {
case "verilator" => c.copy(simulator = VerilatorSimulator) case "verilator" => c.copy(simulator = Some(VerilatorSimulator))
case "vcs" => c.copy(simulator = VCSSimulator) case "vcs" => c.copy(simulator = Some(VCSSimulator))
case "none" => c.copy(simulator = NoSimulator) case "none" => c.copy(simulator = None)
case _ => throw new Exception(s"Unrecognized simulator $x") case _ => throw new Exception(s"Unrecognized simulator $x")
}) })
.text("Name of simulator to generate files for (verilator, vcs, none)") .text("Name of simulator to generate files for (verilator, vcs, none)")
@@ -49,10 +48,10 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
if (fname.takeRight(2) == ".h") { if (fname.takeRight(2) == ".h") {
cfg.simulator match { cfg.simulator match {
// verilator needs to explicitly include verilator.h, so use the -FI option // verilator needs to explicitly include verilator.h, so use the -FI option
case VerilatorSimulator => s"-FI ${fname}" case Some(VerilatorSimulator) => s"-FI ${fname}"
// vcs pulls headers in with +incdir, doesn't have anything like verilator.h // vcs pulls headers in with +incdir, doesn't have anything like verilator.h
case VCSSimulator => "" case Some(VCSSimulator) => ""
case NoSimulator => "" case None => ""
} }
} else { // do nothing otherwise } else { // do nothing otherwise
fname fname
@@ -84,7 +83,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
out.write(text) out.write(text)
out.close() out.close()
} }
def resources(sim: Simulator): Seq[String] = Seq( def resources(sim: Option[Simulator]): Seq[String] = Seq(
"/testchipip/csrc/SimSerial.cc", "/testchipip/csrc/SimSerial.cc",
"/testchipip/csrc/testchip_tsi.cc", "/testchipip/csrc/testchip_tsi.cc",
"/testchipip/csrc/testchip_tsi.h", "/testchipip/csrc/testchip_tsi.h",
@@ -99,7 +98,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
"/csrc/remote_bitbang.cc", "/csrc/remote_bitbang.cc",
"/vsrc/EICG_wrapper.v", "/vsrc/EICG_wrapper.v",
) ++ (sim match { ) ++ (sim match {
case NoSimulator => Seq() case None => Seq()
case _ => Seq( case _ => Seq(
"/testchipip/csrc/SimSerial.cc", "/testchipip/csrc/SimSerial.cc",
"/testchipip/csrc/SimDRAM.cc", "/testchipip/csrc/SimDRAM.cc",
@@ -113,14 +112,14 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
"/csrc/remote_bitbang.cc", "/csrc/remote_bitbang.cc",
) )
}) ++ (sim match { // simulator specific files to include }) ++ (sim match { // simulator specific files to include
case VerilatorSimulator => Seq( case Some(VerilatorSimulator) => Seq(
"/csrc/emulator.cc", "/csrc/emulator.cc",
"/csrc/verilator.h", "/csrc/verilator.h",
) )
case VCSSimulator => Seq( case Some(VCSSimulator) => Seq(
"/vsrc/TestDriver.v", "/vsrc/TestDriver.v",
) )
case NoSimulator => Seq() case None => Seq()
}) })
def writeBootrom(): Unit = { def writeBootrom(): Unit = {