Fix TLMemPort comment | Use Option instead of NoSimulator

2020-11-15 15:44:38 -08:00
parent c8add488ad
commit d94a8efd43
2 changed files with 13 additions and 14 deletions
--- a/fpga/src/main/scala/vcu118/DigitalTop.scala
+++ b/fpga/src/main/scala/vcu118/DigitalTop.scala
@@ -69,7 +69,7 @@ class VCU118ChipyardSystemModule[+L <: VCU118ChipyardSystem](_outer: L) extends
 // VCU118 Mem Port Mixin
 // ------------------------------------

-/** Adds a TileLink port to the system intended to master an MMIO device bus */
+/** Adds a port to the system intended to master an TL DRAM controller. */
 trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
  private val memPortParamsOpt = p(ExtMem)
  private val portName = "tl_mem"