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Update firechip for new testchipip

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This commit is contained in:
Jerry Zhao
2023-10-24 18:42:27 -07:00
parent 68f7c90938
commit d83f395738
2 changed files with 7 additions and 6 deletions
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4
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -69,7 +69,7 @@ class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
case (th: FireSim, port: SerialTLPort) => { case (th: FireSim, port: SerialTLPort) => {
val bits = port.io.bits val bits = port.io.bits
port.io.clock := th.harnessBinderClock port.io.clock := th.harnessBinderClock
val ram = LazyModule(new SerialRAM(port.serdesser)(Parameters.empty)) val ram = LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p))
Module(ram.module) Module(ram.module)
ram.module.io.ser <> port.io.bits ram.module.io.ser <> port.io.bits
@@ -78,7 +78,7 @@ class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
// If FASED bridge is attached, loadmem widget is present // If FASED bridge is attached, loadmem widget is present
val hasMainMemory = th.chipParameters(th.p(MultiChipIdx))(ExtMem).isDefined val hasMainMemory = th.chipParameters(th.p(MultiChipIdx))(ExtMem).isDefined
val mainMemoryName = Option.when(hasMainMemory)(MainMemoryConsts.globalName(th.p(MultiChipIdx))) val mainMemoryName = Option.when(hasMainMemory)(MainMemoryConsts.globalName(th.p(MultiChipIdx)))
TSIBridge(th.harnessBinderClock, ram.module.io.tsi, mainMemoryName, th.harnessBinderReset.asBool)(th.p) TSIBridge(th.harnessBinderClock, ram.module.io.tsi.get, mainMemoryName, th.harnessBinderReset.asBool)(th.p)
} }
}) })

9
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -129,8 +129,7 @@ class WithFireSimHighPerfClocking extends Config(
// 1 GHz matches the FASED default, using some other frequency will require // 1 GHz matches the FASED default, using some other frequency will require
// runnings the FASED runtime configuration generator to generate faithful DDR3 timing values. // runnings the FASED runtime configuration generator to generate faithful DDR3 timing values.
new chipyard.config.WithMemoryBusFrequency(1000.0) ++ new chipyard.config.WithMemoryBusFrequency(1000.0) ++
new chipyard.config.WithAsynchrousMemoryBusCrossing ++ new chipyard.config.WithAsynchrousMemoryBusCrossing
new testchipip.WithAsynchronousSerialSlaveCrossing
) )
// Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz // Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz
@@ -192,7 +191,6 @@ class WithFireSimTestChipConfigTweaks extends Config(
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
new WithFireSimDesignTweaks new WithFireSimDesignTweaks
) )
@@ -250,7 +248,10 @@ class FireSimSmallSystemConfig extends Config(
new WithoutClockGating ++ new WithoutClockGating ++
new WithoutTLMonitors ++ new WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
new testchipip.WithDefaultSerialTL ++ new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams(
client = Some(testchipip.SerialTLClientParams(idBits = 4)),
width = 32
))) ++
new testchipip.WithBlockDevice ++ new testchipip.WithBlockDevice ++
new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++ new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++ new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++