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Update firechip for new testchipip

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This commit is contained in:
Jerry Zhao
2023-10-24 18:42:27 -07:00
parent 68f7c90938
commit d83f395738
2 changed files with 7 additions and 6 deletions
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9
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -129,8 +129,7 @@ class WithFireSimHighPerfClocking extends Config(
// 1 GHz matches the FASED default, using some other frequency will require
// runnings the FASED runtime configuration generator to generate faithful DDR3 timing values.
new chipyard.config.WithMemoryBusFrequency(1000.0) ++
new chipyard.config.WithAsynchrousMemoryBusCrossing ++
new testchipip.WithAsynchronousSerialSlaveCrossing
new chipyard.config.WithAsynchrousMemoryBusCrossing
)
// Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz
@@ -192,7 +191,6 @@ class WithFireSimTestChipConfigTweaks extends Config(
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
new WithFireSimDesignTweaks
)
@@ -250,7 +248,10 @@ class FireSimSmallSystemConfig extends Config(
new WithoutClockGating ++
new WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
new testchipip.WithDefaultSerialTL ++
new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams(
client = Some(testchipip.SerialTLClientParams(idBits = 4)),
width = 32
))) ++
new testchipip.WithBlockDevice ++
new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++