Switch to default generating FSDB
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@@ -152,7 +152,7 @@ Simulation with VCS is supported, and can be run at the RTL- or gate-level (post
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Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` make targets, respectively.
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Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` make targets, respectively.
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Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD (or FSDB if the ``USE_FSDB`` flag is set) and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets.
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Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + FSDB (or VPD if the ``USE_VPD`` flag is set) and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets.
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Power/Rail Analysis
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Power/Rail Analysis
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^^^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^^^
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@@ -156,7 +156,7 @@ Simulation with VCS is supported, and can be run at the RTL- or gate-level (post
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Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` make targets, respectively.
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Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` make targets, respectively.
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Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD (or FSDB if the ``USE_FSDB`` flag is set) and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets.
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Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + FSDB (or VPD if the ``USE_VPD`` flag is set) and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets.
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Power/Rail Analysis
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Power/Rail Analysis
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^^^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^^^
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8
vcs.mk
8
vcs.mk
@@ -1,10 +1,10 @@
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HELP_COMPILATION_VARIABLES += \
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HELP_COMPILATION_VARIABLES += \
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" USE_FSDB = set to '1' to build VCS simulator to emit FSDB instead of VPD."
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" USE_VPD = set to '1' to build VCS simulator to emit VPD instead of FSDB."
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HELP_SIMULATION_VARIABLES += \
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HELP_SIMULATION_VARIABLES += \
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" USE_FSDB = set to '1' to run VCS simulator emitting FSDB instead of VPD."
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" USE_VPD = set to '1' to run VCS simulator emitting VPD instead of FSDB."
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ifdef USE_FSDB
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ifndef USE_VPD
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WAVEFORM_FLAG=+fsdbfile=$(sim_out_name).fsdb
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WAVEFORM_FLAG=+fsdbfile=$(sim_out_name).fsdb
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else
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else
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WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd
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WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd
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@@ -66,6 +66,6 @@ PREPROC_DEFINES = \
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+define+RANDOMIZE_GARBAGE_ASSIGN \
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+define+RANDOMIZE_GARBAGE_ASSIGN \
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+define+RANDOMIZE_INVALID_ASSIGN
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+define+RANDOMIZE_INVALID_ASSIGN
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ifdef USE_FSDB
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ifndef USE_VPD
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PREPROC_DEFINES += +define+FSDB
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PREPROC_DEFINES += +define+FSDB
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endif
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endif
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@@ -177,7 +177,7 @@ $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_commo
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echo " saif.mode: 'time'" >> $@
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echo " saif.mode: 'time'" >> $@
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echo " saif.start_time: '0ns'" >> $@
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echo " saif.start_time: '0ns'" >> $@
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echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
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echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
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ifdef USE_FSDB
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ifndef USE_VPD
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echo " options:" >> $@
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echo " options:" >> $@
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echo ' - "-kdb"' >> $@
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echo ' - "-kdb"' >> $@
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echo " options_meta: 'append'" >> $@
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echo " options_meta: 'append'" >> $@
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@@ -202,7 +202,7 @@ $(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_fi
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echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@
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echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@
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ifneq ($(BINARY), )
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ifneq ($(BINARY), )
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echo " waveforms: [" >> $@
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echo " waveforms: [" >> $@
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ifdef USE_FSDB
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ifndef USE_VPD
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echo " '$(sim_out_name).fsdb'" >> $@
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echo " '$(sim_out_name).fsdb'" >> $@
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else
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else
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echo " '$(sim_out_name).vpd'" >> $@
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echo " '$(sim_out_name).vpd'" >> $@
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