From d82e7dbed5d46acce92e029d925875ebe8eaddbf Mon Sep 17 00:00:00 2001
From: Abraham Gonzalez <abe.j.gonza@gmail.com>
Date: Tue, 18 Aug 2020 10:40:45 -0700
Subject: [PATCH] Cleanup more

---
 docs/Simulation/Software-RTL-Simulation.rst | 28 +++++++++++++++++++++
 sims/vcs/Makefile                           |  9 +------
 variables.mk                                |  6 ++---
 3 files changed, 32 insertions(+), 11 deletions(-)

diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst
index ca852d36..9219f5a3 100644
--- a/docs/Simulation/Software-RTL-Simulation.rst
+++ b/docs/Simulation/Software-RTL-Simulation.rst
@@ -61,6 +61,11 @@ For instance, to run one of the riscv-tools assembly tests.
 
 .. Note:: In a VCS simulator, the simulator name will be ``simv-chipyard-RocketConfig`` instead of ``simulator-chipyard-RocketConfig``.
 
+The makefiles have a ``run-binary`` rule that simplifies running the simulation executable. It adds many of the common command line options for you and redirects the output to a file.
+
+.. code-block:: shell
+    make run-binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
+
 Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``.
 For example:
 
@@ -141,6 +146,29 @@ All ``make`` targets that can be applied to the default example, can also be app
 Finally, in the ``generated-src/<...>-<package>-<config>/`` directory resides all of the collateral and Verilog source files for the build/simulation.
 Specifically, the SoC top-level (``TOP``) Verilog file is denoted with ``*.top.v`` while the ``TestHarness`` file is denoted with ``*.harness.v``.
 
+Fast Memory Loading
+-------------------
+
+The simulator loads the program binary over a simulated serial line. This can be quite slow if there is a lot of static data, so the simulator also allows data to be loaded from a file directly into the DRAM model.
+
+.. code-block:: shell
+
+    make run-binary BINARY=test.riscv LOADMEM=testdata.hex LOADMEM_ADDR=81000000
+
+The ``.hex`` file should be a text file with a hexadecimal number on each line.
+
+.. code-block:: text
+
+    deadbeef
+    0123
+
+Each line uses little-endian order, so this file would produce the bytes "ef be ad de 01 23". ``LOADMEM_ADDR`` specifies which address in memory (in hexadecimal) to write the first byte to. The default is 0x81000000.
+
+A special target that facilitates automatically generating a hex file for an entire elf RISC-V exectuable and then running the simulator with the appropriate flags is also available.
+
+.. code-block:: shell
+
+    make run-binary-hex BINARY=test.riscv
 
 Generating Waveforms
 -----------------------
diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile
index 46b3a267..766350ff 100644
--- a/sims/vcs/Makefile
+++ b/sims/vcs/Makefile
@@ -25,10 +25,7 @@ sim_prefix = simv
 sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
 sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
 
-PERMISSIVE_ON=+permissive
-PERMISSIVE_OFF=+permissive-off
-
-WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd
+include $(base_dir)/vcs.mk
 
 .PHONY: default debug
 default: $(sim)
@@ -138,10 +135,6 @@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
 $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
 
-$(output_dir)/none.vpd: $(sim_debug)
-	mkdir -p $(output_dir)
-	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) none </dev/null 2> >(spike-dasm > $(output_dir)/none.out) | tee $(output_dir)/none.log)
-
 #########################################################################################
 # general cleanup rules
 #########################################################################################
diff --git a/variables.mk b/variables.mk
index e41648d4..e347ccf0 100644
--- a/variables.mk
+++ b/variables.mk
@@ -162,15 +162,15 @@ override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP
 # 1) the sed removes a leading {file:<path>} that sometimes needs to be
 #    provided to SBT when a project but not for bloop.
 # 2) Generally, one could could pass '--' to indicate all remaining arguments are
-#       destined for the scala Main, however a bug in Bloop's argument parsing causes the
+#    destined for the scala Main, however a bug in Bloop's argument parsing causes the
 #    --nailgun-port argument to be lost in this case. Workaround this by prefixing
 #    every main-destined argument with "--args"
 define run_scala_main
-       cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2)  $(addprefix --args ,$3)
+	cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2)  $(addprefix --args ,$3)
 endef
 else
 define run_scala_main
-       cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)"
+	cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)"
 endef
 endif