Merge remote-tracking branch 'origin/dev' into firesim-multiclock

[ci skip]

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -2,6 +2,7 @@ package firesim.firesim
 
 import java.io.File
 
+import chisel3._
 import chisel3.util.{log2Up}
 import freechips.rocketchip.config.{Parameters, Config}
 import freechips.rocketchip.groundtest.TraceGenParams
@@ -12,17 +13,21 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink.BootROMParams
 import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
 import freechips.rocketchip.diplomacy.{RationalCrossing}
+import freechips.rocketchip.diplomacy.LazyModule
 import boom.common.{BoomTilesKey, BoomCrossingKey}
-import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey}
+import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import scala.math.{min, max}
 import tracegen.TraceGenKey
 import icenet._
+import ariane.ArianeTilesKey
+import testchipip.WithRingSystemBus
 
 import firesim.bridges._
-import firesim.util.{WithNumNodes, FireSimClockKey, FireSimClockParameters}
+import midas.widgets.{RationalClock}
 import firesim.configs._
-import midas.widgets.RationalClock
+import chipyard.{BuildTop}
+import chipyard.config.ConfigValName._
 
 class WithBootROM extends Config((site, here, up) => {
   case BootROMParams => {
@@ -42,312 +47,6 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) =>
   case PeripheryBusKey => up(PeripheryBusKey).copy(frequency=freq)
 })
 
-class WithUARTKey extends Config((site, here, up) => {
-  case PeripheryUARTKey => List(UARTParams(
-     address = BigInt(0x54000000L),
-     nTxEntries = 256,
-     nRxEntries = 256))
-})
-
-class WithSerial extends Config((site, here, up) => {
-  case SerialKey => true
-})
-
-class WithBlockDevice extends Config(new testchipip.WithBlockDevice)
-
-class WithNICKey extends Config((site, here, up) => {
-  case NICKey => Some(NICConfig(
-    inBufFlits = 8192,
-    ctrlQueueDepth = 64,
-    checksumOffload = true))
-})
-
-class WithRocketL2TLBs(entries: Int) extends Config((site, here, up) => {
-  case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
-    core = tile.core.copy(
-      nL2TLBEntries = entries
-    )
-  ))
-})
-
-class WithPerfCounters extends Config((site, here, up) => {
-  case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
-    core = tile.core.copy(nPerfCounters = 29)
-  ))
-})
-
-class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => {
-  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(
-    core = tile.core.copy(nL2TLBEntries = entries)
-  ))
-})
-
-class WithBoomEnableTrace extends Config((site, here, up) => {
-  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
-})
-
-// Disables clock-gating; doesn't play nice with our FAME-1 pass
-class WithoutClockGating extends Config((site, here, up) => {
-  case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
-})
-
-// Testing configurations
-// This enables printfs used in testing
-class WithScalaTestFeatures extends Config((site, here, up) => {
-    case PrintTracePort => true
-})
-
-// FASED Config Aliases. This to enable config generation via "_" concatenation
-// which requires that all config classes be defined in the same package
-class DDR3FRFCFS extends FRFCFS16GBQuadRank
-class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB
-
-// L2 Config Aliases. For use with "_" concatenation
-class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache
-
-/*******************************************************************************
-* Full TARGET_CONFIG configurations. These set parameters of the target being
-* simulated.
-*
-* In general, if you're adding or removing features from any of these, you
-* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager
-* will store this name as part of the tags for the AGFI, so that later you can
-* reconstruct what is in a particular AGFI. These tags are also used to
-* determine which driver to build.
-*******************************************************************************/
-class FireSimRocketChipConfig extends Config(
-  new WithBootROM ++
-  new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
-  new WithExtMemSize(0x400000000L) ++ // 16GB
-  new WithoutTLMonitors ++
-  new WithUARTKey ++
-  new WithNICKey ++
-  new WithSerial ++
-  new WithBlockDevice ++
-  new WithRocketL2TLBs(1024) ++
-  new WithPerfCounters ++
-  new WithoutClockGating ++
-  new WithDefaultMemModel ++
-  new WithDefaultFireSimBridges ++
-  new freechips.rocketchip.system.DefaultConfig)
-
-class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => {
-  case RocketTilesKey => List.tabulate(n)(i => up(RocketTilesKey).head.copy(hartId = i))
-})
-
-// single core config
-class FireSimRocketChipSingleCoreConfig extends Config(new FireSimRocketChipConfig)
-
-// dual core config
-class FireSimRocketChipDualCoreConfig extends Config(
-  new WithNDuplicatedRocketCores(2) ++
-  new FireSimRocketChipSingleCoreConfig)
-
-// quad core config
-class FireSimRocketChipQuadCoreConfig extends Config(
-  new WithNDuplicatedRocketCores(4) ++
-  new FireSimRocketChipSingleCoreConfig)
-
-// hexa core config
-class FireSimRocketChipHexaCoreConfig extends Config(
-  new WithNDuplicatedRocketCores(6) ++
-  new FireSimRocketChipSingleCoreConfig)
-
-// octa core config
-class FireSimRocketChipOctaCoreConfig extends Config(
-  new WithNDuplicatedRocketCores(8) ++
-  new FireSimRocketChipSingleCoreConfig)
-
-// SHA-3 accelerator config
-class FireSimRocketChipSha3L2Config extends Config(
-  new WithInclusiveCache ++
-  new sha3.WithSha3Accel ++
-  new WithNBigCores(1) ++
-  new FireSimRocketChipConfig)
-
-// SHA-3 accelerator config with synth printfs enabled
-class FireSimRocketChipSha3L2PrintfConfig extends Config(
-  new WithInclusiveCache ++
-  new sha3.WithSha3Printf ++ 
-  new sha3.WithSha3Accel ++
-  new WithNBigCores(1) ++
-  new FireSimRocketChipConfig)
-
-class FireSimBoomConfig extends Config(
-  new WithBootROM ++
-  new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
-  new WithExtMemSize(0x400000000L) ++ // 16GB
-  new WithoutTLMonitors ++
-  new WithUARTKey ++
-  new WithNICKey ++
-  new WithSerial ++
-  new WithBlockDevice ++
-  new WithBoomEnableTrace ++
-  new WithBoomL2TLBs(1024) ++
-  new WithoutClockGating ++
-  new WithDefaultMemModel ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.WithNBoomCores(1) ++
-  new WithDefaultFireSimBridges ++
-  new freechips.rocketchip.system.BaseConfig
-)
-
-// A safer implementation than the one in BOOM in that it
-// duplicates whatever BOOMTileKey.head is present N times. This prevents
-// accidentally (and silently) blowing away configurations that may change the
-// tile in the "up" view
-class WithNDuplicatedBoomCores(n: Int) extends Config((site, here, up) => {
-  case BoomTilesKey => List.tabulate(n)(i => up(BoomTilesKey).head.copy(hartId = i))
-  case MaxHartIdBits => log2Up(site(BoomTilesKey).size)
-})
-
-class FireSimBoomDualCoreConfig extends Config(
-  new WithNDuplicatedBoomCores(2) ++
-  new FireSimBoomConfig)
-
-class FireSimBoomQuadCoreConfig extends Config(
-  new WithNDuplicatedBoomCores(4) ++
-  new FireSimBoomConfig)
-
-//**********************************************************************************
-//* Heterogeneous Configurations
-//*********************************************************************************/
-
-// dual core config (rocket + small boom)
-class FireSimRocketBoomConfig extends Config(
-  new WithBoomL2TLBs(1024) ++ // reset l2 tlb amt ("WithSmallBooms" overrides it)
-  new boom.common.WithRenumberHarts ++ // fix hart numbering
-  new boom.common.WithSmallBooms ++ // change single BOOM to small
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add a "big" rocket core
-  new FireSimBoomConfig
-)
-
-//**********************************************************************************
-//* Gemmini Configurations
-//*********************************************************************************/
-
-// Gemmini systolic accelerator default config
-class FireSimRocketChipGemminiL2Config extends Config(
-  new WithInclusiveCache ++
-  new gemmini.DefaultGemminiConfig ++
-  new WithNBigCores(1) ++
-  new FireSimRocketChipConfig)
-
-
-//**********************************************************************************
-//* Supernode Configurations
-//*********************************************************************************/
-
-class SupernodeFireSimRocketChipConfig extends Config(
-  new WithNumNodes(4) ++
-  new WithExtMemSize(0x200000000L) ++ // 8GB
-  new FireSimRocketChipConfig)
-
-class SupernodeFireSimRocketChipSingleCoreConfig extends Config(
-  new WithNumNodes(4) ++
-  new WithExtMemSize(0x200000000L) ++ // 8GB
-  new FireSimRocketChipSingleCoreConfig)
-
-class SupernodeSixNodeFireSimRocketChipSingleCoreConfig extends Config(
-  new WithNumNodes(6) ++
-  new WithExtMemSize(0x40000000L) ++ // 1GB
-  new FireSimRocketChipSingleCoreConfig)
-
-class SupernodeEightNodeFireSimRocketChipSingleCoreConfig extends Config(
-  new WithNumNodes(8) ++
-  new WithExtMemSize(0x40000000L) ++ // 1GB
-  new FireSimRocketChipSingleCoreConfig)
-
-class SupernodeFireSimRocketChipDualCoreConfig extends Config(
-  new WithNumNodes(4) ++
-  new WithExtMemSize(0x200000000L) ++ // 8GB
-  new FireSimRocketChipDualCoreConfig)
-
-class SupernodeFireSimRocketChipQuadCoreConfig extends Config(
-  new WithNumNodes(4) ++
-  new WithExtMemSize(0x200000000L) ++ // 8GB
-  new FireSimRocketChipQuadCoreConfig)
-
-class SupernodeFireSimRocketChipHexaCoreConfig extends Config(
-  new WithNumNodes(4) ++
-  new WithExtMemSize(0x200000000L) ++ // 8GB
-  new FireSimRocketChipHexaCoreConfig)
-
-class SupernodeFireSimRocketChipOctaCoreConfig extends Config(
-  new WithNumNodes(4) ++
-  new WithExtMemSize(0x200000000L) ++ // 8GB
-  new FireSimRocketChipOctaCoreConfig)
-
-class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
-    extends Config((site, here, up) => {
-  case TraceGenKey => params.map { dcp => TraceGenParams(
-    dcache = Some(dcp),
-    wordBits = site(XLen),
-    addrBits = 48,
-    addrBag = {
-      val nSets = dcp.nSets
-      val nWays = dcp.nWays
-      val blockOffset = site(SystemBusKey).blockOffset
-      val nBeats = min(2, site(SystemBusKey).blockBeats)
-      val beatBytes = site(SystemBusKey).beatBytes
-      List.tabulate(2 * nWays) { i =>
-        Seq.tabulate(nBeats) { j =>
-          BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
-        }
-      }.flatten
-    },
-    maxRequests = nReqs,
-    memStart = site(ExtMem).get.master.base,
-    numGens = params.size)
-  }
-  case MaxHartIdBits => log2Up(params.size)
-})
-
-class FireSimTraceGenConfig extends Config(
-  new WithTraceGen(
-    List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
-  new WithTraceGenBridge ++
-  new FireSimRocketChipConfig)
-
-class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
-    extends Config((site, here, up) => {
-  case TraceGenKey => params.map { dcp => TraceGenParams(
-    dcache = Some(dcp),
-    wordBits = site(XLen),
-    addrBits = 48,
-    addrBag = {
-      val sbp = site(SystemBusKey)
-      val l2p = site(InclusiveCacheKey)
-      val nSets = max(l2p.sets, dcp.nSets)
-      val nWays = max(l2p.ways, dcp.nWays)
-      val nBanks = site(BankedL2Key).nBanks
-      val blockOffset = sbp.blockOffset
-      val nBeats = min(2, sbp.blockBeats)
-      val beatBytes = sbp.beatBytes
-      List.tabulate(2 * nWays) { i =>
-        Seq.tabulate(nBeats) { j =>
-          BigInt((j * beatBytes) + ((i * nSets * nBanks) << blockOffset))
-        }
-      }.flatten
-    },
-    maxRequests = nReqs,
-    memStart = site(ExtMem).get.master.base,
-    numGens = params.size)
-  }
-  case MaxHartIdBits => log2Up(params.size)
-})
-
-class FireSimTraceGenL2Config extends Config(
-  new WithL2TraceGen(
-    List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
-  new WithInclusiveCache(
-    nBanks = 4,
-    capacityKB = 1024,
-    outerLatencyCycles = 50) ++
-  new WithTraceGenBridge ++
-  new FireSimRocketChipConfig)
-
-
 class WithRationalTiles(multiplier: Int, divisor: Int) extends Config((site, here, up) => {
   case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor)))
   case RocketCrossingKey => up(RocketCrossingKey, site) map { r =>
@@ -360,15 +59,147 @@ class WithRationalTiles(multiplier: Int, divisor: Int) extends Config((site, her
 
 class HalfRateUncore extends WithRationalTiles(2,1)
 
-// Eagle X Mock Configs
-class EagleMockConfig(numCores: Int) extends Config(
-  new WithBootROM ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nBanks = 16, capacityKB = 8192) ++
-  new hwacha.DefaultHwachaConfig ++                        // use Hwacha vector accelerator
-  new WithNBigCores(numCores) ++
-  new FireSimRocketChipConfig)
 
-class EX20C extends EagleMockConfig(20)
-class EX16C extends EagleMockConfig(16)
-class EX12C extends EagleMockConfig(12)
-class EX8C extends EagleMockConfig(8)
+class WithPerfCounters extends Config((site, here, up) => {
+  case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
+    core = tile.core.copy(nPerfCounters = 29)
+  ))
+})
+
+
+// Disables clock-gating; doesn't play nice with our FAME-1 pass
+class WithoutClockGating extends Config((site, here, up) => {
+  case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
+})
+
+// Testing configurations
+// This enables printfs used in testing
+class WithScalaTestFeatures extends Config((site, here, up) => {
+  case TracePortKey => up(TracePortKey, site).map(_.copy(print = true))
+})
+
+
+// FASED Config Aliases. This to enable config generation via "_" concatenation
+// which requires that all config classes be defined in the same package
+class DDR3FRFCFS extends FRFCFS16GBQuadRank
+class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB
+
+class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64)
+
+
+
+// Enables tracing on all cores
+class WithTraceIO extends Config((site, here, up) => {
+  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
+  case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true))
+  case TracePortKey => Some(TracePortParams())
+})
+
+
+// Tweaks that are generally applied to all firesim configs
+class WithFireSimConfigTweaks extends Config(
+  // Required*: When using FireSim-as-top to provide a correct path to the target bootrom source
+  new WithBootROM ++
+  // Optional*: Removing this will require target-software changes to properly capture UART output
+  new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
+  // Required: Existing FAME-1 transform cannot handle black-box clock gates
+  new WithoutClockGating ++
+  // Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix)
+  new WithoutTLMonitors ++
+  // Optional: Adds IO to attach tracerV bridges
+  new WithTraceIO ++
+  // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1)
+  new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++
+  // Required: Adds IO to attach SerialBridge. The SerialBridges is responsible
+  // for signalling simulation termination under simulation success. This fragment can
+  // be removed if you supply an auxiliary bridge that signals simulation termination
+  new testchipip.WithTSI ++
+  // Optional: Removing this will require using an initramfs under linux
+  new testchipip.WithBlockDevice ++
+  // Required*:
+  new chipyard.config.WithUART
+)
+
+/*******************************************************************************
+* Full TARGET_CONFIG configurations. These set parameters of the target being
+* simulated.
+*
+* In general, if you're adding or removing features from any of these, you
+* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager
+* will store this name as part of the tags for the AGFI, so that later you can
+* reconstruct what is in a particular AGFI. These tags are also used to
+* determine which driver to build.
+ *******************************************************************************/
+
+//*****************************************************************
+// Rocket configs, base off chipyard's RocketConfig
+//*****************************************************************
+// DOC include start: firesimconfig
+class FireSimRocketConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.RocketConfig)
+// DOC include end: firesimconfig
+
+class FireSimQuadRocketConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.QuadRocketConfig)
+
+
+//*****************************************************************
+// Boom config, base off chipyard's LargeBoomConfig
+//*****************************************************************
+class FireSimLargeBoomConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.LargeBoomConfig)
+
+
+//********************************************************************
+// Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig
+//********************************************************************
+class FireSimLargeBoomAndRocketConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.LargeBoomAndRocketConfig)
+
+//******************************************************************
+// Gemmini NN accel config, base off chipyard's GemminiRocketConfig
+//******************************************************************
+class FireSimGemminiRocketConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.GemminiRocketConfig)
+
+//******************************************************************
+// Configuration with Ring topology SystemBus
+//******************************************************************
+class FireSimRingSystemBusRocketConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.RingSystemBusRocketConfig)
+
+//**********************************************************************************
+// Supernode Configurations, base off chipyard's RocketConfig
+//**********************************************************************************
+class SupernodeFireSimRocketConfig extends Config(
+  new WithNumNodes(4) ++
+  new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 8L) ++ // 8 GB
+  new FireSimRocketConfig)
+
+//**********************************************************************************
+//* Ariane Configurations
+//*********************************************************************************/
+
+class FireSimArianeConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.ArianeConfig)