Merge remote-tracking branch 'origin/dev' into firesim-multiclock
[ci skip]
This commit is contained in:
David Biancolin
@@ -3,53 +3,53 @@
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package firesim.firesim
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import chisel3._
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import chisel3.experimental.annotate
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import freechips.rocketchip.config.{Field, Config}
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import freechips.rocketchip.config.{Field, Config, Parameters}
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import freechips.rocketchip.diplomacy.{LazyModule}
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import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
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import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp}
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import freechips.rocketchip.tile.{RocketTile}
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import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
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import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp}
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import icenet.HasPeripheryIceNICModuleImpValidOnly
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import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp, CanHaveTraceIOModuleImp}
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import icenet.CanHavePeripheryIceNICModuleImp
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import junctions.{NastiKey, NastiParameters}
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import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig}
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import midas.targetutils.{MemModelAnnotation}
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import firesim.bridges._
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import firesim.configs.MemModelKey
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import firesim.util.RegisterBridgeBinder
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import tracegen.HasTraceGenTilesModuleImp
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import ariane.ArianeTile
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class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp =>
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target.debug.foreach(_.clockeddmi.foreach({ cdmi =>
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cdmi.dmi.req.valid := false.B
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cdmi.dmi.req.bits := DontCare
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cdmi.dmi.resp.ready := false.B
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cdmi.dmiClock := false.B.asClock
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cdmi.dmiReset := false.B
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}))
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Seq()
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import boom.common.{BoomTile}
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import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder}
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import chipyard.HasChipyardTilesModuleImp
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class WithSerialBridge extends OverrideIOBinder({
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(c, r, s, target: CanHavePeripherySerialModuleImp) =>
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target.serial.map(s => SerialBridge(target.clock, s)(target.p)).toSeq
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})
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class WithSerialBridge extends RegisterBridgeBinder({
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case target: CanHavePeripherySerialModuleImp => Seq(SerialBridge(target.clock, target.serial.get)(target.p))
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class WithNICBridge extends OverrideIOBinder({
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(c, r, s, target: CanHavePeripheryIceNICModuleImp) =>
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target.net.map(n => NICBridge(target.clock, n)(target.p)).toSeq
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})
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class WithNICBridge extends RegisterBridgeBinder({
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case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.clock, target.net)(target.p))
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class WithUARTBridge extends OverrideIOBinder({
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(c, r, s, target: HasPeripheryUARTModuleImp) =>
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target.uart.map(u => UARTBridge(target.clock, u)(target.p)).toSeq
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})
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class WithUARTBridge extends RegisterBridgeBinder({
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case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(target.clock, u)(target.p))
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class WithBlockDeviceBridge extends OverrideIOBinder({
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(c, r, s, target: CanHavePeripheryBlockDeviceModuleImp) =>
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target.bdev.map(b => BlockDevBridge(target.clock, b, target.reset.toBool)(target.p)).toSeq
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})
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class WithBlockDeviceBridge extends RegisterBridgeBinder({
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case target: CanHavePeripheryBlockDeviceModuleImp =>
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Seq(BlockDevBridge(target.clock, target.bdev.get, target.reset.toBool)(target.p))
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})
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class WithFASEDBridge extends RegisterBridgeBinder({
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case t: CanHaveMasterAXI4MemPortModuleImp =>
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class WithFASEDBridge extends OverrideIOBinder({
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(c, r, s, t: CanHaveMasterAXI4MemPortModuleImp) => {
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implicit val p = t.p
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(t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) =>
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(io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
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@@ -60,22 +60,58 @@ class WithFASEDBridge extends RegisterBridgeBinder({
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CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge))))
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})
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}).toSeq
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}
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})
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class WithTracerVBridge extends Config((_,_,_) => { case InstantiateTracerVBridges => true })
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class WithTracerVBridge extends OverrideIOBinder({
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(c, r, s, target: CanHaveTraceIOModuleImp) => target.traceIO match {
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case Some(t) => t.traces.map(tileTrace => TracerVBridge(tileTrace)(target.p))
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case None => Nil
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}
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})
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class WithTraceGenBridge extends RegisterBridgeBinder({
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case target: HasTraceGenTilesModuleImp =>
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class WithTraceGenBridge extends OverrideIOBinder({
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(c, r, s, target: HasTraceGenTilesModuleImp) =>
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Seq(GroundTestBridge(target.clock, target.success)(target.p))
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})
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class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
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(c, r, s, target: HasChipyardTilesModuleImp) => {
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target.outer.tiles.map {
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case r: RocketTile => {
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annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
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r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
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}
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case b: BoomTile => {
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val core = b.module.core
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core.iregfile match {
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case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
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case _ => Nil
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}
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if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
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case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
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case _ => Nil
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}
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}
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case a: ArianeTile => Nil
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}
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Nil
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}
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})
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// Shorthand to register all of the provided bridges above
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class WithDefaultFireSimBridges extends Config(
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new WithTiedOffDebug ++
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new chipyard.iobinders.WithGPIOTiedOff ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new WithSerialBridge ++
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new WithNICBridge ++
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new WithUARTBridge ++
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new WithBlockDeviceBridge ++
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new WithFASEDBridge ++
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new WithFireSimMultiCycleRegfile ++
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new WithTracerVBridge
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)
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64
generators/firechip/src/main/scala/FireSim.scala
Normal file
64
generators/firechip/src/main/scala/FireSim.scala
Normal file
@@ -0,0 +1,64 @@
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//See LICENSE for license details.
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package firesim.firesim
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import chisel3._
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import freechips.rocketchip.config.{Field, Config, Parameters}
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import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
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import freechips.rocketchip.subsystem.{HasTiles}
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import freechips.rocketchip.util.{ResetCatchAndSync}
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import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock}
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import chipyard.{BuildTop}
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import chipyard.iobinders.{IOBinders}
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// Determines the number of times to instantiate the DUT in the harness.
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// Subsumes legacy supernode support
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case object NumNodes extends Field[Int](1)
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class WithNumNodes(n: Int) extends Config((pname, site, here) => {
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case NumNodes => n
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})
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case class FireSimClockParameters(additionalClocks: Seq[RationalClock]) {
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def numClocks(): Int = additionalClocks.size + 1
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}
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case object FireSimClockKey extends Field[FireSimClockParameters](FireSimClockParameters(Seq()))
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trait HasAdditionalClocks extends LazyModuleImp {
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val clocks = IO(Vec(p(FireSimClockKey).numClocks, Input(Clock())))
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}
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trait HasFireSimClockingImp extends HasAdditionalClocks {
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val outer: HasTiles
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val (tileClock, tileReset) = p(FireSimClockKey).additionalClocks.headOption match {
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case Some(RationalClock(_, numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool))
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case None => (clocks(0), reset)
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}
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outer.tiles.foreach({ case tile =>
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tile.module.clock := tileClock
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tile.module.reset := tileReset
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})
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}
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class FireSim[T <: LazyModule](implicit val p: Parameters) extends RawModule {
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val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*))
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val refClock = clockBridge.io.clocks(0)
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val reset = WireInit(false.B)
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withClockAndReset(refClock, reset) {
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// Instantiate multiple instances of the DUT to implement supernode
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val targets = Seq.fill(p(NumNodes))(p(BuildTop)(p))
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val peekPokeBridge = PeekPokeBridge(refClock, reset)
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// A Seq of partial functions that will instantiate the right bridge only
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// if that Mixin trait is present in the target's class instance
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//
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// Apply each partial function to each DUT instance
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for ((target) <- targets) {
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p(IOBinders).values.map(fn => fn(refClock, reset.asBool, false.B, target))
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}
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targets.collect({ case t: HasAdditionalClocks => t.clocks := clockBridge.io.clocks })
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}
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}
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@@ -20,12 +20,13 @@ import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGenerat
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import scala.util.Try
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import utilities.TestSuiteHelper
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import chipyard.TestSuiteHelper
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trait HasTestSuites {
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def addTestSuites(targetName: String, params: Parameters) {
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TestSuiteHelper.addRocketTestSuites(params)
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TestSuiteHelper.addBoomTestSuites(params)
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TestSuiteHelper.addArianeTestSuites(params)
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TestGeneration.addSuite(FastBlockdevTests)
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TestGeneration.addSuite(SlowBlockdevTests)
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if (!targetName.contains("NoNIC"))
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@@ -61,7 +62,7 @@ object FireSimGenerator extends App with IsFireSimGeneratorLike {
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override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
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lazy val generatorArgs = GeneratorArgs(args)
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lazy val genDir = new File(names.targetDir)
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// The only reason this is not generateFirrtl; generateAnno is that we need to use a different
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// The only reason this is not generateFirrtl; generateAnno is that we need to use a different
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// JsonProtocol to properly write out the annotations. Fix once the generated are unified
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elaborate
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generateTestSuiteMakefrags
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@@ -2,6 +2,7 @@ package firesim.firesim
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import java.io.File
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import chisel3._
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import chisel3.util.{log2Up}
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import freechips.rocketchip.config.{Parameters, Config}
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import freechips.rocketchip.groundtest.TraceGenParams
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@@ -12,17 +13,21 @@ import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.tilelink.BootROMParams
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import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
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import freechips.rocketchip.diplomacy.{RationalCrossing}
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import freechips.rocketchip.diplomacy.LazyModule
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import boom.common.{BoomTilesKey, BoomCrossingKey}
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import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey}
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import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams}
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import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
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import scala.math.{min, max}
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import tracegen.TraceGenKey
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import icenet._
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import ariane.ArianeTilesKey
|
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import testchipip.WithRingSystemBus
|
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import firesim.bridges._
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import firesim.util.{WithNumNodes, FireSimClockKey, FireSimClockParameters}
|
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import midas.widgets.{RationalClock}
|
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import firesim.configs._
|
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import midas.widgets.RationalClock
|
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import chipyard.{BuildTop}
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import chipyard.config.ConfigValName._
|
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|
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class WithBootROM extends Config((site, here, up) => {
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case BootROMParams => {
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@@ -42,312 +47,6 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) =>
|
||||
case PeripheryBusKey => up(PeripheryBusKey).copy(frequency=freq)
|
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})
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class WithUARTKey extends Config((site, here, up) => {
|
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case PeripheryUARTKey => List(UARTParams(
|
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address = BigInt(0x54000000L),
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nTxEntries = 256,
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nRxEntries = 256))
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})
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|
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class WithSerial extends Config((site, here, up) => {
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case SerialKey => true
|
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})
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|
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class WithBlockDevice extends Config(new testchipip.WithBlockDevice)
|
||||
|
||||
class WithNICKey extends Config((site, here, up) => {
|
||||
case NICKey => Some(NICConfig(
|
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inBufFlits = 8192,
|
||||
ctrlQueueDepth = 64,
|
||||
checksumOffload = true))
|
||||
})
|
||||
|
||||
class WithRocketL2TLBs(entries: Int) extends Config((site, here, up) => {
|
||||
case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
|
||||
core = tile.core.copy(
|
||||
nL2TLBEntries = entries
|
||||
)
|
||||
))
|
||||
})
|
||||
|
||||
class WithPerfCounters extends Config((site, here, up) => {
|
||||
case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
|
||||
core = tile.core.copy(nPerfCounters = 29)
|
||||
))
|
||||
})
|
||||
|
||||
class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => {
|
||||
case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(
|
||||
core = tile.core.copy(nL2TLBEntries = entries)
|
||||
))
|
||||
})
|
||||
|
||||
class WithBoomEnableTrace extends Config((site, here, up) => {
|
||||
case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
|
||||
})
|
||||
|
||||
// Disables clock-gating; doesn't play nice with our FAME-1 pass
|
||||
class WithoutClockGating extends Config((site, here, up) => {
|
||||
case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
|
||||
})
|
||||
|
||||
// Testing configurations
|
||||
// This enables printfs used in testing
|
||||
class WithScalaTestFeatures extends Config((site, here, up) => {
|
||||
case PrintTracePort => true
|
||||
})
|
||||
|
||||
// FASED Config Aliases. This to enable config generation via "_" concatenation
|
||||
// which requires that all config classes be defined in the same package
|
||||
class DDR3FRFCFS extends FRFCFS16GBQuadRank
|
||||
class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB
|
||||
|
||||
// L2 Config Aliases. For use with "_" concatenation
|
||||
class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache
|
||||
|
||||
/*******************************************************************************
|
||||
* Full TARGET_CONFIG configurations. These set parameters of the target being
|
||||
* simulated.
|
||||
*
|
||||
* In general, if you're adding or removing features from any of these, you
|
||||
* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager
|
||||
* will store this name as part of the tags for the AGFI, so that later you can
|
||||
* reconstruct what is in a particular AGFI. These tags are also used to
|
||||
* determine which driver to build.
|
||||
*******************************************************************************/
|
||||
class FireSimRocketChipConfig extends Config(
|
||||
new WithBootROM ++
|
||||
new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
|
||||
new WithExtMemSize(0x400000000L) ++ // 16GB
|
||||
new WithoutTLMonitors ++
|
||||
new WithUARTKey ++
|
||||
new WithNICKey ++
|
||||
new WithSerial ++
|
||||
new WithBlockDevice ++
|
||||
new WithRocketL2TLBs(1024) ++
|
||||
new WithPerfCounters ++
|
||||
new WithoutClockGating ++
|
||||
new WithDefaultMemModel ++
|
||||
new WithDefaultFireSimBridges ++
|
||||
new freechips.rocketchip.system.DefaultConfig)
|
||||
|
||||
class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => {
|
||||
case RocketTilesKey => List.tabulate(n)(i => up(RocketTilesKey).head.copy(hartId = i))
|
||||
})
|
||||
|
||||
// single core config
|
||||
class FireSimRocketChipSingleCoreConfig extends Config(new FireSimRocketChipConfig)
|
||||
|
||||
// dual core config
|
||||
class FireSimRocketChipDualCoreConfig extends Config(
|
||||
new WithNDuplicatedRocketCores(2) ++
|
||||
new FireSimRocketChipSingleCoreConfig)
|
||||
|
||||
// quad core config
|
||||
class FireSimRocketChipQuadCoreConfig extends Config(
|
||||
new WithNDuplicatedRocketCores(4) ++
|
||||
new FireSimRocketChipSingleCoreConfig)
|
||||
|
||||
// hexa core config
|
||||
class FireSimRocketChipHexaCoreConfig extends Config(
|
||||
new WithNDuplicatedRocketCores(6) ++
|
||||
new FireSimRocketChipSingleCoreConfig)
|
||||
|
||||
// octa core config
|
||||
class FireSimRocketChipOctaCoreConfig extends Config(
|
||||
new WithNDuplicatedRocketCores(8) ++
|
||||
new FireSimRocketChipSingleCoreConfig)
|
||||
|
||||
// SHA-3 accelerator config
|
||||
class FireSimRocketChipSha3L2Config extends Config(
|
||||
new WithInclusiveCache ++
|
||||
new sha3.WithSha3Accel ++
|
||||
new WithNBigCores(1) ++
|
||||
new FireSimRocketChipConfig)
|
||||
|
||||
// SHA-3 accelerator config with synth printfs enabled
|
||||
class FireSimRocketChipSha3L2PrintfConfig extends Config(
|
||||
new WithInclusiveCache ++
|
||||
new sha3.WithSha3Printf ++
|
||||
new sha3.WithSha3Accel ++
|
||||
new WithNBigCores(1) ++
|
||||
new FireSimRocketChipConfig)
|
||||
|
||||
class FireSimBoomConfig extends Config(
|
||||
new WithBootROM ++
|
||||
new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
|
||||
new WithExtMemSize(0x400000000L) ++ // 16GB
|
||||
new WithoutTLMonitors ++
|
||||
new WithUARTKey ++
|
||||
new WithNICKey ++
|
||||
new WithSerial ++
|
||||
new WithBlockDevice ++
|
||||
new WithBoomEnableTrace ++
|
||||
new WithBoomL2TLBs(1024) ++
|
||||
new WithoutClockGating ++
|
||||
new WithDefaultMemModel ++
|
||||
new boom.common.WithLargeBooms ++
|
||||
new boom.common.WithNBoomCores(1) ++
|
||||
new WithDefaultFireSimBridges ++
|
||||
new freechips.rocketchip.system.BaseConfig
|
||||
)
|
||||
|
||||
// A safer implementation than the one in BOOM in that it
|
||||
// duplicates whatever BOOMTileKey.head is present N times. This prevents
|
||||
// accidentally (and silently) blowing away configurations that may change the
|
||||
// tile in the "up" view
|
||||
class WithNDuplicatedBoomCores(n: Int) extends Config((site, here, up) => {
|
||||
case BoomTilesKey => List.tabulate(n)(i => up(BoomTilesKey).head.copy(hartId = i))
|
||||
case MaxHartIdBits => log2Up(site(BoomTilesKey).size)
|
||||
})
|
||||
|
||||
class FireSimBoomDualCoreConfig extends Config(
|
||||
new WithNDuplicatedBoomCores(2) ++
|
||||
new FireSimBoomConfig)
|
||||
|
||||
class FireSimBoomQuadCoreConfig extends Config(
|
||||
new WithNDuplicatedBoomCores(4) ++
|
||||
new FireSimBoomConfig)
|
||||
|
||||
//**********************************************************************************
|
||||
//* Heterogeneous Configurations
|
||||
//*********************************************************************************/
|
||||
|
||||
// dual core config (rocket + small boom)
|
||||
class FireSimRocketBoomConfig extends Config(
|
||||
new WithBoomL2TLBs(1024) ++ // reset l2 tlb amt ("WithSmallBooms" overrides it)
|
||||
new boom.common.WithRenumberHarts ++ // fix hart numbering
|
||||
new boom.common.WithSmallBooms ++ // change single BOOM to small
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add a "big" rocket core
|
||||
new FireSimBoomConfig
|
||||
)
|
||||
|
||||
//**********************************************************************************
|
||||
//* Gemmini Configurations
|
||||
//*********************************************************************************/
|
||||
|
||||
// Gemmini systolic accelerator default config
|
||||
class FireSimRocketChipGemminiL2Config extends Config(
|
||||
new WithInclusiveCache ++
|
||||
new gemmini.DefaultGemminiConfig ++
|
||||
new WithNBigCores(1) ++
|
||||
new FireSimRocketChipConfig)
|
||||
|
||||
|
||||
//**********************************************************************************
|
||||
//* Supernode Configurations
|
||||
//*********************************************************************************/
|
||||
|
||||
class SupernodeFireSimRocketChipConfig extends Config(
|
||||
new WithNumNodes(4) ++
|
||||
new WithExtMemSize(0x200000000L) ++ // 8GB
|
||||
new FireSimRocketChipConfig)
|
||||
|
||||
class SupernodeFireSimRocketChipSingleCoreConfig extends Config(
|
||||
new WithNumNodes(4) ++
|
||||
new WithExtMemSize(0x200000000L) ++ // 8GB
|
||||
new FireSimRocketChipSingleCoreConfig)
|
||||
|
||||
class SupernodeSixNodeFireSimRocketChipSingleCoreConfig extends Config(
|
||||
new WithNumNodes(6) ++
|
||||
new WithExtMemSize(0x40000000L) ++ // 1GB
|
||||
new FireSimRocketChipSingleCoreConfig)
|
||||
|
||||
class SupernodeEightNodeFireSimRocketChipSingleCoreConfig extends Config(
|
||||
new WithNumNodes(8) ++
|
||||
new WithExtMemSize(0x40000000L) ++ // 1GB
|
||||
new FireSimRocketChipSingleCoreConfig)
|
||||
|
||||
class SupernodeFireSimRocketChipDualCoreConfig extends Config(
|
||||
new WithNumNodes(4) ++
|
||||
new WithExtMemSize(0x200000000L) ++ // 8GB
|
||||
new FireSimRocketChipDualCoreConfig)
|
||||
|
||||
class SupernodeFireSimRocketChipQuadCoreConfig extends Config(
|
||||
new WithNumNodes(4) ++
|
||||
new WithExtMemSize(0x200000000L) ++ // 8GB
|
||||
new FireSimRocketChipQuadCoreConfig)
|
||||
|
||||
class SupernodeFireSimRocketChipHexaCoreConfig extends Config(
|
||||
new WithNumNodes(4) ++
|
||||
new WithExtMemSize(0x200000000L) ++ // 8GB
|
||||
new FireSimRocketChipHexaCoreConfig)
|
||||
|
||||
class SupernodeFireSimRocketChipOctaCoreConfig extends Config(
|
||||
new WithNumNodes(4) ++
|
||||
new WithExtMemSize(0x200000000L) ++ // 8GB
|
||||
new FireSimRocketChipOctaCoreConfig)
|
||||
|
||||
class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
|
||||
extends Config((site, here, up) => {
|
||||
case TraceGenKey => params.map { dcp => TraceGenParams(
|
||||
dcache = Some(dcp),
|
||||
wordBits = site(XLen),
|
||||
addrBits = 48,
|
||||
addrBag = {
|
||||
val nSets = dcp.nSets
|
||||
val nWays = dcp.nWays
|
||||
val blockOffset = site(SystemBusKey).blockOffset
|
||||
val nBeats = min(2, site(SystemBusKey).blockBeats)
|
||||
val beatBytes = site(SystemBusKey).beatBytes
|
||||
List.tabulate(2 * nWays) { i =>
|
||||
Seq.tabulate(nBeats) { j =>
|
||||
BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
|
||||
}
|
||||
}.flatten
|
||||
},
|
||||
maxRequests = nReqs,
|
||||
memStart = site(ExtMem).get.master.base,
|
||||
numGens = params.size)
|
||||
}
|
||||
case MaxHartIdBits => log2Up(params.size)
|
||||
})
|
||||
|
||||
class FireSimTraceGenConfig extends Config(
|
||||
new WithTraceGen(
|
||||
List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
|
||||
new WithTraceGenBridge ++
|
||||
new FireSimRocketChipConfig)
|
||||
|
||||
class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
|
||||
extends Config((site, here, up) => {
|
||||
case TraceGenKey => params.map { dcp => TraceGenParams(
|
||||
dcache = Some(dcp),
|
||||
wordBits = site(XLen),
|
||||
addrBits = 48,
|
||||
addrBag = {
|
||||
val sbp = site(SystemBusKey)
|
||||
val l2p = site(InclusiveCacheKey)
|
||||
val nSets = max(l2p.sets, dcp.nSets)
|
||||
val nWays = max(l2p.ways, dcp.nWays)
|
||||
val nBanks = site(BankedL2Key).nBanks
|
||||
val blockOffset = sbp.blockOffset
|
||||
val nBeats = min(2, sbp.blockBeats)
|
||||
val beatBytes = sbp.beatBytes
|
||||
List.tabulate(2 * nWays) { i =>
|
||||
Seq.tabulate(nBeats) { j =>
|
||||
BigInt((j * beatBytes) + ((i * nSets * nBanks) << blockOffset))
|
||||
}
|
||||
}.flatten
|
||||
},
|
||||
maxRequests = nReqs,
|
||||
memStart = site(ExtMem).get.master.base,
|
||||
numGens = params.size)
|
||||
}
|
||||
case MaxHartIdBits => log2Up(params.size)
|
||||
})
|
||||
|
||||
class FireSimTraceGenL2Config extends Config(
|
||||
new WithL2TraceGen(
|
||||
List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
|
||||
new WithInclusiveCache(
|
||||
nBanks = 4,
|
||||
capacityKB = 1024,
|
||||
outerLatencyCycles = 50) ++
|
||||
new WithTraceGenBridge ++
|
||||
new FireSimRocketChipConfig)
|
||||
|
||||
|
||||
class WithRationalTiles(multiplier: Int, divisor: Int) extends Config((site, here, up) => {
|
||||
case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor)))
|
||||
case RocketCrossingKey => up(RocketCrossingKey, site) map { r =>
|
||||
@@ -360,15 +59,147 @@ class WithRationalTiles(multiplier: Int, divisor: Int) extends Config((site, her
|
||||
|
||||
class HalfRateUncore extends WithRationalTiles(2,1)
|
||||
|
||||
// Eagle X Mock Configs
|
||||
class EagleMockConfig(numCores: Int) extends Config(
|
||||
new WithBootROM ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache(nBanks = 16, capacityKB = 8192) ++
|
||||
new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
|
||||
new WithNBigCores(numCores) ++
|
||||
new FireSimRocketChipConfig)
|
||||
|
||||
class EX20C extends EagleMockConfig(20)
|
||||
class EX16C extends EagleMockConfig(16)
|
||||
class EX12C extends EagleMockConfig(12)
|
||||
class EX8C extends EagleMockConfig(8)
|
||||
class WithPerfCounters extends Config((site, here, up) => {
|
||||
case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
|
||||
core = tile.core.copy(nPerfCounters = 29)
|
||||
))
|
||||
})
|
||||
|
||||
|
||||
// Disables clock-gating; doesn't play nice with our FAME-1 pass
|
||||
class WithoutClockGating extends Config((site, here, up) => {
|
||||
case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
|
||||
})
|
||||
|
||||
// Testing configurations
|
||||
// This enables printfs used in testing
|
||||
class WithScalaTestFeatures extends Config((site, here, up) => {
|
||||
case TracePortKey => up(TracePortKey, site).map(_.copy(print = true))
|
||||
})
|
||||
|
||||
|
||||
// FASED Config Aliases. This to enable config generation via "_" concatenation
|
||||
// which requires that all config classes be defined in the same package
|
||||
class DDR3FRFCFS extends FRFCFS16GBQuadRank
|
||||
class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB
|
||||
|
||||
class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64)
|
||||
|
||||
|
||||
|
||||
// Enables tracing on all cores
|
||||
class WithTraceIO extends Config((site, here, up) => {
|
||||
case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
|
||||
case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true))
|
||||
case TracePortKey => Some(TracePortParams())
|
||||
})
|
||||
|
||||
|
||||
// Tweaks that are generally applied to all firesim configs
|
||||
class WithFireSimConfigTweaks extends Config(
|
||||
// Required*: When using FireSim-as-top to provide a correct path to the target bootrom source
|
||||
new WithBootROM ++
|
||||
// Optional*: Removing this will require target-software changes to properly capture UART output
|
||||
new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
|
||||
// Required: Existing FAME-1 transform cannot handle black-box clock gates
|
||||
new WithoutClockGating ++
|
||||
// Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix)
|
||||
new WithoutTLMonitors ++
|
||||
// Optional: Adds IO to attach tracerV bridges
|
||||
new WithTraceIO ++
|
||||
// Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1)
|
||||
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++
|
||||
// Required: Adds IO to attach SerialBridge. The SerialBridges is responsible
|
||||
// for signalling simulation termination under simulation success. This fragment can
|
||||
// be removed if you supply an auxiliary bridge that signals simulation termination
|
||||
new testchipip.WithTSI ++
|
||||
// Optional: Removing this will require using an initramfs under linux
|
||||
new testchipip.WithBlockDevice ++
|
||||
// Required*:
|
||||
new chipyard.config.WithUART
|
||||
)
|
||||
|
||||
/*******************************************************************************
|
||||
* Full TARGET_CONFIG configurations. These set parameters of the target being
|
||||
* simulated.
|
||||
*
|
||||
* In general, if you're adding or removing features from any of these, you
|
||||
* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager
|
||||
* will store this name as part of the tags for the AGFI, so that later you can
|
||||
* reconstruct what is in a particular AGFI. These tags are also used to
|
||||
* determine which driver to build.
|
||||
*******************************************************************************/
|
||||
|
||||
//*****************************************************************
|
||||
// Rocket configs, base off chipyard's RocketConfig
|
||||
//*****************************************************************
|
||||
// DOC include start: firesimconfig
|
||||
class FireSimRocketConfig extends Config(
|
||||
new WithDefaultFireSimBridges ++
|
||||
new WithDefaultMemModel ++
|
||||
new WithFireSimConfigTweaks ++
|
||||
new chipyard.RocketConfig)
|
||||
// DOC include end: firesimconfig
|
||||
|
||||
class FireSimQuadRocketConfig extends Config(
|
||||
new WithDefaultFireSimBridges ++
|
||||
new WithDefaultMemModel ++
|
||||
new WithFireSimConfigTweaks ++
|
||||
new chipyard.QuadRocketConfig)
|
||||
|
||||
|
||||
//*****************************************************************
|
||||
// Boom config, base off chipyard's LargeBoomConfig
|
||||
//*****************************************************************
|
||||
class FireSimLargeBoomConfig extends Config(
|
||||
new WithDefaultFireSimBridges ++
|
||||
new WithDefaultMemModel ++
|
||||
new WithFireSimConfigTweaks ++
|
||||
new chipyard.LargeBoomConfig)
|
||||
|
||||
|
||||
//********************************************************************
|
||||
// Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig
|
||||
//********************************************************************
|
||||
class FireSimLargeBoomAndRocketConfig extends Config(
|
||||
new WithDefaultFireSimBridges ++
|
||||
new WithDefaultMemModel ++
|
||||
new WithFireSimConfigTweaks ++
|
||||
new chipyard.LargeBoomAndRocketConfig)
|
||||
|
||||
//******************************************************************
|
||||
// Gemmini NN accel config, base off chipyard's GemminiRocketConfig
|
||||
//******************************************************************
|
||||
class FireSimGemminiRocketConfig extends Config(
|
||||
new WithDefaultFireSimBridges ++
|
||||
new WithDefaultMemModel ++
|
||||
new WithFireSimConfigTweaks ++
|
||||
new chipyard.GemminiRocketConfig)
|
||||
|
||||
//******************************************************************
|
||||
// Configuration with Ring topology SystemBus
|
||||
//******************************************************************
|
||||
class FireSimRingSystemBusRocketConfig extends Config(
|
||||
new WithDefaultFireSimBridges ++
|
||||
new WithDefaultMemModel ++
|
||||
new WithFireSimConfigTweaks ++
|
||||
new chipyard.RingSystemBusRocketConfig)
|
||||
|
||||
//**********************************************************************************
|
||||
// Supernode Configurations, base off chipyard's RocketConfig
|
||||
//**********************************************************************************
|
||||
class SupernodeFireSimRocketConfig extends Config(
|
||||
new WithNumNodes(4) ++
|
||||
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 8L) ++ // 8 GB
|
||||
new FireSimRocketConfig)
|
||||
|
||||
//**********************************************************************************
|
||||
//* Ariane Configurations
|
||||
//*********************************************************************************/
|
||||
|
||||
class FireSimArianeConfig extends Config(
|
||||
new WithDefaultFireSimBridges ++
|
||||
new WithDefaultMemModel ++
|
||||
new WithFireSimConfigTweaks ++
|
||||
new chipyard.ArianeConfig)
|
||||
|
||||
@@ -1,92 +0,0 @@
|
||||
package firesim.firesim
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util.Cat
|
||||
import chisel3.experimental.annotate
|
||||
import freechips.rocketchip.config.{Field, Parameters}
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.subsystem._
|
||||
import freechips.rocketchip.amba.axi4._
|
||||
import freechips.rocketchip.util._
|
||||
import freechips.rocketchip.tile.RocketTile
|
||||
import freechips.rocketchip.subsystem._
|
||||
import freechips.rocketchip.rocket.TracedInstruction
|
||||
import firesim.bridges.{TracerVBridge}
|
||||
import firesim.util.{HasAdditionalClocks, FireSimClockKey}
|
||||
|
||||
import midas.targetutils.MemModelAnnotation
|
||||
import midas.widgets.RationalClock
|
||||
|
||||
import boom.common.BoomTile
|
||||
|
||||
/* Wires out tile trace ports to the top; and wraps them in a Bundle that the
|
||||
* TracerV bridge can match on.
|
||||
*/
|
||||
case object PrintTracePort extends Field[Boolean](false)
|
||||
case object InstantiateTracerVBridges extends Field[Boolean](false)
|
||||
|
||||
trait HasTraceIO {
|
||||
this: HasTiles =>
|
||||
val module: HasTraceIOImp
|
||||
|
||||
// Bind all the trace nodes to a BB; we'll use this to generate the IO in the imp
|
||||
val tileTraceNodes = tiles.map({ tile =>
|
||||
val node = BundleBridgeSink[Vec[TracedInstruction]]
|
||||
node := tile.traceNode
|
||||
node
|
||||
})
|
||||
}
|
||||
|
||||
trait HasTraceIOImp extends LazyModuleImp {
|
||||
val outer: HasTraceIO
|
||||
outer.tileTraceNodes.zipWithIndex.foreach({ case (node, idx) =>
|
||||
if (p(InstantiateTracerVBridges)) {
|
||||
val b = TracerVBridge(node.bundle)
|
||||
// Used for verifying the TracerV bridge
|
||||
if (p(PrintTracePort)) {
|
||||
withClockAndReset(node.bundle.head.clock, node.bundle.head.reset) {
|
||||
val traceprint = WireDefault(0.U(512.W))
|
||||
// The reverse is here to match the behavior the Cat used in the bridge
|
||||
traceprint := b.io.traces.reverse.asUInt
|
||||
printf(s"TRACEPORT ${idx}: %x\n", traceprint)
|
||||
}
|
||||
}
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
trait CanHaveMultiCycleRegfileImp {
|
||||
val outer: utilities.HasBoomAndRocketTiles
|
||||
|
||||
outer.tiles.map {
|
||||
case r: RocketTile => {
|
||||
annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
|
||||
r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
|
||||
}
|
||||
case b: BoomTile => {
|
||||
val core = b.module.core
|
||||
core.iregfile match {
|
||||
case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
|
||||
case _ => Nil
|
||||
}
|
||||
if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
|
||||
case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
|
||||
case _ => Nil
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
trait HasFireSimClockingImp extends HasAdditionalClocks {
|
||||
val outer: HasTiles
|
||||
val (tileClock, tileReset) = p(FireSimClockKey).additionalClocks.headOption match {
|
||||
case Some(RationalClock(_, numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool))
|
||||
case None => (clocks(0), reset)
|
||||
}
|
||||
|
||||
outer.tiles.foreach({ case tile =>
|
||||
tile.module.clock := tileClock
|
||||
tile.module.reset := tileReset
|
||||
})
|
||||
}
|
||||
@@ -1,119 +0,0 @@
|
||||
package firesim.firesim
|
||||
|
||||
import chisel3._
|
||||
import freechips.rocketchip._
|
||||
import freechips.rocketchip.subsystem._
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.devices.tilelink._
|
||||
import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.util.{HeterogeneousBag}
|
||||
import freechips.rocketchip.amba.axi4.AXI4Bundle
|
||||
import freechips.rocketchip.config.{Field, Parameters}
|
||||
import freechips.rocketchip.diplomacy.LazyModule
|
||||
import utilities.{Subsystem, SubsystemModuleImp}
|
||||
import icenet._
|
||||
import firesim.util.DefaultFireSimHarness
|
||||
import testchipip._
|
||||
import testchipip.SerialAdapter.SERIAL_IF_WIDTH
|
||||
import tracegen.{HasTraceGenTiles, HasTraceGenTilesModuleImp}
|
||||
import sifive.blocks.devices.uart._
|
||||
import java.io.File
|
||||
|
||||
|
||||
object FireSimValName {
|
||||
implicit val valName = ValName("FireSimHarness")
|
||||
}
|
||||
import FireSimValName._
|
||||
|
||||
/*******************************************************************************
|
||||
* Top level DESIGN configurations. These describe the basic instantiations of
|
||||
* the designs being simulated.
|
||||
*
|
||||
* In general, if you're adding or removing features from any of these, you
|
||||
* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager
|
||||
* will store this name as part of the tags for the AGFI, so that later you can
|
||||
* reconstruct what is in a particular AGFI. These tags are also used to
|
||||
* determine which driver to build.
|
||||
*******************************************************************************/
|
||||
|
||||
class FireSimDUT(implicit p: Parameters) extends Subsystem
|
||||
with HasHierarchicalBusTopology
|
||||
with CanHaveMasterAXI4MemPort
|
||||
with HasPeripheryBootROM
|
||||
with CanHavePeripherySerial
|
||||
with HasPeripheryUART
|
||||
with CanHavePeripheryIceNIC
|
||||
with CanHavePeripheryBlockDevice
|
||||
with HasTraceIO
|
||||
{
|
||||
override lazy val module = new FireSimModuleImp(this)
|
||||
}
|
||||
|
||||
class FireSimModuleImp[+L <: FireSimDUT](l: L) extends SubsystemModuleImp(l)
|
||||
with HasRTCModuleImp
|
||||
with CanHaveMasterAXI4MemPortModuleImp
|
||||
with HasPeripheryBootROMModuleImp
|
||||
with CanHavePeripherySerialModuleImp
|
||||
with HasPeripheryUARTModuleImp
|
||||
with HasPeripheryIceNICModuleImpValidOnly
|
||||
with CanHavePeripheryBlockDeviceModuleImp
|
||||
with HasTraceIOImp
|
||||
with HasFireSimClockingImp
|
||||
with CanHaveMultiCycleRegfileImp
|
||||
|
||||
class FireSim(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT)
|
||||
|
||||
class FireSimNoNICDUT(implicit p: Parameters) extends Subsystem
|
||||
with HasHierarchicalBusTopology
|
||||
with CanHaveMasterAXI4MemPort
|
||||
with HasPeripheryBootROM
|
||||
with CanHavePeripherySerial
|
||||
with HasPeripheryUART
|
||||
with CanHavePeripheryBlockDevice
|
||||
with HasTraceIO
|
||||
{
|
||||
override lazy val module = new FireSimNoNICModuleImp(this)
|
||||
}
|
||||
|
||||
class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModuleImp(l)
|
||||
with HasRTCModuleImp
|
||||
with CanHaveMasterAXI4MemPortModuleImp
|
||||
with HasPeripheryBootROMModuleImp
|
||||
with CanHavePeripherySerialModuleImp
|
||||
with HasPeripheryUARTModuleImp
|
||||
with CanHavePeripheryBlockDeviceModuleImp
|
||||
with HasTraceIOImp
|
||||
with HasFireSimClockingImp
|
||||
with CanHaveMultiCycleRegfileImp
|
||||
|
||||
class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT)
|
||||
|
||||
class FireSimTraceGenDUT(implicit p: Parameters) extends BaseSubsystem
|
||||
with HasHierarchicalBusTopology
|
||||
with HasTraceGenTiles
|
||||
with CanHaveMasterAXI4MemPort {
|
||||
override lazy val module = new FireSimTraceGenModuleImp(this)
|
||||
}
|
||||
|
||||
class FireSimTraceGenModuleImp(outer: FireSimTraceGenDUT) extends BaseSubsystemModuleImp(outer)
|
||||
with HasTraceGenTilesModuleImp
|
||||
with CanHaveMasterAXI4MemPortModuleImp
|
||||
|
||||
class FireSimTraceGen(implicit p: Parameters) extends DefaultFireSimHarness(
|
||||
() => new FireSimTraceGenDUT)
|
||||
|
||||
// Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1
|
||||
class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT)
|
||||
|
||||
// Verilog blackbox integration demo
|
||||
class FireSimVerilogGCDDUT(implicit p: Parameters) extends FireSimDUT
|
||||
with example.CanHavePeripheryGCD
|
||||
{
|
||||
override lazy val module = new FireSimVerilogGCDModuleImp(this)
|
||||
}
|
||||
|
||||
class FireSimVerilogGCDModuleImp[+L <: FireSimVerilogGCDDUT](l: L) extends FireSimModuleImp(l)
|
||||
|
||||
class FireSimVerilogGCD(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimVerilogGCDDUT)
|
||||
@@ -136,18 +136,18 @@ abstract class FireSimTestSuite(
|
||||
runSuite("verilator")(FastBlockdevTests)
|
||||
}
|
||||
|
||||
class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", "BaseF1Config")
|
||||
class BoomF1Tests extends FireSimTestSuite("FireSimNoNIC", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config")
|
||||
class RocketNICF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimRocketChipConfig", "BaseF1Config") {
|
||||
class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "BaseF1Config")
|
||||
class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config")
|
||||
class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") {
|
||||
runSuite("verilator")(NICLoopbackTests)
|
||||
}
|
||||
class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams")
|
||||
class RamModelBoomF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimBoomConfig", "BaseF1Config_MCRams")
|
||||
class RamModelRocketF1Tests extends FireSimTestSuite("FireSim", "FireSimDualRocketConfig", "BaseF1Config_MCRams")
|
||||
class RamModelBoomF1Tests extends FireSimTestSuite("FireSim", "FireSimBoomConfig", "BaseF1Config_MCRams")
|
||||
|
||||
// Multiclock tests
|
||||
class RocketMulticlockF1Tests extends FireSimTestSuite(
|
||||
"FireSimNoNIC",
|
||||
"HalfRateUncore_DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig",
|
||||
"FireSim",
|
||||
"HalfRateUncore_DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig",
|
||||
"WithSynthAsserts_BaseF1Config")
|
||||
|
||||
abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String)
|
||||
|
||||
Reference in New Issue
Block a user