add additional example code as literalincludes
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@@ -115,12 +115,14 @@ class MyCounterRegisters(implicit p: Parameters) extends LazyModule {
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def readCounter(ready: Bool): (Bool, UInt) = {
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when (ready) { counter := counter - 1.U }
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// (ready, bits)
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(true.B, counter)
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}
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def writeCounter(valid: Bool, bits: UInt): Bool = {
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when (valid) { counter := counter + 1.U }
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// Ignore bits
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// Return ready
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true.B
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}
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@@ -153,10 +155,11 @@ class MyCounterReqRespRegisters(implicit p: Parameters) extends LazyModule {
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responding := false.B
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}
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// (iready, ovalid, obits)
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(!responding, responding, counter)
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}
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def writeCounter(ivalid: Bool, oready: Bool, bits: UInt): (Bool, Bool) = {
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def writeCounter(ivalid: Bool, oready: Bool, ibits: UInt): (Bool, Bool) = {
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val responding = RegInit(false.B)
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when (ivalid && !responding) { responding := true.B }
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@@ -166,6 +169,7 @@ class MyCounterReqRespRegisters(implicit p: Parameters) extends LazyModule {
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responding := false.B
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}
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// (iready, ovalid)
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(!responding, responding)
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}
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