diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh
index 51e56449..ae05eb56 100755
--- a/.circleci/check-commit.sh
+++ b/.circleci/check-commit.sh
@@ -122,12 +122,7 @@ search
 
 submodules=("fpga-shells")
 dir="fpga"
-if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ]
-then
-    branches=("master")
-else
-    branches=("master" "dev")
-fi
+branches=("master")
 search
 
 # turn off verbose printing to make this easier to read
diff --git a/.circleci/config.yml b/.circleci/config.yml
index f5130930..25de2322 100644
--- a/.circleci/config.yml
+++ b/.circleci/config.yml
@@ -81,12 +81,15 @@ commands:
             build-script:
                 type: string
                 default: "do-rtl-build.sh"
+            build-type:
+                type: string
+                default: "sim"
         steps:
             - setup-tools:
                 tools-version: "<< parameters.tools-version >>"
             - run:
                 name: Building << parameters.group-key >> subproject using Verilator
-                command: .circleci/<< parameters.build-script >> << parameters.group-key >>
+                command: .circleci/<< parameters.build-script >> << parameters.group-key >> << parameters.build-type >>
                 no_output_timeout: << parameters.timeout >>
             - save_cache:
                 key: << parameters.group-key >>-{{ .Branch }}-{{ .Revision }}
@@ -366,7 +369,7 @@ jobs:
         steps:
             - prepare-rtl:
                 group-key: "group-fpga"
-                build-script: "do-fpga-rtl-build.sh"
+                build-type: "fpga"
 
 # Order and dependencies of jobs to run
 workflows:
diff --git a/.circleci/do-fpga-rtl-build.sh b/.circleci/do-fpga-rtl-build.sh
deleted file mode 100755
index 29a5dac2..00000000
--- a/.circleci/do-fpga-rtl-build.sh
+++ /dev/null
@@ -1,52 +0,0 @@
-#!/bin/bash
-
-# create the different verilator builds
-# argument is the make command string
-
-# turn echo on and error on earliest command
-set -ex
-
-# get shared variables
-SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )"
-source $SCRIPT_DIR/defaults.sh
-
-# call clean on exit
-trap clean EXIT
-
-cd $LOCAL_CHIPYARD_DIR
-./scripts/init-submodules-no-riscv-tools.sh
-
-# set stricthostkeychecking to no (must happen before rsync)
-run "echo \"Ping $SERVER\""
-
-clean
-
-# copy over riscv/esp-tools, and chipyard to remote
-run "mkdir -p $REMOTE_CHIPYARD_DIR"
-copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR
-
-run "cp -r ~/.ivy2 $REMOTE_WORK_DIR"
-run "cp -r ~/.sbt  $REMOTE_WORK_DIR"
-
-TOOLS_DIR=$REMOTE_RISCV_DIR
-LD_LIB_DIR=$REMOTE_RISCV_DIR/lib
-
-run "mkdir -p $REMOTE_RISCV_DIR"
-copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR
-
-# enter the verilator directory and build the specific config on remote server
-run "export RISCV=\"$TOOLS_DIR\"; \
-     make -C $REMOTE_FPGA_DIR clean;"
-
-read -a keys <<< ${grouping[$1]}
-
-for key in "${keys[@]}"
-do
-    run "export RISCV=\"$TOOLS_DIR\"; \
-         export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \
-         export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \
-         export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \
-         make -j$REMOTE_MAKE_NPROC -C $REMOTE_FPGA_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}"
-done
-
-run "rm -rf $REMOTE_CHIPYARD_DIR/project"
diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh
index 784dbc04..9780f64b 100755
--- a/.circleci/do-rtl-build.sh
+++ b/.circleci/do-rtl-build.sh
@@ -1,7 +1,11 @@
 #!/bin/bash
 
 # create the different verilator builds
-# argument is the make command string
+# usage:
+#   do-rtl-build.sh <make command string> sim
+#     run rtl build for simulations and copy back results
+#   do-rtl-build.sh <make command string> fpga
+#     run rtl build for fpga and don't copy back results
 
 # turn echo on and error on earliest command
 set -ex
@@ -50,9 +54,19 @@ else
     copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR
 fi
 
+# choose what make dir to use
+case $2 in
+    "sim")
+        REMOTE_MAKE_DIR=$REMOTE_SIM_DIR
+        ;;
+    "fpga")
+        REMOTE_MAKE_DIR=$REMOTE_FPGA_DIR
+        ;;
+esac
+
 # enter the verilator directory and build the specific config on remote server
 run "export RISCV=\"$TOOLS_DIR\"; \
-     make -C $REMOTE_SIM_DIR clean;"
+     make -C $REMOTE_MAKE_DIR clean;"
 
 read -a keys <<< ${grouping[$1]}
 
@@ -63,11 +77,14 @@ do
          export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \
          export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \
          export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \
-         make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}"
+         make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}"
 done
 
 run "rm -rf $REMOTE_CHIPYARD_DIR/project"
 
-# copy back the final build
-mkdir -p $LOCAL_CHIPYARD_DIR
-copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR
+# choose to copy back results
+if [ $2 = "sim" ]; then
+    # copy back the final build
+    mkdir -p $LOCAL_CHIPYARD_DIR
+    copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR
+fi