Merge remote-tracking branch 'upstream/main' into graphics

.github/scripts/defaults.sh

@@ -31,8 +31,8 @@ JAVA_TMP_DIR=$(mktemp -d -t ci-cy-XXXXXXXX)
 # key value store to get the build groups
 declare -A grouping
 grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone"
-grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif chipyard-nocores"
+grouping["group-peripherals"]="chipyard-dmirocket chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals"
-grouping["group-accels"]="chipyard-fftgenerator chipyard-nvdla chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
+grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels"
 grouping["group-constellation"]="chipyard-constellation"
 grouping["group-tracegen"]="tracegen tracegen-boom"
 grouping["group-other"]="icenet testchipip constellation"
@@ -42,32 +42,26 @@ grouping["group-fpga"]="arty vcu118 vc707"
 declare -A mapping
 mapping["chipyard-rocket"]=""
 mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig"
-mapping["chipyard-lbwif"]=" CONFIG=LBWIFRocketConfig"
 mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig"
 mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig"
 mapping["chipyard-digitaltop"]=" TOP=DigitalTop"
-mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig"
+mapping["chipyard-manymmioaccels"]=" CONFIG=ManyMMIOAcceleratorRocketConfig"
-mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig"
 mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig"
 mapping["chipyard-boom"]=" CONFIG=MediumBoomCosimConfig"
 mapping["chipyard-spike"]=" CONFIG=SpikeFastUARTConfig EXTRA_SIM_FLAGS='+spike-ipc=10'"
-mapping["chipyard-blkdev"]=" CONFIG=SimBlockDeviceRocketConfig"
 mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
 mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
 mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
 mapping["chipyard-ibex"]=" CONFIG=IbexConfig"
-mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig"
+mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
-mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig"
+mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
-mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog"
 mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog"
 mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"
 mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"
 mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig"
-mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig"
 mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig"
 mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig"
 mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig"
-mapping["chipyard-fftgenerator"]=" CONFIG=FFTRocketConfig"
 mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig"
 
 mapping["constellation"]=" SUB_PROJECT=constellation"

.github/scripts/run-tests.sh

@@ -35,9 +35,6 @@ case $1 in
     chipyard-dmirocket)
         run_bmark ${mapping[$1]}
         ;;
-    chipyard-lbwif)
-        run_bmark ${mapping[$1]}
-        ;;
     chipyard-boom)
         run_bmark ${mapping[$1]}
         ;;
@@ -69,21 +66,33 @@ case $1 in
         (cd $LOCAL_CHIPYARD_DIR/generators/mempress/software/src && make)
         make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary-fast BINARY=$LOCAL_CHIPYARD_DIR/generators/mempress/software/src/mempress-rocc.riscv
         ;;
-    chipyard-streaming-passthrough)
+    chipyard-manymmioaccels)
-        make -C $LOCAL_CHIPYARD_DIR/tests
+	make -C $LOCAL_CHIPYARD_DIR/tests
+
+	# test streaming-passthrough
         make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary-fast BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-passthrough.riscv
-        ;;
+
-    chipyard-streaming-fir)
+	# test streaming-fir
-        make -C $LOCAL_CHIPYARD_DIR/tests
         make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary-fast BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-fir.riscv
-        ;;
+
-    chipyard-spiflashread)
+	# test nvdla
+        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv run-binary-fast
+
+	# test fft
+        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/fft.riscv run-binary-fast
+
+	;;
+    chipyard-manyperipherals)
+	# SPI Flash read tests, then bmark tests
+
         make -C $LOCAL_CHIPYARD_DIR/tests
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashread.riscv SIM_FLAGS="+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img" run-binary-fast
+        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashread.riscv run-binary-fast
+
+	run_bmark ${mapping[$1]}
         ;;
     chipyard-spiflashwrite)
         make -C $LOCAL_CHIPYARD_DIR/tests
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashwrite.riscv SIM_FLAGS="+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img" run-binary-fast
+        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashwrite.riscv run-binary-fast
         [[ "`xxd $LOCAL_CHIPYARD_DIR/tests/spiflash.img  | grep 1337\ 00ff\ aa55\ face | wc -l`" == "6" ]] || false
         ;;
     tracegen)
@@ -101,16 +110,8 @@ case $1 in
     chipyard-sodor)
         run_asm ${mapping[$1]}
         ;;
-    chipyard-nvdla)
-        make -C $LOCAL_CHIPYARD_DIR/tests
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv run-binary-fast
-        ;;
-    chipyard-fftgenerator)
-        make -C $LOCAL_CHIPYARD_DIR/tests
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/fft.riscv run-binary-fast
-        ;;
     chipyard-constellation)
-        run_bmark ${mapping[$1]}
+        make run-binary-hex BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]}
         ;;
     icenet)
         make run-binary-fast BINARY=none -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]}

.github/workflows/chipyard-run-tests.yml

@@ -551,29 +551,6 @@ jobs:
           group-key: "group-cores"
           project-key: "chipyard-spike"
 
-  chipyard-fftgenerator-run-tests:
-    name: chipyard-fftgenerator-run-tests
-    needs: prepare-chipyard-accels
-    runs-on: self-hosted
-    steps:
-      - name: Delete old checkout
-        run: |
-            ls -alh .
-            rm -rf ${{ github.workspace }}/* || true
-            rm -rf ${{ github.workspace }}/.* || true
-            ls -alh .
-      - name: Checkout
-        uses: actions/checkout@v3
-      - name: Git workaround
-        uses: ./.github/actions/git-workaround
-      - name: Create conda env
-        uses: ./.github/actions/create-conda-env
-      - name: Run tests
-        uses: ./.github/actions/run-tests
-        with:
-          group-key: "group-accels"
-          project-key: "chipyard-fftgenerator"
-
   chipyard-dmirocket-run-tests:
     name: chipyard-dmirocket-run-tests
     needs: prepare-chipyard-peripherals
@@ -620,31 +597,8 @@ jobs:
           group-key: "group-peripherals"
           project-key: "chipyard-spiflashwrite"
 
-  chipyard-spiflashread-run-tests:
+  chipyard-manyperipherals-run-tests:
-    name: chipyard-spiflashread-run-tests
+    name: chipyard-manyperipherals-run-tests
-    needs: prepare-chipyard-peripherals
-    runs-on: self-hosted
-    steps:
-      - name: Delete old checkout
-        run: |
-          ls -alh .
-          rm -rf ${{ github.workspace }}/* || true
-          rm -rf ${{ github.workspace }}/.* || true
-          ls -alh .
-      - name: Checkout
-        uses: actions/checkout@v3
-      - name: Git workaround
-        uses: ./.github/actions/git-workaround
-      - name: Create conda env
-        uses: ./.github/actions/create-conda-env
-      - name: Run tests
-        uses: ./.github/actions/run-tests
-        with:
-          group-key: "group-peripherals"
-          project-key: "chipyard-spiflashread"
-
-  chipyard-lbwif-run-tests:
-    name: chipyard-lbwif-run-tests
     needs: prepare-chipyard-peripherals
     runs-on: self-hosted
     steps:
@@ -664,7 +618,7 @@ jobs:
         uses: ./.github/actions/run-tests
         with:
           group-key: "group-peripherals"
-          project-key: "chipyard-lbwif"
+          project-key: "chipyard-manyperipherals"
 
   chipyard-sha3-run-tests:
     name: chipyard-sha3-run-tests
@@ -689,52 +643,6 @@ jobs:
           group-key: "group-accels"
           project-key: "chipyard-sha3"
 
-  chipyard-streaming-fir-run-tests:
-    name: chipyard-streaming-fir-run-tests
-    needs: prepare-chipyard-accels
-    runs-on: self-hosted
-    steps:
-      - name: Delete old checkout
-        run: |
-            ls -alh .
-            rm -rf ${{ github.workspace }}/* || true
-            rm -rf ${{ github.workspace }}/.* || true
-            ls -alh .
-      - name: Checkout
-        uses: actions/checkout@v3
-      - name: Git workaround
-        uses: ./.github/actions/git-workaround
-      - name: Create conda env
-        uses: ./.github/actions/create-conda-env
-      - name: Run tests
-        uses: ./.github/actions/run-tests
-        with:
-          group-key: "group-accels"
-          project-key: "chipyard-streaming-fir"
-
-  chipyard-streaming-passthrough-run-tests:
-    name: chipyard-streaming-passthrough-run-tests
-    needs: prepare-chipyard-accels
-    runs-on: self-hosted
-    steps:
-      - name: Delete old checkout
-        run: |
-            ls -alh .
-            rm -rf ${{ github.workspace }}/* || true
-            rm -rf ${{ github.workspace }}/.* || true
-            ls -alh .
-      - name: Checkout
-        uses: actions/checkout@v3
-      - name: Git workaround
-        uses: ./.github/actions/git-workaround
-      - name: Create conda env
-        uses: ./.github/actions/create-conda-env
-      - name: Run tests
-        uses: ./.github/actions/run-tests
-        with:
-          group-key: "group-accels"
-          project-key: "chipyard-streaming-passthrough"
-
   chipyard-gemmini-run-tests:
     name: chipyard-gemmini-run-tests
     needs: prepare-chipyard-accels
@@ -758,8 +666,8 @@ jobs:
           group-key: "group-accels"
           project-key: "chipyard-gemmini"
 
-  chipyard-nvdla-run-tests:
+  chipyard-manymmioaccels-run-tests:
-    name: chipyard-nvdla-run-tests
+    name: chipyard-manymmioaccels-run-tests
     needs: prepare-chipyard-accels
     runs-on: self-hosted
     steps:
@@ -779,7 +687,7 @@ jobs:
         uses: ./.github/actions/run-tests
         with:
           group-key: "group-accels"
-          project-key: "chipyard-nvdla"
+          project-key: "chipyard-manymmioaccels"
 
   chipyard-mempress-run-tests:
     name: chipyard-mempress-run-tests
@@ -1008,15 +916,11 @@ jobs:
             chipyard-ibex-run-tests,
             chipyard-sodor-run-tests,
             chipyard-dmirocket-run-tests,
-            chipyard-fftgenerator-run-tests,
-            chipyard-spiflashread-run-tests,
             chipyard-spiflashwrite-run-tests,
-            chipyard-lbwif-run-tests,
+            chipyard-manyperipherals-run-tests,
             chipyard-sha3-run-tests,
-            chipyard-streaming-fir-run-tests,
-            chipyard-streaming-passthrough-run-tests,
             chipyard-gemmini-run-tests,
-            chipyard-nvdla-run-tests,
+            chipyard-manymmioaccels-run-tests,
             chipyard-mempress-run-tests,
             chipyard-constellation-run-tests,
             tracegen-boom-run-tests,

build.sbt

@@ -12,7 +12,10 @@ lazy val commonSettings = Seq(
   assembly / assemblyMergeStrategy := { _ match {
     case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
     case _ => MergeStrategy.first}},
-  scalacOptions ++= Seq("-deprecation","-unchecked"),
+  scalacOptions ++= Seq(
+    "-deprecation",
+    "-unchecked",
+    "-Ymacro-annotations"), // fix hierarchy API
   unmanagedBase := (chipyardRoot / unmanagedBase).value,
   allDependencies := {
     // drop specific maven dependencies in subprojects in favor of Chipyard's version

docs/VLSI/Advanced-Usage.rst

@@ -95,6 +95,6 @@ With the Synopsys plugin, hierarchical RTL and gate-level simulation is supporte
 
 * ``redo-`` can be appended to all above targets to break dependency tracking, like described above.
 
-* ``-$(VLSI_TOP)`` suffixes denote simulations/power analysis on a submodule in a hierarchical flow. Note that you must provide the testbenches for these modules since the default testbench only simulates a Chipyard-based ``ChipTop`` DUT instance.
+* ``-$(VLSI_TOP)`` suffixes denote simulations/power analysis on a submodule in a hierarchical flow (remember to override this variable). Note that you must provide the testbenches for these modules since the default testbench only simulates a Chipyard-based ``ChipTop`` DUT instance.
 
 The simulation configuration (e.g. binaries) can be edited for your design. See the ``Makefile`` and refer to Hammer's documentation for how to set up simulation parameters for your design.

docs/VLSI/Basic-Flow.rst

@@ -295,8 +295,11 @@ For example, if we choose to specifiy the previously mentioned ``GemminiRocketCo
             bottom: 0
 
 
-In this specification, ``vlsi.inputs.hierarchical.mode`` indicates the manual specification of the heirarchy tree (which is the only mode currently supported by Hammer), ``vlsi.inputs.hiearchical.top_module`` sets the root of the hierarchical tree, ``vlsi.inputs.hierarchical.manual_modules`` enumerates the tree of hierarchical modules, and ``vlsi.inputs.hierarchical.manual_placement_constraints`` enumerates the floorplan for each module.
+In this specification, ``vlsi.inputs.hierarchical.mode`` indicates the manual specification of the hierarchy tree (which is the only mode currently supported by Hammer), ``vlsi.inputs.hierarchical.top_module`` sets the root of the hierarchical tree, ``vlsi.inputs.hierarchical.manual_modules`` enumerates the tree of hierarchical modules, and ``vlsi.inputs.hierarchical.manual_placement_constraints`` enumerates the floorplan for each module.
 
+For more information about the Hammer hierarchical flow and specifying the hierarchy and constraints, visit the `Hammer documentation <https://hammer-vlsi.readthedocs.io/en/stable/Hammer-Use/Hierarchical.html>`__.
+
+.. Note:: You must generate the hierarchical hierarchy BEFORE running the ``make buildfile`` target. This is because Hammer encodes its hierarchical flow graph in a generated Makefile in ``$(OBJ_DIR)/hammer.d``. If you modify your physical hierarchy, you must wipe and regenerate this Makefile. Finally, you must always override the ``VLSI_TOP`` variable to be the hierarchical block that you are working on. This is required for hierarchical simulation and power flows.
 
 .. Specifying a Custom Floorplan
 .. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

fpga/Makefile

@@ -90,12 +90,10 @@ fpga_common_script_dir := $(fpga_dir)/common/tcl
 #########################################################################################
 # setup misc. sim files
 #########################################################################################
-SIM_FILE_REQS += \
-	$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v
-
 # copy files but ignore *.h files in *.f (match vcs)
 $(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(GEN_COLLATERAL_DIR)
-	cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR)
+	-cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR)
+	touch $@
 	$(foreach file,\
 		$(SIM_FILE_REQS),\
 		$(if $(filter %.h,$(file)),\

generators/chipyard/src/main/resources/csrc/cospike.cc

@@ -226,6 +226,7 @@ extern "C" void cospike_cosim(long long int cycle,
           bool csr_read = (insn & 0x7f) == 0x73;
           if (csr_read) printf("CSR read %lx\n", csr_addr);
           if (csr_read && (
+                           (csr_addr == 0x301) || // misa
                            (csr_addr == 0xf13) || // mimpid
                            (csr_addr == 0xf12) || // marchid
                            (csr_addr == 0xf11) || // mvendorid

generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala

@@ -56,3 +56,11 @@ class LargeNVDLARocketConfig extends Config(
   new nvidia.blocks.dla.WithNVDLA("large", true) ++         // add a large NVDLA with synth. rams
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
+
+class ManyMMIOAcceleratorRocketConfig extends Config(
+  new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
+  new nvidia.blocks.dla.WithNVDLA("small") ++               // add a small NVDLA
+  new chipyard.example.WithStreamingPassthrough ++          // use top with tilelink-controlled streaming passthrough
+  new chipyard.example.WithStreamingFIR ++                  // use top with tilelink-controlled streaming FIR
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala

@@ -63,3 +63,15 @@ class dmiRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: DmiRocket
+
+class ManyPeripheralsRocketConfig extends Config(
+  new chipyard.harness.WithSimSPIFlashModel(true) ++         // add the SPI flash model in the harness (read-only)
+  new chipyard.harness.WithSimBlockDevice ++                 // drive block-device IOs with SimBlockDevice
+  new chipyard.config.WithSPIFlash ++                        // add the SPI flash controller
+  new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++  // add default external master port
+  new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
+  new testchipip.WithBlockDevice ++                          // add block-device module to peripherybus
+  new testchipip.WithSerialTLMem(isMainMemory=true) ++       // set lbwif memory base to DRAM_BASE, use as main memory
+  new freechips.rocketchip.subsystem.WithNoMemPort ++        // remove AXI4 backing memory
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)

scripts/build-setup.sh

@@ -91,7 +91,7 @@ run_step() {
 # Check for this, since many users will be attempting to use this with gemmini
 if [ $TOOLCHAIN_TYPE == "esp-tools" ]; then
     while true; do
-        read -p "WARNING: You are trying to install the esp-tools toolchain."$'n'"This should ONLY be used for Hwacha development."$'\n'"Gemmini should be used with riscv-tools."$'\n'"Type \"y\" to continue if this is intended, or \"n\" if not: " validate
+        read -p "WARNING: You are trying to install the esp-tools toolchain."$'\n'"This should ONLY be used for Hwacha development."$'\n'"Gemmini should be used with riscv-tools."$'\n'"Type \"y\" to continue if this is intended, or \"n\" if not: " validate
         case "$validate" in
             y | Y)
                 echo "Installing esp-tools."

vlsi/power.mk

@@ -2,8 +2,9 @@ POWER_CONF = $(OBJ_DIR)/power-inputs.yml
 POWER_RTL_CONF = $(OBJ_DIR)/power-rtl-inputs.yml
 POWER_SYN_CONF = $(OBJ_DIR)/power-syn-inputs.yml
 POWER_PAR_CONF = $(OBJ_DIR)/power-par-inputs.yml
+POWER_PAR_HIER_CONF = $(OBJ_DIR)/power-par-$(VLSI_TOP)-inputs.yml
 
-.PHONY: $(POWER_CONF) $(POWER_RTL_CONF) $(POWER_SYN_CONF) $(POWER_PAR_CONF)
+.PHONY: $(POWER_CONF) $(POWER_RTL_CONF) $(POWER_SYN_CONF) $(POWER_PAR_CONF) $(POWER_PAR_HIER_CONF)
 
 $(POWER_CONF): $(VLSI_RTL)
 	mkdir -p $(dir $@)
@@ -45,6 +46,12 @@ $(POWER_PAR_CONF): $(VLSI_RTL)
 	echo "  level: par" >> $@
 	echo "  database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@
 
+$(POWER_PAR_HIER_CONF): $(VLSI_RTL)
+	echo "vlsi.core.power_tool: hammer.power.voltus" > $@
+	echo "power.inputs:" >> $@
+	echo "  level: par" >> $@
+	echo "  database: '$(OBJ_DIR)/par-$(VLSI_TOP)/$(VLSI_TOP)_FINAL'" >> $@
+
 power-rtl: $(POWER_CONF) $(POWER_RTL_CONF) sim-rtl-debug
 power-rtl-$(VLSI_TOP): $(POWER_CONF) $(POWER_RTL_CONF) sim-rtl-debug-$(VLSI_TOP)
 power-rtl: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_RTL_CONF)
@@ -64,12 +71,12 @@ redo-power-syn: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_SYN_CO
 redo-power-syn-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_SYN_CONF)
 
 power-par: $(POWER_CONF) $(POWER_PAR_CONF) sim-par-debug
-power-par-$(VLSI_TOP): $(POWER_CONF) $(POWER_PAR_CONF) sim-par-debug-$(VLSI_TOP)
+power-par-$(VLSI_TOP): $(POWER_CONF) $(POWER_PAR_HIER_CONF) sim-par-debug-$(VLSI_TOP)
 power-par: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_CONF)
-power-par-$(VLSI_TOP): override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_CONF)
+power-par-$(VLSI_TOP): override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_HIER_CONF)
 redo-power-par: $(POWER_CONF) $(POWER_PAR_CONF)
-redo-power-par-$(VLSI_TOP): $(POWER_CONF) $(POWER_PAR_CONF)
+redo-power-par-$(VLSI_TOP): $(POWER_CONF) $(POWER_PAR_HIER_CONF)
 redo-power-par: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_CONF)
-redo-power-par-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_CONF)
+redo-power-par-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_HIER_CONF)
 
 $(OBJ_DIR)/power-%/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS)