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Merge remote-tracking branch 'upstream/main' into graphics

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This commit is contained in:
Hansung Kim
2023-02-26 21:12:36 -08:00
parent 09782b3322 58590f2abe
commit d57c384342
13 changed files with 81 additions and 150 deletions
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2
generators/boom

Submodule generators/boom updated: 615f4ef60f...deae9f7046

1
generators/chipyard/src/main/resources/csrc/cospike.cc
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@@ -226,6 +226,7 @@ extern "C" void cospike_cosim(long long int cycle,
bool csr_read = (insn & 0x7f) == 0x73;
if (csr_read) printf("CSR read %lx\n", csr_addr);
if (csr_read && (
(csr_addr == 0x301) || // misa
(csr_addr == 0xf13) || // mimpid
(csr_addr == 0xf12) || // marchid
(csr_addr == 0xf11) || // mvendorid

8
generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
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@@ -56,3 +56,11 @@ class LargeNVDLARocketConfig extends Config(
new nvidia.blocks.dla.WithNVDLA("large", true) ++ // add a large NVDLA with synth. rams
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
class ManyMMIOAcceleratorRocketConfig extends Config(
new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA
new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough
new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

12
generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
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@@ -63,3 +63,15 @@ class dmiRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include end: DmiRocket
class ManyPeripheralsRocketConfig extends Config(
new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only)
new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice
new chipyard.config.WithSPIFlash ++ // add the SPI flash controller
new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port
new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
new testchipip.WithBlockDevice ++ // add block-device module to peripherybus
new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)