From e7c727372ff3cb9ccf91a8ea3575fb2b4e040c70 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Mon, 26 Aug 2019 14:32:08 -0700
Subject: [PATCH 01/16] Cleanup configs

---
 generators/boom                               |   2 +-
 .../example/src/main/scala/BoomConfigs.scala  | 101 +++---
 .../example/src/main/scala/ConfigMixins.scala |  44 +--
 .../example/src/main/scala/Configs.scala      | 300 ++++--------------
 .../src/main/scala/HeteroConfigs.scala        |  84 +++++
 .../example/src/main/scala/Subsystem.scala    | 108 +++++++
 .../example/src/main/scala/System.scala       |  63 ++++
 .../example/src/main/scala/TestHarness.scala  |   8 +-
 generators/example/src/main/scala/Top.scala   |  40 +--
 .../utilities/src/main/scala/TestSuites.scala |   2 +-
 variables.mk                                  |   4 +-
 11 files changed, 412 insertions(+), 344 deletions(-)
 create mode 100644 generators/example/src/main/scala/HeteroConfigs.scala
 create mode 100644 generators/example/src/main/scala/Subsystem.scala
 create mode 100644 generators/example/src/main/scala/System.scala

diff --git a/generators/boom b/generators/boom
index 4e9d496d..793912ee 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit 4e9d496d3678cc5ae005669a448ae9e89f8ae847
+Subproject commit 793912eef8a9f09c13bd791c33ba682350a6026a
diff --git a/generators/example/src/main/scala/BoomConfigs.scala b/generators/example/src/main/scala/BoomConfigs.scala
index f328b902..c97154aa 100644
--- a/generators/example/src/main/scala/BoomConfigs.scala
+++ b/generators/example/src/main/scala/BoomConfigs.scala
@@ -3,88 +3,65 @@ package example
 import chisel3._
 
 import freechips.rocketchip.config.{Config}
-import freechips.rocketchip.subsystem.{WithJtagDTM}
-
-import boom.common._
 
 // ---------------------
 // BOOM Configs
 // ---------------------
 
 class SmallBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.SmallBoomConfig)
+  new WithTop ++                                            // use normal top
+  new WithBootROM ++                                        // use testchipip bootrom
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++  // use Sifive L2 cache
+  new boom.common.WithSmallBooms ++                         // 1-wide BOOM
+  new boom.common.WithNBoomCores(1) ++                      // single-core
+  new freechips.rocketchip.system.BaseConfig)               // "Base" rocketchip system
 
 class MediumBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
+  new WithTop ++
   new WithBootROM ++
-  new boom.common.MediumBoomConfig)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithMediumBooms ++                        // 2-wide BOOM
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
 
 class LargeBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
+  new WithTop ++
   new WithBootROM ++
-  new boom.common.LargeBoomConfig)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithLargeBooms ++                         // 3-wide BOOM
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
 
 class MegaBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
+  new WithTop ++
   new WithBootROM ++
-  new boom.common.MegaBoomConfig)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithMegaBooms ++                          // 4-wide BOOM
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
 
-class jtagSmallBoomConfig extends Config(
-  new WithDTMBoomRocketTop ++
+class DualSmallBoomConfig extends Config(
+  new WithTop ++
   new WithBootROM ++
-  new WithJtagDTM ++
-  new boom.common.SmallBoomConfig)
-
-class jtagMediumBoomConfig extends Config(
-  new WithDTMBoomRocketTop ++
-  new WithBootROM ++
-  new WithJtagDTM ++
-  new boom.common.MediumBoomConfig)
-
-class jtagLargeBoomConfig extends Config(
-  new WithDTMBoomRocketTop ++
-  new WithBootROM ++
-  new WithJtagDTM ++
-  new boom.common.LargeBoomConfig)
-
-class jtagMegaBoomConfig extends Config(
-  new WithDTMBoomRocketTop ++
-  new WithBootROM ++
-  new WithJtagDTM ++
-  new boom.common.MegaBoomConfig)
-
-class SmallDualBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.SmallDualBoomConfig)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithSmallBooms ++
+  new boom.common.WithNBoomCores(2) ++                      // dual-core
+  new freechips.rocketchip.system.BaseConfig)
 
 class TracedSmallBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
+  new WithTop ++
   new WithBootROM ++
-  new boom.common.TracedSmallBoomConfig)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithTrace ++                             // enable trace port on BOOM
+  new boom.common.WithSmallBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
 
 class SmallRV32UnifiedBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
+  new WithTop ++
   new WithBootROM ++
-  new boom.common.SmallRV32UnifiedBoomConfig)
-
-// --------------------------
-// BOOM + Rocket Configs
-// --------------------------
-
-class SmallBoomAndRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.SmallBoomAndRocketConfig)
-
-class MediumBoomAndRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.MediumBoomAndRocketConfig)
-
-class DualMediumBoomAndDualRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.DualMediumBoomAndDualRocketConfig)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithUnifiedMemIntIQs ++                 // use unified mem+int issue queues
+  new boom.common.WithSmallBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala
index 17fac94d..17cbcaa5 100644
--- a/generators/example/src/main/scala/ConfigMixins.scala
+++ b/generators/example/src/main/scala/ConfigMixins.scala
@@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy.{LazyModule, ValName}
 import freechips.rocketchip.devices.tilelink.BootROMParams
 import freechips.rocketchip.tile.{XLen, BuildRoCC, TileKey, LazyRoCC}
 
-import boom.system.{BoomTilesKey}
+import boom.common.{BoomTilesKey}
 
 import testchipip._
 
@@ -52,43 +52,43 @@ class WithGPIO extends Config((site, here, up) => {
 /**
  * Class to specify a "plain" top level BOOM and/or Rocket system
  */
-class WithNormalBoomRocketTop extends Config((site, here, up) => {
-  case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
-    Module(LazyModule(new BoomRocketTop()(p)).module)
+class WithTop extends Config((site, here, up) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
+    Module(LazyModule(new Top()(p)).module)
   }
 })
 
 /**
  * Class to specify a top level BOOM and/or Rocket system with DTM
  */
-class WithDTMBoomRocketTop extends Config((site, here, up) => {
-  case BuildBoomRocketTopWithDTM => (clock: Clock, reset: Bool, p: Parameters) => {
-    Module(LazyModule(new BoomRocketTopWithDTM()(p)).module)
+class WithDTMTop extends Config((site, here, up) => {
+  case BuildTopWithDTM => (clock: Clock, reset: Bool, p: Parameters) => {
+    Module(LazyModule(new TopWithDTM()(p)).module)
   }
 })
 
 /**
  * Class to specify a top level BOOM and/or Rocket system with PWM
  */
-class WithPWMBoomRocketTop extends Config((site, here, up) => {
-  case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) =>
-    Module(LazyModule(new BoomRocketTopWithPWMTL()(p)).module)
+class WithPWMTop extends Config((site, here, up) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
+    Module(LazyModule(new TopWithPWMTL()(p)).module)
 })
 
 /**
  * Class to specify a top level BOOM and/or Rocket system with a PWM AXI4
  */
-class WithPWMAXI4BoomRocketTop extends Config((site, here, up) => {
-  case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) =>
-    Module(LazyModule(new BoomRocketTopWithPWMAXI4()(p)).module)
+class WithPWMAXI4Top extends Config((site, here, up) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
+    Module(LazyModule(new TopWithPWMAXI4()(p)).module)
 })
 
 /**
  * Class to specify a top level BOOM and/or Rocket system with a block device
  */
-class WithBlockDeviceModelBoomRocketTop extends Config((site, here, up) => {
-  case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
-    val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module)
+class WithBlockDeviceModelTop extends Config((site, here, up) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
+    val top = Module(LazyModule(new TopWithBlockDevice()(p)).module)
     top.connectBlockDeviceModel()
     top
   }
@@ -97,9 +97,9 @@ class WithBlockDeviceModelBoomRocketTop extends Config((site, here, up) => {
 /**
  * Class to specify a top level BOOM and/or Rocket system with a simulator block device
  */
-class WithSimBlockDeviceBoomRocketTop extends Config((site, here, up) => {
-  case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
-    val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module)
+class WithSimBlockDeviceTop extends Config((site, here, up) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
+    val top = Module(LazyModule(new TopWithBlockDevice()(p)).module)
     top.connectSimBlockDevice(clock, reset)
     top
   }
@@ -108,9 +108,9 @@ class WithSimBlockDeviceBoomRocketTop extends Config((site, here, up) => {
 /**
  * Class to specify a top level BOOM and/or Rocket system with GPIO
  */
-class WithGPIOBoomRocketTop extends Config((site, here, up) => {
-  case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
-    val top = Module(LazyModule(new BoomRocketTopWithGPIO()(p)).module)
+class WithGPIOTop extends Config((site, here, up) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
+    val top = Module(LazyModule(new TopWithGPIO()(p)).module)
     for (gpio <- top.gpio) {
       for (pin <- gpio.pins) {
         pin.i.ival := false.B
diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala
index c7e70dd2..5004e6ee 100644
--- a/generators/example/src/main/scala/Configs.scala
+++ b/generators/example/src/main/scala/Configs.scala
@@ -3,264 +3,100 @@ package example
 import chisel3._
 
 import freechips.rocketchip.config.{Config}
-import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize, WithNBanks, WithInclusiveCache}
-
-import testchipip._
 
 // --------------
 // Rocket Configs
 // --------------
 
-class BaseRocketConfig extends Config(
+class RocketConfig extends Config(
+  new WithTop ++                                           // use default top
+  new WithBootROM ++                                       // use default bootrom
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++   // single rocket-core
+  new freechips.rocketchip.system.BaseConfig)              // "base" rocketchip system (implicitly creates Rocket cores)
+
+class HwachaRocketConfig extends Config(
+  new WithTop ++
   new WithBootROM ++
-  new freechips.rocketchip.system.DefaultConfig)
-
-class DefaultRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new BaseRocketConfig)
-
-class HwachaConfig extends Config(
-  new hwacha.DefaultHwachaConfig ++
-  new DefaultRocketConfig)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new hwacha.DefaultHwachaConfig ++                        // use Hwacha vector accelerator
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
 
 class RoccRocketConfig extends Config(
-  new WithRoccExample ++
-  new DefaultRocketConfig)
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithRoccExample ++    // use example RoCC-based accelerator
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class jtagRocketConfig extends Config(
+  new WithDTMTop ++                                        // use top with dtm
+  new freechips.rocketchip.subsystem.WithJtagDTM ++        // add jtag/DTM module to coreplex
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
 
 class PWMRocketConfig extends Config(
-  new WithPWMBoomRocketTop ++
-  new BaseRocketConfig)
+  new WithPWMTop ++                                        // use top with tilelink-controlled PWM
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
 
-class PWMAXI4RocketConfig extends Config(
-  new WithPWMAXI4BoomRocketTop ++
-  new BaseRocketConfig)
+class PWMRAXI4ocketConfig extends Config(
+  new WithPWMAXI4Top ++                                    // use top with axi4-controlled PWM
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
 
 class SimBlockDeviceRocketConfig extends Config(
-  new WithBlockDevice ++
-  new WithSimBlockDeviceBoomRocketTop ++
-  new BaseRocketConfig)
+  new testchipip.WithBlockDevice ++                        // add block-device module to peripherybus
+  new WithSimBlockDeviceTop ++                             // use top with block-device IOs and connect to simblockdevice
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
 
 class BlockDeviceModelRocketConfig extends Config(
-  new WithBlockDevice ++
-  new WithBlockDeviceModelBoomRocketTop ++
-  new BaseRocketConfig)
+  new testchipip.WithBlockDevice ++                        // add block-device module to periphery bus
+  new WithBlockDeviceModelTop ++                           // use top with block-device IOs and connect to a blockdevicemodel
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
 
 class GPIORocketConfig extends Config(
-  new WithGPIO ++
-  new WithGPIOBoomRocketTop ++
-  new BaseRocketConfig)
+  new WithGPIO ++                                          // add GPIOs to the peripherybus
+  new WithGPIOTop ++                                       // use top with GPIOs
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
 
 class DualCoreRocketConfig extends Config(
-  new WithNBigCores(2) ++
-  new DefaultRocketConfig)
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNBigCores(2) ++   // dual-core (2 RocketTiles)
+  new freechips.rocketchip.system.BaseConfig)
 
 class RV32RocketConfig extends Config(
-  new WithRV32 ++
-  new DefaultRocketConfig)
-
-class GB1MemoryConfig extends Config(
-  new WithExtMemSize((1<<30) * 1L) ++
-  new DefaultRocketConfig)
-
-class RocketL2Config extends Config(
-  new WithInclusiveCache ++
-  new DefaultRocketConfig)
-
-class HwachaL2Config extends Config(
-  new hwacha.DefaultHwachaConfig ++
-  new WithInclusiveCache ++
-  new DefaultRocketConfig)
-
-// ------------
-// BOOM Configs
-// ------------
-
-class BaseBoomConfig extends Config(
+  new WithTop ++
   new WithBootROM ++
-  new boom.common.LargeBoomConfig)
-
-class SmallBaseBoomConfig extends Config(
-  new WithBootROM ++
-  new boom.common.SmallBoomConfig)
-
-class DefaultBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new BaseBoomConfig)
-
-class SmallDefaultBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new SmallBaseBoomConfig)
-
-class HwachaBoomConfig extends Config(
-  new hwacha.DefaultHwachaConfig ++
-  new DefaultBoomConfig)
-
-class RoccBoomConfig extends Config(
-  new WithRoccExample ++
-  new DefaultBoomConfig)
-
-class PWMBoomConfig extends Config(
-  new WithPWMBoomRocketTop ++
-  new BaseBoomConfig)
-
-class PWMAXI4BoomConfig extends Config(
-  new WithPWMAXI4BoomRocketTop ++
-  new BaseBoomConfig)
-
-class SimBlockDeviceBoomConfig extends Config(
-  new WithBlockDevice ++
-  new WithSimBlockDeviceBoomRocketTop ++
-  new BaseBoomConfig)
-
-class BlockDeviceModelBoomConfig extends Config(
-  new WithBlockDevice ++
-  new WithBlockDeviceModelBoomRocketTop ++
-  new BaseBoomConfig)
-
-class GPIOBoomConfig extends Config(
-  new WithGPIO ++
-  new WithGPIOBoomRocketTop ++
-  new BaseBoomConfig)
-
-/**
- * Slightly different looking configs since we need to override
- * the `WithNBoomCores` with the DefaultBoomConfig params
- */
-class DualCoreBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.WithRVC ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.BaseBoomConfig ++
-  new boom.common.WithNBoomCores(2) ++
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class DualCoreSmallBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.WithRVC ++
-  new boom.common.WithSmallBooms ++
-  new boom.common.BaseBoomConfig ++
-  new boom.common.WithNBoomCores(2) ++
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class RV32UnifiedBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.SmallRV32UnifiedBoomConfig)
-
-class BoomL2Config extends Config(
-  new WithInclusiveCache ++
-  new SmallDefaultBoomConfig)
-
-// ---------------------
-// BOOM and Rocket Configs
-// ---------------------
-
-class BaseBoomAndRocketConfig extends Config(
-  new WithBootROM ++
-  new boom.common.WithRenumberHarts ++
-  new boom.common.WithRVC ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.BaseBoomConfig ++
-  new boom.common.WithNBoomCores(1) ++
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithRV32 ++           // set RocketTiles to be 32-bit
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
 
-class SmallBaseBoomAndRocketConfig extends Config(
+class GB1MemoryRocketConfig extends Config(
+  new WithTop ++
   new WithBootROM ++
-  new boom.common.WithRenumberHarts ++
-  new boom.common.WithRVC ++
-  new boom.common.WithSmallBooms ++
-  new boom.common.BaseBoomConfig ++
-  new boom.common.WithNBoomCores(1) ++
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 2GB simulated external memory
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
 
-class DefaultBoomAndRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new BaseBoomAndRocketConfig)
-
-class SmallDefaultBoomAndRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new SmallBaseBoomAndRocketConfig)
-
-class HwachaBoomAndRocketConfig extends Config(
-  new hwacha.DefaultHwachaConfig ++
-  new DefaultBoomAndRocketConfig)
-
-class RoccBoomAndRocketConfig extends Config(
-  new WithRoccExample ++
-  new DefaultBoomAndRocketConfig)
-
-class PWMBoomAndRocketConfig extends Config(
-  new WithPWMBoomRocketTop ++
-  new BaseBoomAndRocketConfig)
-
-class PWMAXI4BoomAndRocketConfig extends Config(
-  new WithPWMAXI4BoomRocketTop ++
-  new BaseBoomAndRocketConfig)
-
-class SimBlockDeviceBoomAndRocketConfig extends Config(
-  new WithBlockDevice ++
-  new WithSimBlockDeviceBoomRocketTop ++
-  new BaseBoomAndRocketConfig)
-
-class BlockDeviceModelBoomAndRocketConfig extends Config(
-  new WithBlockDevice ++
-  new WithBlockDeviceModelBoomRocketTop ++
-  new BaseBoomAndRocketConfig)
-
-class GPIOBoomAndRocketConfig extends Config(
-  new WithGPIO ++
-  new WithGPIOBoomRocketTop ++
-  new BaseBoomAndRocketConfig)
-
-class DualCoreBoomAndOneRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.WithRenumberHarts ++
-  new boom.common.WithRVC ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.BaseBoomConfig ++
-  new boom.common.WithNBoomCores(2) ++
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class DualBoomAndOneHwachaRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new WithMultiRoCC ++
-  new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket
-  new boom.common.WithRenumberHarts(rocketFirst = true) ++
-  new hwacha.DefaultHwachaConfig ++
-  new boom.common.WithRVC ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.BaseBoomConfig ++
-  new boom.common.WithNBoomCores(2) ++
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class RV32BoomAndRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.WithRenumberHarts ++
-  new boom.common.WithBoomRV32 ++
-  new boom.common.WithRVC ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.BaseBoomConfig ++
-  new boom.common.WithNBoomCores(1) ++
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
-  new freechips.rocketchip.subsystem.WithRV32 ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class DualCoreRocketL2Config extends Config(
-  new WithInclusiveCache ++
-  new DualCoreRocketConfig)
diff --git a/generators/example/src/main/scala/HeteroConfigs.scala b/generators/example/src/main/scala/HeteroConfigs.scala
new file mode 100644
index 00000000..898991d7
--- /dev/null
+++ b/generators/example/src/main/scala/HeteroConfigs.scala
@@ -0,0 +1,84 @@
+package example
+
+import chisel3._
+
+import freechips.rocketchip.config.{Config}
+
+// ---------------------
+// Heterogenous Configs
+// ---------------------
+
+class LargeBoomAndRocketConfig extends Config(
+  new WithTop ++                                          // default top
+  new WithBootROM ++                                      // default bootrom
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive l2
+  new boom.common.WithRenumberHarts ++                    // avoid hartid overlap
+  new boom.common.WithLargeBooms ++                       // 3-wide boom
+  new boom.common.WithNBoomCores(1) ++                    // single-core boom
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++  // single-core rocket
+  new freechips.rocketchip.system.BaseConfig)             // "Base" rocketchip system
+
+class HwachaLargeBoomAndHwachaRocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new hwacha.DefaultHwachaConfig ++                      // add hwacha to all harts
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class RoccLargeBoomAndRoccRocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithRoccExample ++  // add example rocc accelerator to all harts
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class DualLargeBoomAndRocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(2) ++                  // 2-boom cores
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class DualLargeBoomAndHwachaRocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new WithMultiRoCC ++                                  // support heterogeneous rocc
+  new WithMultiRoCCHwacha(2) ++                         // put hwacha on hart-2 (rocket)
+  new boom.common.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(2) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class LargeBoomAndRV32RocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithRV32 ++        // use 32-bit rocket
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class DualLargeBoomAndDualRocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(2) ++                   // 2 boom cores
+  new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores
+  new freechips.rocketchip.system.BaseConfig)
diff --git a/generators/example/src/main/scala/Subsystem.scala b/generators/example/src/main/scala/Subsystem.scala
new file mode 100644
index 00000000..7888bc4f
--- /dev/null
+++ b/generators/example/src/main/scala/Subsystem.scala
@@ -0,0 +1,108 @@
+//******************************************************************************
+// Copyright (c) 2019 - 2019, The Regents of the University of California (Regents).
+// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
+//------------------------------------------------------------------------------
+
+package example
+
+import chisel3._
+import chisel3.internal.sourceinfo.{SourceInfo}
+
+import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt}
+import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree}
+import freechips.rocketchip.tile._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.interrupts._
+import freechips.rocketchip.util._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.amba.axi4._
+
+import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey}
+
+
+trait HasBoomAndRocketTiles extends HasTiles
+  with CanHavePeripheryPLIC
+  with CanHavePeripheryCLINT
+  with HasPeripheryDebug
+{ this: BaseSubsystem =>
+
+  val module: HasBoomAndRocketTilesModuleImp
+
+  protected val rocketTileParams = p(RocketTilesKey)
+  protected val boomTileParams = p(BoomTilesKey)
+  // crossing can either be per tile or global (aka only 1 crossing specified)
+  private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size)
+  private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size)
+
+  // Make a tile and wire its nodes into the system,
+  // according to the specified type of clock crossing.
+  // Note that we also inject new nodes into the tile itself,
+  // also based on the crossing type.
+  val rocketTiles = rocketTileParams.zip(rocketCrossings).map { case (tp, crossing) =>
+    val rocket = LazyModule(new RocketTile(tp, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
+
+    connectMasterPortsToSBus(rocket, crossing)
+    connectSlavePortsToCBus(rocket, crossing)
+
+    def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(rocket.rocketLogicalTree.getOMInterruptTargets)
+    LogicalModuleTree.add(logicalTreeNode, rocket.rocketLogicalTree)
+
+    rocket
+  }
+
+  val boomTiles = boomTileParams.zip(boomCrossings).map { case (tp, crossing) =>
+    val boom = LazyModule(new BoomTile(tp, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
+
+    connectMasterPortsToSBus(boom, crossing)
+    connectSlavePortsToCBus(boom, crossing)
+
+    def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(boom.rocketLogicalTree.getOMInterruptTargets)
+    LogicalModuleTree.add(logicalTreeNode, boom.rocketLogicalTree)
+
+    boom
+  }
+
+  // combine tiles and connect interrupts based on the order of harts
+  val boomAndRocketTiles = (rocketTiles ++ boomTiles).sortWith(_.tileParams.hartId < _.tileParams.hartId).map {
+    tile => {
+      connectInterrupts(tile, Some(debug), clintOpt, plicOpt)
+
+      tile
+    }
+  }
+
+  def coreMonitorBundles = (rocketTiles map { t => t.module.core.rocketImpl.coreMonitorBundle}).toList ++
+                             (boomTiles map { t => t.module.core.coreMonitorBundle}).toList
+}
+
+trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp
+  with HasPeripheryDebugModuleImp
+{
+  val outer: HasBoomAndRocketTiles
+}
+
+class Subsystem(implicit p: Parameters) extends BaseSubsystem
+  with HasBoomAndRocketTiles
+{
+  val tiles = boomAndRocketTiles
+  override lazy val module = new SubsystemModuleImp(this)
+
+  def getOMInterruptDevice(resourceBindingsMap: ResourceBindingsMap): Seq[OMInterrupt] = Nil
+}
+
+class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
+  with HasResetVectorWire
+  with HasBoomAndRocketTilesModuleImp
+{
+  tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
+    wire.hartid := i.U
+    wire.reset_vector := global_reset_vector
+  }
+
+  // create file with boom params
+  ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n"))
+}
diff --git a/generators/example/src/main/scala/System.scala b/generators/example/src/main/scala/System.scala
new file mode 100644
index 00000000..1c62bf51
--- /dev/null
+++ b/generators/example/src/main/scala/System.scala
@@ -0,0 +1,63 @@
+//******************************************************************************
+// Copyright (c) 2019 - 2019, The Regents of the University of California (Regents).
+// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
+//------------------------------------------------------------------------------
+
+package example
+
+import chisel3._
+
+import freechips.rocketchip.config.{Parameters}
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.util.{DontTouch}
+
+// ---------------------------------------------------------------------
+// Base system that uses the debug test module (dtm) to bringup the core
+// ---------------------------------------------------------------------
+
+/**
+ * Base top with periphery devices and ports, and a BOOM + Rocket subsystem
+ */
+class System(implicit p: Parameters) extends Subsystem
+  with HasAsyncExtInterrupts
+  with CanHaveMasterAXI4MemPort
+  with CanHaveMasterAXI4MMIOPort
+  with CanHaveSlaveAXI4Port
+  with HasPeripheryBootROM
+{
+  override lazy val module = new SystemModule(this)
+
+  // The sbus masters the cbus; here we convert TL-UH -> TL-UL
+  sbus.crossToBus(cbus, NoCrossing)
+
+  // The cbus masters the pbus; which might be clocked slower
+  cbus.crossToBus(pbus, SynchronousCrossing())
+
+  // The fbus masters the sbus; both are TL-UH or TL-C
+  FlipRendering { implicit p =>
+    sbus.crossFromBus(fbus, SynchronousCrossing())
+  }
+
+  // The sbus masters the mbus; here we convert TL-C -> TL-UH
+  private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key)
+  private val (in, out, halt) = coherenceManager(this)
+  if (nBanks != 0) {
+    sbus.coupleTo("coherence_manager") { in :*= _ }
+    mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out }
+  }
+}
+
+/**
+ * Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem
+ */
+class SystemModule[+L <: System](_outer: L) extends SubsystemModuleImp(_outer)
+  with HasRTCModuleImp
+  with HasExtInterruptsModuleImp
+  with CanHaveMasterAXI4MemPortModuleImp
+  with CanHaveMasterAXI4MMIOPortModuleImp
+  with CanHaveSlaveAXI4PortModuleImp
+  with HasPeripheryBootROMModuleImp
+  with DontTouch
diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala
index 778fcc81..61807f2e 100644
--- a/generators/example/src/main/scala/TestHarness.scala
+++ b/generators/example/src/main/scala/TestHarness.scala
@@ -14,8 +14,8 @@ import freechips.rocketchip.devices.debug.{Debug}
 // BOOM and/or Rocket Test Harness
 // -------------------------------
 
-case object BuildBoomRocketTop extends Field[(Clock, Bool, Parameters) => BoomRocketTopModule[BoomRocketTop]]
-case object BuildBoomRocketTopWithDTM extends Field[(Clock, Bool, Parameters) => BoomRocketTopWithDTMModule[BoomRocketTopWithDTM]]
+case object BuildTop extends Field[(Clock, Bool, Parameters) => TopModule[Top]]
+case object BuildTopWithDTM extends Field[(Clock, Bool, Parameters) => TopWithDTMModule[TopWithDTM]]
 
 /**
  * Test harness using TSI to bringup the system
@@ -28,7 +28,7 @@ class TestHarness(implicit val p: Parameters) extends Module {
   // force Chisel to rename module
   override def desiredName = "TestHarness"
 
-  val dut = p(BuildBoomRocketTop)(clock, reset.toBool, p)
+  val dut = p(BuildTop)(clock, reset.toBool, p)
 
   dut.debug := DontCare
   dut.connectSimAXIMem()
@@ -63,7 +63,7 @@ class TestHarnessWithDTM(implicit p: Parameters) extends Module
   // force Chisel to rename module
   override def desiredName = "TestHarness"
 
-  val dut = p(BuildBoomRocketTopWithDTM)(clock, reset.toBool, p)
+  val dut = p(BuildTopWithDTM)(clock, reset.toBool, p)
 
   dut.reset := reset.asBool | dut.debug.ndreset
   dut.connectSimAXIMem()
diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala
index b861fdec..bfb03e0c 100644
--- a/generators/example/src/main/scala/Top.scala
+++ b/generators/example/src/main/scala/Top.scala
@@ -16,63 +16,63 @@ import sifive.blocks.devices.gpio._
 // BOOM and/or Rocket Top Level Systems
 // ------------------------------------
 
-class BoomRocketTop(implicit p: Parameters) extends boom.system.BoomRocketSystem
+class Top(implicit p: Parameters) extends System
   with HasNoDebug
   with HasPeripherySerial {
-  override lazy val module = new BoomRocketTopModule(this)
+  override lazy val module = new TopModule(this)
 }
 
-class BoomRocketTopModule[+L <: BoomRocketTop](l: L) extends boom.system.BoomRocketSystemModule(l)
+class TopModule[+L <: Top](l: L) extends SystemModule(l)
   with HasNoDebugModuleImp
   with HasPeripherySerialModuleImp
   with DontTouch
 
 //---------------------------------------------------------------------------------------------------------
 
-class BoomRocketTopWithPWMTL(implicit p: Parameters) extends BoomRocketTop
+class TopWithPWMTL(implicit p: Parameters) extends Top
   with HasPeripheryPWMTL {
-  override lazy val module = new BoomRocketTopWithPWMTLModule(this)
+  override lazy val module = new TopWithPWMTLModule(this)
 }
 
-class BoomRocketTopWithPWMTLModule(l: BoomRocketTopWithPWMTL) extends BoomRocketTopModule(l)
+class TopWithPWMTLModule(l: TopWithPWMTL) extends TopModule(l)
   with HasPeripheryPWMTLModuleImp
 
 //---------------------------------------------------------------------------------------------------------
 
-class BoomRocketTopWithPWMAXI4(implicit p: Parameters) extends BoomRocketTop
+class TopWithPWMAXI4(implicit p: Parameters) extends Top
   with HasPeripheryPWMAXI4 {
-  override lazy val module = new BoomRocketTopWithPWMAXI4Module(this)
+  override lazy val module = new TopWithPWMAXI4Module(this)
 }
 
-class BoomRocketTopWithPWMAXI4Module(l: BoomRocketTopWithPWMAXI4) extends BoomRocketTopModule(l)
+class TopWithPWMAXI4Module(l: TopWithPWMAXI4) extends TopModule(l)
   with HasPeripheryPWMAXI4ModuleImp
 
 //---------------------------------------------------------------------------------------------------------
 
-class BoomRocketTopWithBlockDevice(implicit p: Parameters) extends BoomRocketTop
+class TopWithBlockDevice(implicit p: Parameters) extends Top
   with HasPeripheryBlockDevice {
-  override lazy val module = new BoomRocketTopWithBlockDeviceModule(this)
+  override lazy val module = new TopWithBlockDeviceModule(this)
 }
 
-class BoomRocketTopWithBlockDeviceModule(l: BoomRocketTopWithBlockDevice) extends BoomRocketTopModule(l)
+class TopWithBlockDeviceModule(l: TopWithBlockDevice) extends TopModule(l)
   with HasPeripheryBlockDeviceModuleImp
 
 //---------------------------------------------------------------------------------------------------------
 
-class BoomRocketTopWithGPIO(implicit p: Parameters) extends BoomRocketTop
-    with HasPeripheryGPIO {
-  override lazy val module = new BoomRocketTopWithGPIOModule(this)
+class TopWithGPIO(implicit p: Parameters) extends Top
+  with HasPeripheryGPIO {
+  override lazy val module = new TopWithGPIOModule(this)
 }
 
-class BoomRocketTopWithGPIOModule(l: BoomRocketTopWithGPIO)
-  extends BoomRocketTopModule(l)
+class TopWithGPIOModule(l: TopWithGPIO)
+  extends TopModule(l)
   with HasPeripheryGPIOModuleImp
 
 //---------------------------------------------------------------------------------------------------------
 
-class BoomRocketTopWithDTM(implicit p: Parameters) extends boom.system.BoomRocketSystem
+class TopWithDTM(implicit p: Parameters) extends System
 {
-  override lazy val module = new BoomRocketTopWithDTMModule(this)
+  override lazy val module = new TopWithDTMModule(this)
 }
 
-class BoomRocketTopWithDTMModule[+L <: BoomRocketTopWithDTM](l: L) extends boom.system.BoomRocketSystemModule(l)
+class TopWithDTMModule[+L <: TopWithDTM](l: L) extends SystemModule(l)
diff --git a/generators/utilities/src/main/scala/TestSuites.scala b/generators/utilities/src/main/scala/TestSuites.scala
index ab0ff8d5..725e1e69 100644
--- a/generators/utilities/src/main/scala/TestSuites.scala
+++ b/generators/utilities/src/main/scala/TestSuites.scala
@@ -8,7 +8,7 @@ import freechips.rocketchip.config.{Parameters}
 import freechips.rocketchip.util.{GeneratorApp}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
 
-import boom.system.{BoomTilesKey}
+import boom.common.{BoomTilesKey}
 
 /**
  * A set of pre-chosen regression tests
diff --git a/variables.mk b/variables.mk
index ca0f8fc9..ddf05da8 100644
--- a/variables.mk
+++ b/variables.mk
@@ -32,11 +32,11 @@ ifeq ($(SUB_PROJECT),example)
 	MODEL             ?= TestHarness
 	VLOG_MODEL        ?= TestHarness
 	MODEL_PACKAGE     ?= $(SBT_PROJECT)
-	CONFIG            ?= DefaultRocketConfig
+	CONFIG            ?= RocketConfig
 	CONFIG_PACKAGE    ?= $(SBT_PROJECT)
 	GENERATOR_PACKAGE ?= $(SBT_PROJECT)
 	TB                ?= TestDriver
-	TOP               ?= BoomRocketTop
+	TOP               ?= Top
 endif
 # for Rocket-chip developers
 ifeq ($(SUB_PROJECT),rocketchip)

From ba3deac1de165f3bbbc660666d9fddc40521ca4e Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Mon, 26 Aug 2019 14:50:46 -0700
Subject: [PATCH 02/16] Update CI with new config names

---
 .circleci/config.yml  | 62 -------------------------------------------
 .circleci/defaults.sh |  7 +++--
 2 files changed, 3 insertions(+), 66 deletions(-)

diff --git a/.circleci/config.yml b/.circleci/config.yml
index 1ae4a000..107749e5 100644
--- a/.circleci/config.yml
+++ b/.circleci/config.yml
@@ -117,35 +117,6 @@ jobs:
                 key: example-{{ .Branch }}-{{ .Revision }}
                 paths:
                     - "/home/riscvuser/project"
-    prepare-boomexample:
-        docker:
-            - image: riscvboom/riscvboom-images:0.0.10
-        environment:
-            JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
-            TERM: dumb
-        steps:
-            - add_ssh_keys:
-                fingerprints:
-                    - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e"
-            - checkout
-            - run:
-                name: Create hash of toolchains
-                command: |
-                    .circleci/create-hash.sh
-            - restore_cache:
-                keys:
-                    - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
-            - restore_cache:
-                keys:
-                    - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
-            - run:
-                name: Building the boomexample subproject using Verilator
-                command: .circleci/do-rtl-build.sh boomexample
-                no_output_timeout: 120m
-            - save_cache:
-                key: boomexample-{{ .Branch }}-{{ .Revision }}
-                paths:
-                    - "/home/riscvuser/project"
     prepare-boomrocketexample:
         docker:
             - image: riscvboom/riscvboom-images:0.0.10
@@ -315,30 +286,6 @@ jobs:
             - run:
                 name: Run example tests
                 command: .circleci/run-tests.sh example
-    boomexample-run-tests:
-        docker:
-            - image: riscvboom/riscvboom-images:0.0.10
-        environment:
-            JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
-            TERM: dumb
-        steps:
-            - checkout
-            - run:
-                name: Create hash of toolchains
-                command: |
-                    .circleci/create-hash.sh
-            - restore_cache:
-                keys:
-                    - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
-            - restore_cache:
-                keys:
-                    - boomexample-{{ .Branch }}-{{ .Revision }}
-            - restore_cache:
-                keys:
-                    - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
-            - run:
-                name: Run boomexample tests
-                command: .circleci/run-tests.sh boomexample
     boomrocketexample-run-tests:
         docker:
             - image: riscvboom/riscvboom-images:0.0.10
@@ -468,11 +415,6 @@ workflows:
                     - install-riscv-toolchain
                     - install-verilator
 
-            - prepare-boomexample:
-                requires:
-                    - install-riscv-toolchain
-                    - install-verilator
-
             - prepare-boomrocketexample:
                 requires:
                     - install-riscv-toolchain
@@ -505,10 +447,6 @@ workflows:
                 requires:
                     - prepare-example
 
-            - boomexample-run-tests:
-                requires:
-                    - prepare-boomexample
-
             - boomrocketexample-run-tests:
                 requires:
                     - prepare-boomrocketexample
diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh
index 439c4177..fb7a3571 100755
--- a/.circleci/defaults.sh
+++ b/.circleci/defaults.sh
@@ -36,9 +36,8 @@ LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verilator
 # key value store to get the build strings
 declare -A mapping
 mapping["example"]="SUB_PROJECT=example"
-mapping["boomexample"]="SUB_PROJECT=example CONFIG=DefaultBoomConfig"
-mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=DefaultBoomAndRocketConfig"
+mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=LargeBoomAndRocketConfig"
 mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig"
 mapping["rocketchip"]="SUB_PROJECT=rocketchip"
-mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig TOP=BoomRocketTopWithBlockDevice"
-mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaL2Config GENERATOR_PACKAGE=hwacha"
+mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig TOP=TopWithBlockDevice"
+mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig GENERATOR_PACKAGE=hwacha"

From 19282fd438d376e2dc11ca5b2d2603d117d22b9e Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Mon, 26 Aug 2019 14:51:20 -0700
Subject: [PATCH 03/16] Update FireChip with the new locations for subsystem

---
 generators/firechip/src/main/scala/Generator.scala     |  4 ++--
 generators/firechip/src/main/scala/TargetConfigs.scala |  2 +-
 generators/firechip/src/main/scala/Targets.scala       | 10 +++++-----
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala
index 0dd0e1eb..7f8c796a 100644
--- a/generators/firechip/src/main/scala/Generator.scala
+++ b/generators/firechip/src/main/scala/Generator.scala
@@ -27,8 +27,8 @@ trait HasTestSuites {
       "rv64ud-v-fadd",
       "rv64uf-v-fadd",
       "rv64um-v-mul",
-      // "rv64mi-p-breakpoint", // Not implemented in BOOM
-      // "rv64uc-v-rvc", // Not implemented in BOOM
+      "rv64mi-p-breakpoint",
+      "rv64uc-v-rvc",
       "rv64ud-v-structural",
       "rv64si-p-wfi",
       "rv64um-v-divw",
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index c81fe843..3795784b 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink.BootROMParams
 import freechips.rocketchip.devices.debug.DebugModuleParams
-import boom.system.BoomTilesKey
+import boom.common.BoomTilesKey
 import testchipip.{WithBlockDevice, BlockDeviceKey, BlockDeviceConfig}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import icenet._
diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala
index 7f8bb830..8f122a2c 100644
--- a/generators/firechip/src/main/scala/Targets.scala
+++ b/generators/firechip/src/main/scala/Targets.scala
@@ -11,7 +11,7 @@ import freechips.rocketchip.util.{HeterogeneousBag}
 import freechips.rocketchip.amba.axi4.AXI4Bundle
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy.LazyModule
-import boom.system.{BoomRocketSubsystem, BoomRocketSubsystemModuleImp}
+import example.{Subsystem, SubsystemModuleImp}
 import icenet._
 import testchipip._
 import testchipip.SerialAdapter.SERIAL_IF_WIDTH
@@ -80,7 +80,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod
     with HasTraceIOImp
 
 
-class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem
+class FireBoom(implicit p: Parameters) extends Subsystem
     with HasHierarchicalBusTopology
     with CanHaveFASEDOptimizedMasterAXI4MemPort
     with HasPeripheryBootROM
@@ -94,7 +94,7 @@ class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem
   override lazy val module = new FireBoomModuleImp(this)
 }
 
-class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleImp(l)
+class FireBoomModuleImp[+L <: FireBoom](l: L) extends SubsystemModuleImp(l)
     with HasRTCModuleImp
     with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
@@ -106,7 +106,7 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleI
     with HasTraceIOImp
     with ExcludeInvalidBoomAssertions
 
-class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem
+class FireBoomNoNIC(implicit p: Parameters) extends Subsystem
     with HasHierarchicalBusTopology
     with CanHaveFASEDOptimizedMasterAXI4MemPort
     with HasPeripheryBootROM
@@ -119,7 +119,7 @@ class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem
   override lazy val module = new FireBoomNoNICModuleImp(this)
 }
 
-class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomRocketSubsystemModuleImp(l)
+class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends SubsystemModuleImp(l)
     with HasRTCModuleImp
     with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp

From 832d5585172f46416afbd7fa80e19298eb6cd45a Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Mon, 26 Aug 2019 15:56:51 -0700
Subject: [PATCH 04/16] Update FireChip reference to boom configs

---
 generators/example/src/main/scala/Configs.scala        | 2 +-
 generators/firechip/src/main/scala/TargetConfigs.scala | 6 ++++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala
index 5004e6ee..ede2701b 100644
--- a/generators/example/src/main/scala/Configs.scala
+++ b/generators/example/src/main/scala/Configs.scala
@@ -13,7 +13,7 @@ class RocketConfig extends Config(
   new WithBootROM ++                                       // use default bootrom
   new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++   // single rocket-core
-  new freechips.rocketchip.system.BaseConfig)              // "base" rocketchip system (implicitly creates Rocket cores)
+  new freechips.rocketchip.system.BaseConfig)              // "base" rocketchip system
 
 class HwachaRocketConfig extends Config(
   new WithTop ++
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index 3795784b..85c82753 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -136,8 +136,10 @@ class FireSimBoomConfig extends Config(
   new WithBlockDevice ++
   new WithBoomL2TLBs(1024) ++
   new WithoutClockGating ++
-  // Using a small config because it has 64-bit system bus, and compiles quickly
-  new boom.common.SmallBoomConfig)
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig
+)
 
 // A safer implementation than the one in BOOM in that it
 // duplicates whatever BOOMTileKey.head is present N times. This prevents

From 93c3a2cd723816f1fa7403db4ce2ba717b9b110e Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Mon, 26 Aug 2019 16:29:54 -0700
Subject: [PATCH 05/16] Rename Configs -> RocketConfigs

---
 .../example/src/main/scala/{Configs.scala => RocketConfigs.scala} | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename generators/example/src/main/scala/{Configs.scala => RocketConfigs.scala} (100%)

diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/RocketConfigs.scala
similarity index 100%
rename from generators/example/src/main/scala/Configs.scala
rename to generators/example/src/main/scala/RocketConfigs.scala

From 939ce4ea175c2c5788c8abb78dc134ad76d42d88 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Mon, 26 Aug 2019 16:31:10 -0700
Subject: [PATCH 06/16] Fix Config comments

---
 .../example/src/main/scala/BoomConfigs.scala     |  4 ++--
 .../example/src/main/scala/HeteroConfigs.scala   | 16 ++++++++--------
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/generators/example/src/main/scala/BoomConfigs.scala b/generators/example/src/main/scala/BoomConfigs.scala
index c97154aa..7da54ffa 100644
--- a/generators/example/src/main/scala/BoomConfigs.scala
+++ b/generators/example/src/main/scala/BoomConfigs.scala
@@ -11,10 +11,10 @@ import freechips.rocketchip.config.{Config}
 class SmallBoomConfig extends Config(
   new WithTop ++                                            // use normal top
   new WithBootROM ++                                        // use testchipip bootrom
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++  // use Sifive L2 cache
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++  // use SiFive L2 cache
   new boom.common.WithSmallBooms ++                         // 1-wide BOOM
   new boom.common.WithNBoomCores(1) ++                      // single-core
-  new freechips.rocketchip.system.BaseConfig)               // "Base" rocketchip system
+  new freechips.rocketchip.system.BaseConfig)               // "base" rocketchip system
 
 class MediumBoomConfig extends Config(
   new WithTop ++
diff --git a/generators/example/src/main/scala/HeteroConfigs.scala b/generators/example/src/main/scala/HeteroConfigs.scala
index 898991d7..8c966bc2 100644
--- a/generators/example/src/main/scala/HeteroConfigs.scala
+++ b/generators/example/src/main/scala/HeteroConfigs.scala
@@ -9,14 +9,14 @@ import freechips.rocketchip.config.{Config}
 // ---------------------
 
 class LargeBoomAndRocketConfig extends Config(
-  new WithTop ++                                          // default top
-  new WithBootROM ++                                      // default bootrom
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive l2
-  new boom.common.WithRenumberHarts ++                    // avoid hartid overlap
-  new boom.common.WithLargeBooms ++                       // 3-wide boom
-  new boom.common.WithNBoomCores(1) ++                    // single-core boom
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++  // single-core rocket
-  new freechips.rocketchip.system.BaseConfig)             // "Base" rocketchip system
+  new WithTop ++                                           // default top
+  new WithBootROM ++                                       // default bootrom
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use SiFive l2
+  new boom.common.WithRenumberHarts ++                     // avoid hartid overlap
+  new boom.common.WithLargeBooms ++                        // 3-wide boom
+  new boom.common.WithNBoomCores(1) ++                     // single-core boom
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++   // single-core rocket
+  new freechips.rocketchip.system.BaseConfig)              // "base" rocketchip system
 
 class HwachaLargeBoomAndHwachaRocketConfig extends Config(
   new WithTop ++

From f221c8f26e8e47d4f192f9ed8cb74ad748289751 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Mon, 26 Aug 2019 20:15:01 -0700
Subject: [PATCH 07/16] Bump boomrocket example CI build time

---
 .circleci/config.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.circleci/config.yml b/.circleci/config.yml
index 107749e5..77a813ee 100644
--- a/.circleci/config.yml
+++ b/.circleci/config.yml
@@ -141,7 +141,7 @@ jobs:
             - run:
                 name: Building the boomrocketexample subproject using Verilator
                 command: .circleci/do-rtl-build.sh boomrocketexample
-                no_output_timeout: 120m
+                no_output_timeout: 240m
             - save_cache:
                 key: boomrocketexample-{{ .Branch }}-{{ .Revision }}
                 paths:

From 20b6737889dd4b90cf02daa54d305a55c821d1a8 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Mon, 26 Aug 2019 23:28:35 -0700
Subject: [PATCH 08/16] Add remaining configs for BOOM CI

---
 generators/example/src/main/scala/BoomConfigs.scala   |  1 +
 generators/example/src/main/scala/HeteroConfigs.scala | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/generators/example/src/main/scala/BoomConfigs.scala b/generators/example/src/main/scala/BoomConfigs.scala
index 7da54ffa..c6521619 100644
--- a/generators/example/src/main/scala/BoomConfigs.scala
+++ b/generators/example/src/main/scala/BoomConfigs.scala
@@ -61,6 +61,7 @@ class SmallRV32UnifiedBoomConfig extends Config(
   new WithTop ++
   new WithBootROM ++
   new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithoutBoomFPU ++                       // no floating point
   new boom.common.WithUnifiedMemIntIQs ++                 // use unified mem+int issue queues
   new boom.common.WithSmallBooms ++
   new boom.common.WithNBoomCores(1) ++
diff --git a/generators/example/src/main/scala/HeteroConfigs.scala b/generators/example/src/main/scala/HeteroConfigs.scala
index 8c966bc2..6f7cf8b1 100644
--- a/generators/example/src/main/scala/HeteroConfigs.scala
+++ b/generators/example/src/main/scala/HeteroConfigs.scala
@@ -18,6 +18,16 @@ class LargeBoomAndRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++   // single-core rocket
   new freechips.rocketchip.system.BaseConfig)              // "base" rocketchip system
 
+class SmallBoomAndRocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithRenumberHarts ++
+  new boom.common.WithSmallBooms ++                        // 1-wide boom
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
 class HwachaLargeBoomAndHwachaRocketConfig extends Config(
   new WithTop ++
   new WithBootROM ++

From 65003f86d0d5dbb37897666c7a9b06ad672079de Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Mon, 26 Aug 2019 23:29:50 -0700
Subject: [PATCH 09/16] Bump boom

---
 generators/boom | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/generators/boom b/generators/boom
index 793912ee..fb184407 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit 793912eef8a9f09c13bd791c33ba682350a6026a
+Subproject commit fb184407e93183353a3286a8c8ec9bf6660ff352

From 1d85dc32a07cc391ee1763f71eef17ba14f2b858 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 27 Aug 2019 12:00:50 -0700
Subject: [PATCH 10/16] Use HasHierarchicalBusTopology mixin

---
 .../example/src/main/scala/System.scala       | 20 +------------------
 1 file changed, 1 insertion(+), 19 deletions(-)

diff --git a/generators/example/src/main/scala/System.scala b/generators/example/src/main/scala/System.scala
index 1c62bf51..3b39ff80 100644
--- a/generators/example/src/main/scala/System.scala
+++ b/generators/example/src/main/scala/System.scala
@@ -22,6 +22,7 @@ import freechips.rocketchip.util.{DontTouch}
  * Base top with periphery devices and ports, and a BOOM + Rocket subsystem
  */
 class System(implicit p: Parameters) extends Subsystem
+  with HasHierarchicalBusTopology
   with HasAsyncExtInterrupts
   with CanHaveMasterAXI4MemPort
   with CanHaveMasterAXI4MMIOPort
@@ -29,25 +30,6 @@ class System(implicit p: Parameters) extends Subsystem
   with HasPeripheryBootROM
 {
   override lazy val module = new SystemModule(this)
-
-  // The sbus masters the cbus; here we convert TL-UH -> TL-UL
-  sbus.crossToBus(cbus, NoCrossing)
-
-  // The cbus masters the pbus; which might be clocked slower
-  cbus.crossToBus(pbus, SynchronousCrossing())
-
-  // The fbus masters the sbus; both are TL-UH or TL-C
-  FlipRendering { implicit p =>
-    sbus.crossFromBus(fbus, SynchronousCrossing())
-  }
-
-  // The sbus masters the mbus; here we convert TL-C -> TL-UH
-  private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key)
-  private val (in, out, halt) = coherenceManager(this)
-  if (nBanks != 0) {
-    sbus.coupleTo("coherence_manager") { in :*= _ }
-    mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out }
-  }
 }
 
 /**

From ca70c1544709843452d17d9045da30981f8101d6 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 27 Aug 2019 17:34:50 -0700
Subject: [PATCH 11/16] Remove TracedBoomConfig

---
 generators/example/src/main/scala/BoomConfigs.scala | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/generators/example/src/main/scala/BoomConfigs.scala b/generators/example/src/main/scala/BoomConfigs.scala
index c6521619..59654ea5 100644
--- a/generators/example/src/main/scala/BoomConfigs.scala
+++ b/generators/example/src/main/scala/BoomConfigs.scala
@@ -48,15 +48,6 @@ class DualSmallBoomConfig extends Config(
   new boom.common.WithNBoomCores(2) ++                      // dual-core
   new freechips.rocketchip.system.BaseConfig)
 
-class TracedSmallBoomConfig extends Config(
-  new WithTop ++
-  new WithBootROM ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new boom.common.WithTrace ++                             // enable trace port on BOOM
-  new boom.common.WithSmallBooms ++
-  new boom.common.WithNBoomCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
 class SmallRV32UnifiedBoomConfig extends Config(
   new WithTop ++
   new WithBootROM ++

From f1929a0da816fd0bcd84e47c46cdbd8975d44425 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 27 Aug 2019 18:05:24 -0700
Subject: [PATCH 12/16] Move System/Subsystem to utilities

---
 generators/example/src/main/scala/Top.scala                     | 2 ++
 generators/firechip/src/main/scala/Targets.scala                | 2 +-
 .../{example => utilities}/src/main/scala/Subsystem.scala       | 2 +-
 generators/{example => utilities}/src/main/scala/System.scala   | 2 +-
 4 files changed, 5 insertions(+), 3 deletions(-)
 rename generators/{example => utilities}/src/main/scala/Subsystem.scala (99%)
 rename generators/{example => utilities}/src/main/scala/System.scala (98%)

diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala
index bfb03e0c..19990817 100644
--- a/generators/example/src/main/scala/Top.scala
+++ b/generators/example/src/main/scala/Top.scala
@@ -10,6 +10,8 @@ import freechips.rocketchip.util.DontTouch
 
 import testchipip._
 
+import utilities.{System, SystemModule}
+
 import sifive.blocks.devices.gpio._
 
 // ------------------------------------
diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala
index 8f122a2c..7b6ea95c 100644
--- a/generators/firechip/src/main/scala/Targets.scala
+++ b/generators/firechip/src/main/scala/Targets.scala
@@ -11,7 +11,7 @@ import freechips.rocketchip.util.{HeterogeneousBag}
 import freechips.rocketchip.amba.axi4.AXI4Bundle
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy.LazyModule
-import example.{Subsystem, SubsystemModuleImp}
+import utilities.{Subsystem, SubsystemModuleImp}
 import icenet._
 import testchipip._
 import testchipip.SerialAdapter.SERIAL_IF_WIDTH
diff --git a/generators/example/src/main/scala/Subsystem.scala b/generators/utilities/src/main/scala/Subsystem.scala
similarity index 99%
rename from generators/example/src/main/scala/Subsystem.scala
rename to generators/utilities/src/main/scala/Subsystem.scala
index 7888bc4f..58bc342d 100644
--- a/generators/example/src/main/scala/Subsystem.scala
+++ b/generators/utilities/src/main/scala/Subsystem.scala
@@ -3,7 +3,7 @@
 // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
 //------------------------------------------------------------------------------
 
-package example
+package utilities
 
 import chisel3._
 import chisel3.internal.sourceinfo.{SourceInfo}
diff --git a/generators/example/src/main/scala/System.scala b/generators/utilities/src/main/scala/System.scala
similarity index 98%
rename from generators/example/src/main/scala/System.scala
rename to generators/utilities/src/main/scala/System.scala
index 3b39ff80..0eed6660 100644
--- a/generators/example/src/main/scala/System.scala
+++ b/generators/utilities/src/main/scala/System.scala
@@ -3,7 +3,7 @@
 // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
 //------------------------------------------------------------------------------
 
-package example
+package utilities
 
 import chisel3._
 

From 4de40d3863670fd4dc7e7359b2e163d09bb09ff6 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Wed, 28 Aug 2019 14:53:24 -0700
Subject: [PATCH 13/16] Update naming in docs

---
 docs/Advanced-Usage/DTM-Debugging.rst         |  6 +++---
 docs/Chipyard-Basics/Running-A-Simulation.rst |  6 ------
 docs/Customization/Heterogeneous-SoCs.rst     | 16 ++++++++--------
 docs/Simulation/Software-RTL-Simulators.rst   | 12 ++++++------
 4 files changed, 17 insertions(+), 23 deletions(-)

diff --git a/docs/Advanced-Usage/DTM-Debugging.rst b/docs/Advanced-Usage/DTM-Debugging.rst
index bf033fec..839e36a0 100644
--- a/docs/Advanced-Usage/DTM-Debugging.rst
+++ b/docs/Advanced-Usage/DTM-Debugging.rst
@@ -16,12 +16,12 @@ This involves specifying the SoC top-level to add a DTM as well as configuring t
 .. code-block:: scala
 
     class DTMBoomConfig extends Config(
-      new WithDTMBoomRocketTop ++
+      new WithDTMTop ++
       new WithBootROM ++
       new WithJtagDTM ++
       new boom.common.SmallBoomConfig)
 
-In this example, the ``WithDTMBoomRocketTop`` mixin specifies that the top-level SoC will instantiate a DTM.
+In this example, the ``WithDTMTop`` mixin specifies that the top-level SoC will instantiate a DTM.
 The ``WithJtagDTM`` will configure that instantiated DTM to use JTAG as the bringup method (note: this can be removed if you want a DTM-only bringup).
 The rest of the mixins specify the rest of the system (cores, accelerators, etc).
 
@@ -36,7 +36,7 @@ After creating the config, call the ``make`` command like the following:
     # or
     cd sims/vcs
 
-    make CONFIG=DTMBoomConfig TOP=BoomRocketTopWithDTM MODEL=TestHarnessWithDTM
+    make CONFIG=DTMBoomConfig TOP=TopWithDTM MODEL=TestHarnessWithDTM
 
 In this example, this will use the config that you previously specified, as well as set the other parameters that are needed to satisfy the build system.
 After that point, you should have a JTAG enabled simulation that you can attach to using OpenOCD and GDB!
diff --git a/docs/Chipyard-Basics/Running-A-Simulation.rst b/docs/Chipyard-Basics/Running-A-Simulation.rst
index 39128f30..7b3f0cc1 100644
--- a/docs/Chipyard-Basics/Running-A-Simulation.rst
+++ b/docs/Chipyard-Basics/Running-A-Simulation.rst
@@ -58,12 +58,6 @@ Therefore, in order to simulate a simple Rocket-based example system we can use:
 
     make SUB_PROJECT=example
 
-Alternatively, if we would like to simulate a simple BOOM-based example system we can use:
-
-.. code-block:: shell
-
-    make SUB_PROJECT=exampleboom
-
 Once the simulator has been constructed, we would like to run RISC-V programs on it.
 In the simulation directory, we will find an executable file called ``<...>-<package>-<config>``.
 We run this executable with our target RISC-V program as a command line argument in one of two ways.
diff --git a/docs/Customization/Heterogeneous-SoCs.rst b/docs/Customization/Heterogeneous-SoCs.rst
index 96a7e40e..c1a6a003 100644
--- a/docs/Customization/Heterogeneous-SoCs.rst
+++ b/docs/Customization/Heterogeneous-SoCs.rst
@@ -15,18 +15,18 @@ The following example shows a dual core BOOM with a single core Rocket.
 .. code-block:: scala
 
     class DualBoomAndOneRocketConfig extends Config(
-      new WithNormalBoomRocketTop ++
+      new WithTop ++
       new WithBootROM ++
       new boom.system.WithRenumberHarts ++
       new boom.common.WithRVC ++
-      new boom.common.DefaultBoomConfig ++
+      new boom.common.LargeBoomConfig ++
       new boom.system.WithNBoomCores(2) ++
       new freechips.rocketchip.subsystem.WithoutTLMonitors ++
       new freechips.rocketchip.subsystem.WithNBigCores(1) ++
       new freechips.rocketchip.system.BaseConfig)
 
 In this example, the ``WithNBoomCores`` and ``WithNBigCores`` mixins set up the default parameters for the multiple BOOM and Rocket cores, respectively.
-However, for BOOM, an extra mixin called ``DefaultBoomConfig`` is added to override the default parameters with a different set of more common default parameters.
+However, for BOOM, an extra mixin called ``LargeBoomConfig`` is added to override the default parameters with a different set of more common default parameters.
 This mixin applies to all BOOM cores in the system and changes the parameters for each.
 
 Great! Now you have a heterogeneous setup with BOOMs and Rockets.
@@ -62,7 +62,7 @@ Then you could use this new mixin like the following.
 .. code-block:: scala
 
     class SixCoreConfig extends Config(
-      new WithNormalBoomRocketTop ++
+      new WithTop ++
       new WithBootROM ++
       new WithHeterCoresSetup ++
       new freechips.rocketchip.system.BaseConfig)
@@ -78,12 +78,12 @@ An example of adding a Hwacha to all tiles in the system is below.
 .. code-block:: scala
 
     class DualBoomAndRocketWithHwachasConfig extends Config(
-      new WithNormalBoomRocketTop ++
+      new WithTop ++
       new WithBootROM ++
       new hwacha.DefaultHwachaConfig ++
       new boom.system.WithRenumberHarts ++
       new boom.common.WithRVC ++
-      new boom.common.DefaultBoomConfig ++
+      new boom.common.LargeBoomConfig ++
       new boom.system.WithNBoomCores(2) ++
       new freechips.rocketchip.subsystem.WithoutTLMonitors ++
       new freechips.rocketchip.subsystem.WithNBigCores(1) ++
@@ -103,14 +103,14 @@ An example is shown below with two BOOM cores, and one Rocket tile with a RoCC a
 .. code-block:: scala
 
     class DualBoomAndOneHwachaRocketConfig extends Config(
-      new WithNormalBoomRocketTop ++
+      new WithTop ++
       new WithBootROM ++
       new WithMultiRoCC ++
       new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket
       new boom.system.WithRenumberHarts(rocketFirst = true) ++
       new hwacha.DefaultHwachaConfig ++
       new boom.common.WithRVC ++
-      new boom.common.DefaultBoomConfig ++
+      new boom.common.LargeBoomConfig ++
       new boom.system.WithNBoomCores(2) ++
       new freechips.rocketchip.subsystem.WithoutTLMonitors ++
       new freechips.rocketchip.subsystem.WithNBigCores(1) ++
diff --git a/docs/Simulation/Software-RTL-Simulators.rst b/docs/Simulation/Software-RTL-Simulators.rst
index 89bd337c..5dd4e527 100644
--- a/docs/Simulation/Software-RTL-Simulators.rst
+++ b/docs/Simulation/Software-RTL-Simulators.rst
@@ -12,16 +12,16 @@ The Chipyard framework can download, build, and execute simulations using Verila
 To run a simulation using Verilator, perform the following steps:
 
 To compile the example design, run ``make`` in the ``sims/verilator`` directory.
-This will elaborate the ``DefaultRocketConfig`` in the example project.
+This will elaborate the ``RocketConfig`` in the example project.
 
-An executable called ``simulator-example-DefaultRocketConfig`` will be produced.
+An executable called ``simulator-example-RocketConfig`` will be produced.
 This executable is a simulator that has been compiled based on the design that was built.
 You can then use this executable to run any compatible RV64 code.
 For instance, to run one of the riscv-tools assembly tests.
 
 .. code-block:: shell
 
-    ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
+    ./simulator-example-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
 
 If you later create your own project, you can use environment variables to build an alternate configuration.
 
@@ -50,16 +50,16 @@ To run a simulation using VCS, perform the following steps:
 Make sure that the VCS simulator is on your ``PATH``.
 
 To compile the example design, run make in the ``sims/vcs`` directory.
-This will elaborate the ``DefaultRocketConfig`` in the example project.
+This will elaborate the ``RocketConfig`` in the example project.
 
-An executable called ``simulator-example-DefaultRocketConfig`` will be produced.
+An executable called ``simulator-example-RocketConfig`` will be produced.
 This executable is a simulator that has been compiled based on the design that was built.
 You can then use this executable to run any compatible RV64 code.
 For instance, to run one of the riscv-tools assembly tests.
 
 .. code-block:: shell
 
-    ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
+    ./simulator-example-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
 
 If you later create your own project, you can use environment variables to build an alternate configuration.
 

From 71b3d7e1e688267d175cdced81307c662fe11f03 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Thu, 29 Aug 2019 18:50:43 -0700
Subject: [PATCH 14/16] Force verilator to produce fragmented cpp files

---
 sims/verilator/Makefile | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile
index 31fc2d41..2fcb79d1 100644
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -59,7 +59,8 @@ VERILATOR_NONCC_OPTS = \
 	+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
 	+define+STOP_COND=\$$c\(\"done_reset\"\) \
 	--assert \
-	--output-split 20000 \
+        --output-split 10000 \
+	--output-split-cfuncs 100 \
 	$(sim_vsrcs) \
 	-f $(sim_common_files)
 
@@ -96,11 +97,12 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR)
 #########################################################################################
 # invoke make to make verilator sim rules
 #########################################################################################
+VERILATOR_MAKEFLAGS=-j8
 $(sim): $(model_mk)
-	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(VLOG_MODEL).mk
+	$(MAKE) $(VERILATOR_MAKEFLAGS) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(VLOG_MODEL).mk
 
 $(sim_debug): $(model_mk_debug)
-	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(VLOG_MODEL).mk
+	$(MAKE) $(VERILATOR_MAKEFLAGS) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(VLOG_MODEL).mk
 
 #########################################################################################
 # create a verilator vpd rule

From 648780601c3b149a2de0f8695be0a936071ab854 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Thu, 29 Aug 2019 22:53:41 -0700
Subject: [PATCH 15/16] Bump boom to version which passes ci

---
 generators/boom | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/generators/boom b/generators/boom
index fb184407..7b68d748 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit fb184407e93183353a3286a8c8ec9bf6660ff352
+Subproject commit 7b68d748b6c09d2403ba500590a8e32f5963c407

From d363ad5a460a84fa920e260b84d420f7bfc749c2 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Thu, 29 Aug 2019 23:04:06 -0700
Subject: [PATCH 16/16] Fix tabs vs spaces in sims/verilator/Makefile

---
 sims/verilator/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile
index 2fcb79d1..3763f627 100644
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -59,7 +59,7 @@ VERILATOR_NONCC_OPTS = \
 	+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
 	+define+STOP_COND=\$$c\(\"done_reset\"\) \
 	--assert \
-        --output-split 10000 \
+	--output-split 10000 \
 	--output-split-cfuncs 100 \
 	$(sim_vsrcs) \
 	-f $(sim_common_files)