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Add notes to docs indicating SoftCore bringup with VCU118 is legacy

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This commit is contained in:
Jerry Zhao
2023-04-20 00:00:42 -07:00
parent 4f5bbdca97
commit d42b195b91
2 changed files with 15 additions and 5 deletions
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10
docs/Advanced-Concepts/Chip-Communication.rst
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@@ -206,8 +206,12 @@ This type of simulation setup is done in the following multi-clock configuration
:start-after: DOC include start: MulticlockAXIOverSerialConfig
:end-before: DOC include end: MulticlockAXIOverSerialConfig
Bringup Setup of the Example Test Chip after Tapeout
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Softcore-driven Bringup Setup of the Example Test Chip after Tapeout
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. warning::
Bringing up test chips with a FPGA softcore as described here is discouraged.
An alternative approach using the FPGA to "bridge" between a x86 host and the test chip is the preferred approach.
Assuming this example test chip is taped out and now ready to be tested, we can communicate with the chip using this serial-link.
For example, a common test setup used at Berkeley to evaluate Chipyard-based test-chips includes an FPGA running a RISC-V soft-core that is able to speak to the DUT (over an FMC).
@@ -222,4 +226,4 @@ The following image shows this flow:
.. image:: ../_static/images/chip-bringup.png
In fact, this exact type of bringup setup is what the following section discusses:
:ref:`Prototyping/VCU118:Introduction to the Bringup Design`.
:ref:_legacy-vcu118-bringup.